RU2117388C1 - Data coding and decoding method and device - Google Patents

Abstract

FIELD: coding devices designed for data compacting systems incorporating decoding device for decoding information generated by coding device. SUBSTANCE: coding device has encoder used to generate code word information in response to data. Coding device also incorporates re- ordering unit generating stream of coded data in response to code word information arriving from encoder. Re-ordering unit has run count re-ordering sub-unit designed to arrange code words in coding sequence and binary digit arrangement sub-unit for aggregating variable-length code words with fixed length alternation and for submitting these fixed- length words in sequence required by decoding device. EFFECT: provision for precise recovery of original data. 121 cl, 33 dwg

Description

 This patent application is partly continuing the application for US patent N 08/172646 under the name "Method and device for parallel encoding and decoding of data" dated December 23, 1993, which, in turn, is partly continuing the application for US patent N 08 / 016035 entitled "Method and device for parallel decoding and encoding of data" dated February 10, 1993

 The invention relates to data compression and decompression systems, in particular, to a method and apparatus for parallel encoding and decoding of data in compression-decompression systems.

 Currently, data compression is widely used, in particular, for storing and transmitting large amounts of data. Many different data compression techniques are known in the art. Compaction methods can be divided into two categories: lossy coding and lossless coding. Lossy coding includes coding, resulting in loss of information, as a result of which accurate restoration of the original data is not guaranteed. With lossless compression, all information is saved, and data is compressed so as to ensure accurate recovery.

 With lossless multiplexing, input characters are converted to output codewords. If summarization is successful, codewords are represented by fewer bits than the number of input characters. Lossless coding methods include vocabulary coding methods (for example, the Lempel-Ziv method), coding with an uneven code, an enumerating code, and a statistical code.

 Statistical code coding refers to any lossless coding method in which they seek to compress data close to the limiting entropy using known or predicted symbol probabilities. Statistics codes include Huffman codes, arithmetic codes, and binary statistics codes. Encoding devices with a binary statistical code are lossless encoding devices that operate on the basis of binary solutions (yes-no), often defined as the most probable character (BWS) and the least probable character (MBC). Examples of binary statistical encoders include an IBM Q encoder and an encoder called a B encoder. Further information on the B encoder can be found in US Pat. No. 5,272,478 to "Method and apparatus for encoding a statistical code" issued by J. D. Allen on December 21, 1993 and owned by the same applicant as the present invention (see also work M .J. Gormish and JD Allen, “Binary Encoding with a State Machine Statistical Code,” summarized in the proceedings of the Conference on Data Compression Methods, published March 30, 1993 in Snowbid, Utah, p.449). A B-encoder is a binary statistical encoding device in which a state machine (a machine with a finite number of states) is used for compression.

 Figure 1 shows a block diagram of a prior art compression and decompression system in which a binary statistical encoding device is used. For encoding, data is entered into the context model 101 (CM). KM 101 converts the input into a series or sequence of binary decisions and provides a context element for each decision. Both the sequence of binary decisions and the contextual elements associated with them are output from CM 101 to the probability estimation module (MOB) 102. MOB 102 receives each context element and generates a probability estimate for each binary decision. A valid probability estimate is usually represented by a class denoted by a P-class. Each P-class is used for a range of probabilities. MOB 102, in addition, determines whether the binary solution (result) is in its most probable state or not (that is, whether the BVS solution matches). The Bit Sequence Generator (GPB) module 103 receives probability estimation signals (i.e., P-class) and determines how likely the binary solution is as input signals. In response to this, the GPU module 103 creates a sequence of compressed data, generating zero or nonzero bits at the output to represent the original input data.

 For decoding, KM 104 provides a context element for MOB 105, and MOB 105, based on the context element, provides a probability class (P-class) for the GPU module 106. The GPU module 106 is connected to receive a probability class. In response to the probability class and compressed data, the GPU module 106 returns a binary digit, symbolizing whether the binary solution (i.e., the event) corresponds to its most probable state or not. MOB 105 receives this binary bit, updates the probability estimate based on the received binary bit, and returns the result to CM 104. CM 104 receives the returned binary bit and uses this returned binary bit to generate the source data and update the context element for the next binary decision.

 One of the problems encountered when using binary statistic code decoders, such as the Q-encoder and IBM B-encoder, is their low speed, even when implemented in hardware. Their operation is based on the use of one large slow-acting feedback circuit. To restart the decoding process, the context model uses the latest decoded data to create the context. In the probability estimation module, context is used to create a probability class. The binary sequence generator uses a probability class and summarized data to determine if the next binary bit represents a likely or unbelievable result. The probability estimation module uses a probable / improbable result to generate a binary digit of the result (and to update the context probability estimate). The binary digit of the result is used in the context model to update the archive of the latest data. All of these steps are required to decode a single bit. Since the context model must expect a binary digit of the result to update its data archive, and can provide the following context, it is necessary to expect decoding of the next binary digit. It is advisable to avoid waiting for the feedback loop to close before decoding the next bit. In other words, it is desirable to simultaneously decode more than one binary bit or codeword to increase the decoding rate of the compressed data.

 Another problem with binary statistic decoders is that variable length data needs to be processed. In most systems, decoded codewords have variable lengths. Or other systems encode variable-length characters (non-encoded data). When processing data of variable length, it is necessary to shift the data at the binary level to provide subsequent correct data for the decoding or encoding operation. These binary-level manipulations in the data stream may require the use of expensive and / or slow-acting hardware and / or software. In addition, in known systems it is required that this bias be implemented in feedback loops that are time critical, which limits the efficiency of the decoding device. It would also be desirable to eliminate the manipulation of the binary level of the data stream from time-critical feedback loops so that parallel processing could be used to increase speed.

 The present invention relates to a lossless sealing and decompression system. In addition, the present invention provides real-time encoding and decoding devices for parallel encoding and decoding of data, respectively. The encoding and decoding devices of the present invention form a balanced parallel entropy system in which both real-time encoding and decoding are performed using hardware with high speed and low cost.

 A method and apparatus for decompression and data compression are proposed. The present invention provides an encoding device for use in a compaction system having a decoding device for decoding information generated by the encoding device. The encoding apparatus of the present invention includes an encoder for generating codewords information in response to data. The encoding device also includes a reordering unit that generates a stream of encoded data in response to the codeword information received from the encoder.

 The reordering unit includes a run count reordering unit designed to arrange codewords in decoding order, and a binary bit arrangement unit for combining variable-length codewords into words with alternating fixed lengths and for outputting words with alternating fixed lengths in the order required by the decoding device.

 The present invention will be better understood from the following detailed description and the accompanying drawings of various embodiments of the invention, which, however, are not given as a limitation of the invention to specific embodiments, but only for explanation and understanding.

 FIG. 1 is a block diagram of known binary statistical encoding and decoding devices; 2 is a block diagram of a decoding system according to the present invention; 3 is a block diagram of a possible embodiment of a coding system according to the present invention; FIG. 4 is a block diagram of a possible embodiment of a decoding system according to the present invention, in which parallel processing of context elements of an encoded signal is performed; 5 is a block diagram of a possible embodiment of a decoding system according to the present invention in which probability classes are processed in parallel; 6 illustrates a non-intermittent code stream according to the present invention; FIG. 7 illustrates a possible embodiment of an interleaved code information stream obtained from an exemplary data set; FIG. Fig. 8 is an example of a probability estimation table and a binary sequence generator for an R-encoder according to the invention; Fig. 9 is a block diagram of a possible embodiment of an encoding device according to the invention; 10 is a block diagram of a possible embodiment of a binary digit generator according to the invention; 11 is a block diagram of a possible embodiment of a reordering block according to the invention; FIG. 12 is a block diagram of a possible embodiment of a reordering run counting unit according to the present invention; 13 is a block diagram of another embodiment of a reordering run counting unit according to the present invention; FIG. 14 is a block diagram of a possible embodiment of a binary digitization unit of the present invention; FIG. 15 is a block diagram of a possible embodiment of a layout logic in accordance with the present invention; FIG. FIG. 16 is a block diagram of an encoder according to the present invention; 17 is a block diagram of a possible embodiment of a decoding system according to the present invention; FIG. 18 is a block diagram of a decoding apparatus of the present invention; FIG. 19 is a block diagram of a possible embodiment of a Reverse Shop Type (FIFO) structure according to the present invention; FIG. 20 illustrates a possible embodiment of a decoding pipeline according to the present invention; FIG. 21 illustrates a possible embodiment of a decoding apparatus according to the present invention; FIG. 22 is a block diagram of a possible embodiment of a shifting device according to the present invention; FIG. 23 is a block diagram of another embodiment of a shifting device according to the present invention; FIG. 24 is a block diagram of a system having an external context model; FIG. 25 is a block diagram of another system having an external context model; FIG. 26 is a block diagram of a possible embodiment of a decoding apparatus of the present invention; Fig.27 is a block diagram of a possible embodiment of a decoding device with separate binary generators; FIG. 28 is a block diagram of a possible embodiment of a binary digit generator according to the present invention; FIG. Fig.29 is a block diagram of a possible embodiment of the present invention block long run; FIG. 30 is a block diagram of a possible embodiment of the present invention of a short run block; FIG. 31 is a block diagram of a possible embodiment of an initialization and control logic in accordance with the present invention; FIG. Fig. 32 is a block diagram of a possible embodiment of reordering data using a decoding tracking device: Fig. 33 is a block diagram of another embodiment of a reordering unit; Fig. 34 is a block diagram of another embodiment of a reordering block in which a combined order is used; Fig. 35 is a block diagram of a wide band system using the present invention; FIG. 36 is a block diagram of a band matching system in which the present invention is used; Fig. 37 is a block diagram of a real-time television system using the present invention; Fig. 38 illustrates a possible embodiment of a coded data storage device according to the present invention; Fig. 39 is a decoding timing diagram of the present invention.

 A method and apparatus for parallel coding and decoding of data are described. In the following description, numerous specific details are given, such as certain numbers of binary bits, number of encoders, specific probabilities, data types, and so on, in order to provide a thorough understanding of the preferred embodiments of the present invention. Those skilled in the art will appreciate that the present invention can be practiced without these specific details. In addition, well-known schemes are shown in the form of flowcharts, and not in detail, for greater clarity of presentation of the present invention.

 Some parts of the following detailed description are presented in the form of algorithms and symbolic representations of operations with binary bits of data in the memory of a computer. These algorithmic descriptions and representations are the means used by specialists in the data processing technique to more effectively express the essence of their work for other specialists in this technical field. The algorithm is considered as a sequence of processing steps leading to the desired result. These stages characterize physical operations on physical objects. These objects can take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and other operations performed. Sometimes these signals are conveniently called binary digits, values, elements, symbols, signs, terms, numbers, or similar concepts.

 However, it must be borne in mind that all these and similar terms should be associated with the corresponding physical objects and simply represent their convenient notation. Unless otherwise noted, as is apparent from the following description, it should be understood that throughout the present invention, discussions are used using terms such as "processing", "calculation", "calculation", "definition", "display" or the like , relate to the operation and processes of a computing system or similar electronic computing device that manipulates data and converts data represented as physical (electronic) quantities inside registers and storage devices of computing systems Into other data similarly represented as physical quantities within the registers or memories of the computing system or other such storage, transmission or display information devices.

 The present invention also relates to a device for performing operations therein. This device can be specially created for the required purposes, or it can contain a universal computer, selectively driven or reconfigurable using a computer program stored in a computer. The algorithms and indicators available in it are not inherently associated with any particular computing machine or other device. Various universal computers can be used with programs in accordance with the provisions set forth herein, or it may be convenient to create a specialized device to perform the required steps of this method. From the description below, the necessary structure of these various computers will be clear. In addition, the present invention is described without reference to any particular programming language. It should be understood that a variety of programming languages can be used to implement the invention.

 The present invention provides a parallel statistical coding system. The system includes an encoding device and a decoding device. In one embodiment of the invention, the encoder encodes the data in real time. Similarly, in one embodiment, a decoding apparatus of the present invention decodes real-time data. Real-time encoding and decoding devices together form a balanced coding system.

 The present invention relates to a system that decodes losslessly encoded data in parallel. Data is decoded in parallel using multiple decoding resources. Each of the plurality of decoding resources is allocated data (eg, codewords) from the data stream for decoding. The allocation of the data stream occurs continuously, the decoding resources decode the data simultaneously, thereby parallel decoding the data stream. In order to enable such data allocation for efficient use of decoding resources, the data stream is streamlined. This process is called data stream parallelization. Data sequencing allows each decoding resource (means) to decode some or all of the encoded data without waiting for feedback from the context model.

 In FIG. 2 shows a decoding system according to the present invention that does not use the slow feedback loop known in the art. An input buffer 204 receives encoded data (i.e., code words) and a feedback signal from a decoder 205 and supplies the encoded data in a predetermined order (e.g., in a context element order) to a decoder 205 according to the present invention, which decodes the encoded data. Decoding device 205 includes a plurality of decoding units (e.g., 205A, 205B, 205C, and so on).

 In one embodiment, each of the decoding units 205A, 205B, 205C, etc. provided with data for a group of contexts. Each of the decoding blocks in the decoding device 205 is provided with encoded data for each context sampling element in its context group from the input buffer 204. Using this data, each decoding block 205A, 205B, 205C, etc. generates decoded data for its group of contextual elements. A context model is not required to associate encoded data with a particular group of context elements.

 The decoding device 205 sends the decoded data to the decoded data storage 207 (e.g., 207A, 207B, 207C, etc.). Note that the decoded data storage 207 may store intermediate data that is neither encoded nor unencoded, such as run accounts. In this case, the decoded data storage 207 stores the data in a compressed, but not in a form encoded by a statistical code.

 Operating independently, the context model 206 is connected to receive previously decoded data from the decoded data storage 207 (i.e., 207A, 207B, 207C, etc.) in response to feedback signals that it sends to the decoded data storage 207. Therefore, there are two independent feedback circuits; one between the decoding device 205 and the input buffer 204, and the second between the context model 206 and the decoded data storage 207. Since the large feedback loop is removed, the decoders in the decoding device 205 (for example, 205A, 205B, 205C, etc.) are able to decode their associated codewords as soon as they receive them from the input buffer 204.

 The context model provides a memory portion of the encoding system and divides the data set (e.g., images) into various categories (e.g., context-sensitive data encoding elements) based on a storage device. In the present invention, contextual elements are considered independent ordered data sets. In one embodiment, each group of contextual elements of encoded data has its own probability estimation model, and each contextual element has its own state (where probability estimation models are separated). Therefore, each context element of the encoded data may use a different probability estimation model and / or a binary sequence generator.

 Thus, data is ordered or parallelized, and data from the data stream is assigned to individual decoders for decoding.

 Adding concurrency to the classic statistical coding model.

 To parallelize the data stream, data can be divided in accordance with any of the sequences: contextual, probabilistic, mosaic, codewords (based on codewords), etc. The reordering of the encoded data stream is independent of concurrency, the method used for concurrency of data, or probability at any other point. In FIG. 3 shows a parallel coding device of a coding system according to the present invention, into which data differentiated by a context model (CM) is received.

 As shown in FIG. 3, a parallel context-dependent encoder comprises a context model (CM) 214, probability estimation modules (MOBs) 215-217, and bit sequence generators (GPUs) 218-220. KM 214 is connected to receive encoded input data. KM 214 is also connected to modules 215-217. MOB 215-217, in addition, are associated with GPB 218-220, respectively, which yield encoded streams 1, 2, and 3, respectively. Each pair of MOB and GPB contains an encoder. Therefore, a parallel encoder is shown with three encoders. Although only three parallel encoders are shown, any number of them can be used.

 KM 214 divides the data stream into different contexts in the same way as a regular KM, and sends multiple streams to parallel coding hardware. Individual contexts or groups of contexts are routed to separate probability estimation modules (MOBs) 215-217 and bit sequence generators (GPBs) 218-219. Each of GPB 218-220 gives an output stream of encoded data.

 In FIG. 4 is a block diagram of one embodiment of a decoding device of a decoding system of the present invention. Figure 4 shows a context-dependent parallel decoding device having a GPB 221-223, MOB 224-226 and KM 227. Coded streams 1-3 are supplied to GPB 221-223, respectively. GPB 221-223 are also associated with MOB 224-226, respectively. MOB 224-226 are connected to KM 227, which provides reconstructed input data at the output. The input signal comes from several code streams shown as code streams 1-3. One codestream is allocated to each MOV and GPB. Each of GPB 221-223 returns a binary bit representing a choice of two alternatives, depending on whether it is in its most probable state, which MOB 224-226 uses to return decoded binary bits (for example, a choice of two alternatives). Each of MOB 224-226 is associated with one of the GPB 221-223, showing which code must be used to generate the data stream from its input code stream. KM 227 creates a decoded data stream by selecting the decoded binary bits from the bit stream generators in the proper sequence, thereby recreating the original data. Thus, KM 227 receives a binary bit of decompressed data from the corresponding MOV and GPB, actually reordering the data in the original order. Note that this circuit is controlled in the opposite direction relative to the data stream. GPB and MOV can decode data before it is required by KM 227, leaving one or more binary bits ahead. Alternatively, KM 227 may request (but not receive) a binary bit from one GPB and MOB, and then request one or more binary bits from other GPB and MOB before using the originally requested binary bit.

 The configuration shown in FIG. 4 provides for a rigid connection of the MOB and GPB. The 1BM Q encoder is a good example of an encoder having hardwired MOBs and GPBs. Local feedback circuits between these two nodes do not have a limiting effect on the characteristics of the system.

 In another design option, MOVs could differentiate the data and send them to parallel blocks of the GPB. Thus, there can only be one CM and one MOU, and the GPB is duplicated. With this method, adapted Huffman coding and state machine coding can be used.

 Figure 5 shows a similar decoding system in which the MOB is used to differentiate data and send them to parallel GPBs. In this case, the probability classes are processed in parallel, and each bit sequence generator (GPB) is allocated to a certain probability class and receives information about the result. As shown in FIG. 5, encoded data streams 1–3 are supplied to the corresponding from a plurality of generators bit sequences (for example, GPB 232, GPB 233, GPB 234, etc.) that are connected to receive them. Each of the bit sequence generators is connected to the MOB 235. The MOB 235 is also connected to the CM 236. In this configuration, each of the bit sequence generators decodes the encoded data, and the decoding results are selected by the MOB 235 (instead of the CM 236). Each of the bit sequence generators receives encoded data from a source associated with one probability class (that is, where the encoded data could be from any context element). MOB 235 selects bit sequence generators using a probability class. The probability class prescribes the context elements of the encoded data provided for it by the KM 236 model. Thus, the decoded data is obtained by parallel processing of the probability classes.

 Numerous implementations exist for parallel decoding systems of the present invention. In one embodiment, encoded data streams corresponding to multiple contextual encoded data elements may be interleaved into a single stream ordered by requests from different encoders. In one embodiment of the present invention, the encoded data is arranged so that each encoder constantly receives data, even if the encoded data is supplied to the decoder in one stream. It should be noted that the present invention operates with all types of data, including video data.

 With small, simple encoders that can be easily duplicated in integrated circuits, encoded data can be quickly decoded in parallel. In one embodiment of the invention, the encoders are hardware-based using Operational Programmable Logic Matrix Crystals (MLEEP) or a standard application-oriented integrated circuit chip (ISPS). The combination of parallelism and simple bit sequence generators allows decoding of encoded data at a speed exceeding the speed in existing decoding devices, while maintaining or exceeding the compression efficiency of existing decoding systems.

 Channel sequencing of multiple data streams.

 There are many different design issues and problems that affect system performance.

 Some of them will be mentioned below. However, in those shown in FIG. 3 and 4 (and 5) embodiments, multiple code streams are used. You can imagine systems with parallel channels that can provide this embodiment: lines with many telephones, many heads on drives, etc. On some systems, only one channel is available or usable. In fact, if many channels are required, then the use of the frequency band may be insufficient due to the packet nature of the individual code streams.

 In one embodiment, code streams are concatenated (articulated) and sent continuously to a decoding device. The start header contains location indicators for the start bit of each stream. In FIG. Figure 6 shows a possible arrangement for arranging the location of this data. As shown in FIG. 6, here three pointers 301-303 show the initial location in the articulated code of the code streams 1, 2, and 3, respectively. The buffer contains the complete compressed data file provided for the decoding device. If necessary, code words are retrieved at the proper location using the proper pointer. The pointer is then updated for the next codeword in this codestream.

 It should be noted that this method requires storing in the decoding device and for practical purposes in the encoding device the full encoded frame (data block). If a real-time system or a packet-free data stream is required, then two frame buffers can be used for grouping in both encoding and decoding devices.

 Data streamlining to streamline codewords.

 Note that the decoding device decodes the code words in a predetermined deterministic order. In parallel coding, the codestream request stream is deterministic. Thus, if codewords from parallel codestreams can be alternated in the correct order in the encoder, then one codestream is sufficient. Code words are supplied to the decoding device in the same manner on a “strictly on time” basis. In the encoder, the model of the decoder determines the order of the code words and composes the code words into a single stream. This model may represent a valid decoding device.

 A problem with supplying data to parallel decoding elements occurs if the data is of variable length. Unpacking a variable-length codeword stream requires the use of a bit-shift register to align codewords. Bit shift registers are often expensive and / or have low performance if they are hardware-based. The control of the bit shift register depends on the size of a particular codeword. This feedback control loop interferes with the rapid implementation of a variable length shift. The positive qualities of supplying a single stream to a plurality of decoding devices cannot be realized if the process of unpacking a stream is carried out in a single bit-shift register, which does not have sufficient speed to work in conjunction with a plurality of decoding devices.

 The solution proposed in this invention is to separate the problem of distributing encoded data among parallel encoders from alignment of variable-length codewords for decoding. Code words in each independent code stream are arranged into words of a fixed length, called words with alternation (alternation). At the decoding end of the channel, these words with interleaving can be distributed across parallel blocks of decoders with high-speed data lines on hardware and with a simple control circuit.

 It is convenient to choose the length of the interleaved word greater than the maximum length of the codeword so that each interleaved word contains at least a sufficient number of binary bits for the whole one codeword. Interleaved words may contain possible codewords and parts of codewords. 7 shows the interleaving of an exemplary set of parallel code streams.

 These words are interleaved in accordance with the needs of the decoding device. Each independent decoder receives an integer interleaved word. The bitwise offset operation is now performed locally in each decoder, maintaining system parallelism. Note that in FIG. 7, the first codeword in each interleaved word is the lowest remaining codeword in the set. For example, the first interleaved words come from codestream 1, starting with the lowest codeword (i.e., N 1). It is followed by the first interleaved word in codestream 2, and then the first interleaved word in codestream 3. However, the next lowest codeword, not completely contained in the already ordered interleaved word, is N 7. Therefore, the next word in the stream is the second interleaved codestream word 2.

 In another embodiment of the invention, the order in which a subsequent set of interleaved words (for example, a codeword starting with codeword N 8 in stream 1, a codeword starting with codeword N 7 in stream 2, codeword starting with codeword N 11 in stream 3) is introduced into the interleaved codestream, based on the first codeword of the previous set of interleaved words (for example, a codeword starting with codeword N 1 in stream 1, a codeword starting with codeword N 2 in stream 2, code word start arising from codeword N 4 in stream 3) and is ordered from the interleaved word with the first codeword of the lowest number to the interleaved word with the first codeword of the highest number. Therefore, in this case, since the first was an interleaved word starting with the code word N 1, the next interleaved word in stream 1 is the first of the second group of interleaved words to be introduced into the interleaved stream, followed by the interleaved word in stream 2, and then the next interleaved word in stream 3. It should be noted that after introducing the second group of interleaved words into the interleaved stream, the next interleaved word in stream 2 may be the next interleaved word entered into the stream, since the code The new word N 7 is the lowest codeword of the second set of interleaved words (followed by the code word N 8 in stream 1 and then the code word N 11 in stream 3).

 Using a valid decoder as a model designer for a data stream takes into account all construction and delay options when creating an interleaved stream. This does not increase the cost of duplex systems having both encoding and decoding devices. It should be noted that this can be generalized for any parallel set of information words of variable length (or different sizes), which are used in a deterministic order.

 Types of codes and bit sequence generators for parallel decoding.

 In the present invention, existing encoders such as Q encoders and B encoders can be used as elements for generating a sequence of bits that are duplicated in parallel. However, other codes and encoders may be used. The encoders and associated codes used in the present invention are simple encoders. The present invention provides the advantages of using a bit sequence generator with a simple code instead of a complex code, such as the arithmetic code used in the Q encoder, or codes with a large number of states used in the B encoder. Simple code has the advantage that the hardware implementation has much higher performance, is simpler in design and requires less silicon elements than in the case of complex code.

 Another advantage of the present invention is that coding efficiency can be improved. A code that uses a limited amount of state information cannot fully match the Shannon entropy limit for each probability. Codes implemented in hardware are known in the art that allow a single bit sequence generator to manipulate multiple probabilities or contexts, but having limitations that reduce coding efficiency. Elimination of the restrictions required for a large number of contexts or probability classes allows the use of codes that are more consistent with the Shannon entropy limit.

 R codes.

 The code (and encoder) used in one embodiment of the present invention is called an R code. R codes are adaptive codes that convert a variable number of identical input characters into a code word. In an embodiment of the invention, the R codes are parameterized so that a large number of different probabilities can be manipulated with a single decoding device. Moreover, the R codes of the present invention can be decoded using simple high-speed hardware.

 In the present invention, R codes are used by an R encoder to perform encoding or decoding. In one embodiment, the R encoder is a combined bit sequence generator and a probability estimator. For example, in FIG. 1, an R-encoder may include combining a probability estimator 102 and a bit sequence generator 103 and combining a probability estimator 105 with a bit sequence generator 106.

 Code words represent runs of the most probable character (BVS). BVS represents the result of a decision of two alternatives with a probability of more than 50%. On the other hand, the least probable symbol (MVS) represents the outcome of a decision of two alternatives with a probability of less than 50%. It should be noted that when two results are equally probable, it does not matter which of them is indicated by BVS or MVS, since both the encoding and decoding devices make the same designation. The resulting sequence of binary bits in the compressed file is shown in Table 1 for this parameter denoted by MAXRUN (maximum number of runs).

 When encoding, the number of DSS in the run is calculated by a simple counter. If this count is equal to the MAXRUN count, the code word 0 is sent to the code stream, and the counter returns to its original state. If MVS is encountered, then 1 with subsequent N binary digits is sent to the code stream, which uniquely describe the number of BVS symbols before MVS. (It should be noted that there are many ways to assign N bits to describe the length of the run.) Once again, the counter is reset. It should be noted that the number of bits required for N depends on the value of MAXRUN. In addition, note that you can use the complement of up to 1 code words.

 When decoding, if the first binary bit in the code stream is 0, then the MAXRUN value is placed in the BVS counter, and the MBC value is reset. Then 0 binary digit is discarded. If the first binary digit is 1, then the following binary digits are examined to extract N binary digits, and the corresponding count (N) is placed in the BVS counter, and the MBC indicator is set. Then the binary bits of the codestream containing codeword 1 are discarded.

R-codes are generated according to the table. 1 rules. It should be noted that the description of this R-code Rx (k) is determined by the parameter MAXRUN. For instance:
MAXRUN for Rx (k) = x • 2 ^k-1 ,
thus
MAXRUN for R2 (k) = 2 • 2 ^k-1 ;
MAXRUN for R3 (k) = 3 • 2 ^k-1 ,
etc.

Note that R codes are a subset of the Golomb codes. Note also that in Rice codes only R2 (*) codes are used. The R codes corresponding to the present invention allow the use of both R2 (k) and R3 (k) codes, as well as other Rn (k) codes, if required. In one embodiment, codes R2 (k) and R3 (k) are used. It should be noted that Rn exists for n = 2 and n equal to any odd number (for example, R2, R3, R5, R7, R9, R11, R13, R15). In one embodiment of the invention, for the code R2 (k), the run count r is encoded by the variable N, the run count r is described in binary digits, so 1N is represented in + 1 binary digits. In yet another embodiment of the invention, for the R3 (k) code, N binary bits may contain 1 binary bit to indicate if n <2 ^(k-1) or n ≥ 2 ^(k-1) and either k-1 or binary bits to display the run count of r, so that the variable N is represented by the total number of k or k + 1 binary bits, respectively. In other embodiments of the invention, a complement of up to 1 value N can be used in the codeword. In this case, the BVS tends to create code streams with a large number of 0, and the MVS tends to create code streams with a large number of 1.

 In the table. 2, 3, 4, and 5 depict some effective R codes used for one embodiment of the present invention. It should be noted that other run duration codes can also be used in the present invention. An example of an alternative run length code for R2 (2) is shown in Table. 6. Tables 7 and 8 show examples of codes used in an embodiment of the invention.

 Probability estimation module for R-codes.

In an embodiment, the code R2 (0) does not encode: input 0 is encoded to 0, and input 1 is encoded to 1 (or vice versa) and is optimal for probabilities of 60%. Code R2 (1) of the currently preferred embodiment is optimal for probabilities close to 0.707 (i.e. 70.7%), and R3 (1) is optimal for probability 0.794 (79.4%). The code is optimal for a probability of 0.841 (84.1%). Tab. 9 displays a run-length code that is close to optimal, where the skew of probability is determined by the following expression:
Skew of probability = -log ₂ (MBC).

 Note that the codes turn out to be close to optimal in the sense that the probability range, as shown by the bias of probability, spans the interval relatively evenly, even if the optimal probabilities do not differentiate as much at higher values of k as at lower values of k.

 Reference is made to the probability at which the R code is optimal. In fact, only R2 (2) corresponds to the entropy curve. The real consideration is which probability range a particular R-encoder represents better than all other R-encoders in this class. The following tables provide probability ranges for the code class R2 and code class R2 and R3.

 For the code class R2 from 0 to 12, the ranges are presented in Table 10. For example, when only the codes R2, R2 (0) are used, it turns out to be better when 0.50 ≤ probability ≤ 0.6180. Similarly, R2 (1) is better when 0.6180 ≤ probability ≤ 0.7862.

 For the class of codes R2 and R3, the solutions are presented in Table 11. For example, when codes R2 and R3 are used, R2 (1) is better when 0.6180 ≤ probability ≤ 0.7549.

 R2 (k) for fixed k is called the run length code. However, fixed to is only better for the probability range. It is noted that when the encoding is carried out near the optimal probability, the code words “0” and “1N” are used with approximately the same frequency in the R code corresponding to the present invention. In other words, half the time, the R-encoder corresponding to the present invention outputs one code, and the other half-time, the R-encoder outputs another code. By examining the codewords with the numbers “0” and “1N”, a determination can be made as to whether the best code is used. That is, if the output contains too many code words "1N", then the run length is too long, on the other hand, if the output contains too many code words 0, then the run length is too small.

 The probability estimation model used by Langdon examines the first binary bit of each codeword to determine whether the source of the current estimate is higher or lower (see JJ Langdon's work “Adaptive Run-Length Encoding Algorithm”, IBM Technical Discovery Bulletin, Volume 26, N 7B, December 1983). Based on this definition, k increases or decreases. For example, if a codeword indicating BWS is detected, the probability score is too low. Therefore, according to Langdon, k is increased by 1 for each codeword 0. If a codeword is detected showing less than MAXRUN BVS followed by MVS (for example, codeword "1N"), the probability score is too high. Therefore, according to Langdon, k decreases by 1 for each codeword 1N.

 The present invention provides a more complex probability estimate than simply increasing or decreasing k by 1 of each codeword. The present invention includes a state (mode) of a probability estimation module that determines a code to use. Many states (modes) can use the same code. Codes are assigned to states using a state table or state machine.

 In one embodiment of the present invention, a probability estimate changes the state of each output word. Thus, the probability estimation module increases or decreases the probability estimate depending on whether the codeword starts from 0 or 1. For example, if the codeword is “0” at the output, the probability estimate of the BVI increases. On the other hand, if the codeword represents “1” at the output, the probability estimate of the DSS is reduced.

 In the well-known Langdon encoder, only the R2 (k) codes are used and an increase or decrease in k is made for each codeword. As an alternative to the present invention, codes R2 (k) and R3 (k) are used together with a state table or a state machine, which makes it possible to adjust the rate of adaptation to the application. That is, if there is a small amount of stationary data, adaptation should be faster to obtain better coding, and if there is more stationary data, the adaptation time may be longer, so you can choose the coding to achieve better compression of the rest of the data. Note that in cases where variable amounts of state changes can occur, special characteristics of the applications can also affect the rate of adaptation. Due to the nature of the R codes, the evaluation of R codes is simple and requires little technical support, while at the same time it has a very high power. On Fig shows this graph of coding efficiency (the length of the code is normalized relative to the entropy) depending on the likelihood of BVS. In FIG. 40 shows how some of the R codes of the present invention span a probability interval. As an example, FIG. 40 shows that in the case of a probability of BVI of approximately 0.55, the efficiency of the R2 (0) code is 1.01 (or 1% worse) of the entropy limit. In contrast, the R2 (1) code has an efficiency of 1.09 (or 9% worse) than the entropy limit. This example shows that using the wrong code for this particular case of low probability leads to a loss of 8% coding efficiency.

 The inclusion of R3 (k) codes makes it possible to cover a greater probability range with higher efficiency. In FIG. 8 shows an exemplary table of estimation and probability states corresponding to the present invention. Consider FIG. 8, in which the probability estimation state table shows both the state number counter and the code associated with each of the individual states in the table. It should be noted that the table includes both positive and negative states. The table shows the presence of 37 positive states and 37 negative states, including zero states. Negative states have BVS values different from positive states. In one embodiment, negative states can be used when BVI is 1, and positive states can be used when BVI is 0, or vice versa. Note that shown in FIG. 8, the table is only an example and that other tables may have more or less states and a different arrangement of states.

 In the initial position, the encoder is in state 0, which means the code R2 (0) (that is, there is no code) to estimate the probability of 0.50. After each processing of the codeword, the state counter obtains a positive or negative increment depending on the first binary digit of the codeword. In one embodiment of the invention, the codeword 0 increases the counter of the number of states, the beginning of the codeword from 1 decreases the counter of the number of states. Therefore, each codeword forces a state change using a state count. In other words, the probability estimation module changes state. However, successive states may be associated with the same code. In this case, the probability estimate is performed without changing the codes with each codeword. In other words, the state changes with each codeword; however, at certain points, the state is set to the same probabilities. For example, all states from 5 to -5 use the R2 (0) code, while states 6 to 11 and -6 to -11 use the R2 (1) code. Using the state table of the invention, the probability estimate can remain in the same encoder in a non-linear fashion.

 It should be noted that for lower probabilities, more states with the same R code are included. This is because the loss of efficiency when using the wrong code at low probabilities is greater. The nature of the state table of run length codes is to switch between states after each codeword. In the state table, compiled to change codes with each state change, when switching between states at lower probabilities, the code switches between a code that is very close to the limit of entropic efficiency and a code that is far from the limit of entropic efficiency. Thus, a penalty (expressed as the number of bits of encoded data) can lead to a transition between states. Existing probability estimation modules such as the Langdon probability estimation module lose their characterization due to such a fine.

 In codes with a higher probability of run length, the penalty for using the wrong code is not so large. Therefore, in the present invention, additional states are added at lower probabilities, so that changes in switching between two correct states increase, thereby reducing coding inefficiency.

 Note that in some embodiments, the encoder may have an initial probability estimation state. In other words, the encoder may begin to operate in a predetermined one of the states, such as state 18. In one embodiment, another state table may be used, so that some states may be used for the first few characters in order to ensure quick adaptation. The second state table can be used for the remaining characters for the purpose of slow adaptation to ensure fine tuning of the probability estimate. Thus, the encoder may be able to more likely use a more efficient code in the encoding process. In another embodiment, the codestream may establish an initial probability estimate for each context. In one embodiment, positive and negative increments are not produced according to a fixed number (e.g., 1). Instead, the state of the probability estimate can be increased by a variable number in accordance with the amount of data already encountered or the amount of data change (stability). Examples of such tables are presented in table. 22 - 26.

 If the state table is symmetric, as shown in FIG. 8, an example table, then only half of it (including the zero state) needs to be stored or implemented in the hardware. In one embodiment of the invention, the number of states is stored in the form of complementing the sign magnitude (1) to take advantage of symmetry. Thus, you can use the table, taking the absolute value of the number of additions to one to determine the state and checking the sign to determine whether BVS is 1 or 0. This makes it possible to reduce the amount of hardware required for a positive or negative state increment, since it is used to index the table the absolute value of the state, and the calculation of the absolute value of the number of additions to unity is trivial. In another embodiment, the state table can be replaced by a hard-wired or programmable state machine for greater hardware efficiency. A hard-mounted state of a code converter characterizes one of the state table implementations.

 General characteristics of a balanced parallel statistical coding system.

 The present invention provides a balanced parallel statistical coding system. The system of parallel statistical coding includes both real-time coding and real-time decoding, performed using hardware with high speed and low cost. The present invention can be used in numerous lossless coding applications, including but not limited to real-time compaction and decompression of data on rewritable optical discs or magnetic disks, real-time compaction and decompression of computer network data, real-time compaction and decompression the time scale of the image data in the memory of a compressed group of data in a multifunction machine (for example, in a photocopier, fax machine, an analyzing device, a printing device, etc.) and real-time compaction and decompression of audio data.

 Some attention is required to characterize the encoder. Its design and implementation of coding is very simple, which allows you to achieve a certain speed of receipt of the source data output to the channel with a fairly fast data coding. However, in many applications, the challenge is for the encoder to efficiently use the encoded data channel. The use of the encoded data channel is influenced by the maximum packet rate, the source data interface, the speed of the encoder and the achieved degree of data compression. The influence of these influences must be considered for a certain local amount of data, which depends on the provided buffering in the encoding device. It is desirable to have an encoding device that effectively uses the channel of encoded data while maintaining the speed of the encoding device and high compression, while ensuring maximum packet transfer rate.

 In the following description, an encoding device according to the present invention is disclosed. A decoding device that can be used with an encoding device is also described.

 Real-time coding in the present invention.

 In FIG. 9 is a block diagram of a coding system according to the present invention. In one embodiment of the invention, an encoder according to the present invention performs real-time encoding. Shown in FIG. 9, the encoding system 600 includes an encoding device 602 connected to a context model (CM) and a state memory 603 for generating encoded information in the form of codeword information 604 in response to the source data 601. The codeword information 604 is received by the reordering unit 606, which is connected to the reordering memory 607. In response to the codeword information 604, the reordering unit 606, together with the reordering memory 607, generates a stream of encoded data 608. It should be noted that YSTEM encoding 600 according to the invention is not limited to operating with the code words, but may in other embodiments handle discrete analog waveforms, combinations of bits of the variable length communication channel symbols, alphabets, events, etc.

 Encoding device 602 includes a context model (CM), a probability estimation mechanism (MOB), and a bit sequence generator (GPB). The context model and the MOB (probability estimation mechanism) in the encoder 602 are essentially identical to the elements in the decoder (except for the direction of the data stream). The binary generator of the encoder 602 is similar to the binary generator of the decoder and is described below. The result of encoding by encoder 602 is an output from zero or more bits that represent the source data. In one embodiment of the invention, the output of the bit sequence generator further includes one or more control signals. These control signals provide a control circuit for data in a sequence of binary bits. In one embodiment of the invention, the codeword information may include an indication of the start of the run and an indication of the end of the run, a codeword and an index identifying the count of the runs (as related to the context or probability class) for the codeword. One embodiment of a bit sequence generator according to the present invention is described below.

 The reordering unit 606 receives the binary bits and control signals generated by the bit sequence generator (if any) of the encoder 602, and generates encoded data. In one embodiment of the invention, the output encoded data of the reordering unit 606 comprises an interleaved word stream.

 In one embodiment, the reordering unit 606 has two functions. The reordering unit 606 moves the codewords from the end of the runs created by the encoder to the start of the runs, as required by the decoder, and combines the variable-length codewords into interlaced words having a fixed length and sends them to the output in the proper order required for a decoding device.

 In the reordering unit 606, a temporary reordering memory 607 is used. In one embodiment of the invention, where encoding is performed on a workstation, the capacity of the temporary reordering memory may be more than 100 megabytes. In a balanced system according to the present invention, the temporary reordering memory 607 has significantly lower capacity (e.g., approximately 1 kilobyte) and is constant. Thus, in one embodiment of the invention, real-time coding is performed using a constant amount of memory, even if it increases the memory needed by the decoding device or for the bit rate (for example, when output is performed before the completion of the run). The decoding apparatus of the present invention is capable of determining the actions of the limited memory of a reordering block using, for example, implicit, explicit, or intra-stream signaling (as described below). The reordering unit 606 has limited memory used for reordering, but the “required” memory is not limited. It is necessary to take into account both the influence of limited memory in relation to the end of the run with the aim of starting the run queue, and in relation to the reordering of interleaved words.

 In one embodiment of the invention, the encoding system of the present invention (and the corresponding decoding system) performs encoding (or decoding) using a single integrated circuit. In another embodiment, a single integrated circuit comprises an encoder system according to the present invention, including its encoding and decoding devices and memory. To provide encoding, a separate external storage device may be additionally used. A multi-chip module or integrated circuit may contain both encoding-decoding hardware and a storage device.

 A coding system according to the present invention can increase the effective bandwidth up to a value determined by the coefficient N. If the achieved compression is less than N: 1, then the data coding channel will be fully utilized, but the resulting increase in the effective bandwidth is only equal to the degree of compression. If the achieved compaction is greater than N: 1, then an effective bandwidth with an additional overwrite bandwidth is provided. In both cases, the achieved compression should be provided over the entire local data region, determined by the amount of buffering available in the coding system.

 In FIG. 10 shows one embodiment of an encoder binary generator according to the present invention. The binary generator 701 is connected to receive as input signals of the probability class and an unencrypted binary bit (for example, an indication of BVS or MVS). In response to the input signals, a generator 701 provides a plurality of signals. Two of the output signals represent control signals indicating the start of the run and the end of the run (each code word represents the run), the start signal 711 and the end signal 712. The run can be started and terminated at the same time. When the run starts or ends, the output signal “index” 713 contains an indication of the probability class (or context) for the non-encoded binary bit. In one embodiment, the output of index 713 represents the combination of a probability class for a binary digit and the identification of a data bank for systems in which each probability class is duplicated in several data banks of a storage device. The output of codeword 714 is used to output the encoded word from binary generator 701 when the run ends.

 The memory 702 is connected to a binary generator 701 and contains a run count for a given probability class. During binary generation, the binary generator 701 reads from the memory 702 using an index (e.g., a probability class). After reading from the memory 702, the binary generator 701 generates binary bits as follows. Firstly, if the run count is zero, a start signal 711 is issued, indicating the start of the run. Then, if the non-encoded binary bit is equal to MVS, then an end signal 712 is generated, indicating the end of the run. In addition, if the non-encoded binary bit is the least probable character (MBC), an output codeword 714 is generated to indicate that the codeword is the codeword “1N” and the run count is cleared, for example, set to zero (since this is the end of the run ) If the non-encoded binary bit is not equal to MVS, then the run count is incremented, and the check determines whether the run count is equal to the maximum run count for the code. If so, then an end signal 712 is output, the output of codeword 714 is set to zero, and the run count is cleared (for example, the run count is set to zero). If as a result of the check it is determined that the number of runs is not equal to the maximum value for the code, then the run count receives a positive increment. Note that the indexing signal 713 corresponds to a probability class adopted as an input signal.

 In the present invention, the triggering of the code words 1N is carried out so that their length can be determined without any additional information. Tab. 12 illustrates codewords “1N” representing codewords R3 (2) for decoding and encoding devices. The decoding device expects that the binary digit “1” in the codeword “1N” will be MVS and that part of the count N will be in the proper order BVS ... MVS. In decoding order, a variable-length codeword cannot differ from zero filling without knowing which specific code is used. In coding order, the codeword is reversed, and the position of the high order bit “1” indicates the length of the codewords “1N”. To generate codewords in coding order, the complement of the count value must be reversed. This can be done by reversing the 13-bit account and then shifting it so that it is compatible with the MVS. As described in detail below, the binary unit arranges the code words backward, according to the decoding order. However, this reversal of codewords does not complicate the block arrangement of the binary digits 606, since it must carry out the shift in any way.

 For R3 codes, generating the code words “N2” also requires that the binary digit following “1” indicates whether a short or long count is present.

 Using numerous banks of memory data, the present invention allows you to work in a pipelined mode. For example, in the case of a multi-port storage device, a read operation is performed in a storage device for an unencrypted bit, while a write operation is performed in a storage device for a previous unencrypted bit.

 Create an Altera AHDL Sample.

 One embodiment of an encoder binary generator according to the present invention includes a user programmable gate array (FPGA). During creation, all codes R2 and R3 are processed up to R2 (12). The source code for AHDL (hardware description language Altera) is printed below.

 As shown in FIG. 16, this diagram contains several parts. The first part of the CBG EN is the main part of the circuit, in which there is a logic circuit 1301 for starting, ending and continuing the run. The second part of KEXPAND 1302 is used to extend the probability class to the maximum run length, a variable-length mask, and the length of the first long codeword for R3 codes. The KEXPAND 1302 function is identical to the function of the decoder of the same name. The third part of the LPSCW 1303 receives the count value and the probability class information as input signals and generates the appropriate codeword "1N".

 In this scheme, two conveyor stages are used. During the operation of the first pipeline stage, the count is incremented, the probability class is expanded, and the long codewords R3 are subtracted and compared. All other operations are carried out during operation of the second conveyor cascade (see table 13).

 In FIG. 11 is a block diagram of one embodiment of a reordering block. The reordering unit 606 comprises a reordering unit of the run count 801 and a binary bit compaction unit 802. The reordering unit of the run count 801 moves the code words from the end of the runs, as created by the encoder, to the start of the runs, as necessary for the decoding device, while the block Binary Arrangements 802 Combines variable-length codewords into interleaved constant-length words and outputs them in the proper order required by the decoding device.

 For reordering purposes, for any decoding device, a “search” decoding device can be used in which the decoding device is included in the encoding device and provides data requests in the order in which codewords are needed for the actual decoding device. To support the "search" decoding device, independent reordering of run accounts for each stream can be performed. For decoding devices that can be easily modeled, in order to allow reordering, you can use queues with multiple time stamps or a single combined order. In one embodiment of the invention, the reordering of each codeword may be performed using a queue-like data structure and regardless of the use of multiple encoded data streams. The following is a description of a method for performing reordering.

 The first reordering operation performed by the encoder is to reorder each of the run accounts so that the run count is set at the start of the run (as required by the decoding device for decoding). This reordering is required because the encoder until the end of the run does not determine which run count (and code word) is available. Thus, the resulting run count output from the data encoding is reordered so that the decoding apparatus is able to properly decode the run counts back to the data stream.

 As shown in FIG. 11, the reordering unit 606 of the present invention includes a run count reordering unit 801 and a binary bit arrangement unit 802. A run reordering unit 801 is connected to receive a plurality of input signals that include a start signal 711, an end signal 712, an index signal 713 and codeword 714. These signals will be described in more detail in connection with the run-count reordering unit shown in FIG. In response to the input signals, the run count reordering unit 801 generates a codeword 803 and a signal 804. A signal 804 indicates when the run count needs to be reset. The codeword 803 is received by the binary unit 802. In response to the code word 803, the binary unit 802 produces interleaved words 805.

 Run count reordering unit 801 and binary bit arrangement unit 802 are described in more detail below.

 Block reordering run accounts.

 As described above, the decoding device is required to receive codewords at the time of the start of the data encoded by the codeword. However, the encoder does not know the identity of the codeword until the end of the data encoded with the codeword.

 A block diagram of one embodiment of a reordering block of run count 801 is shown in FIG. 12. The described embodiment provides four interleaved streams in which each interleaved word contains 16 bits, and the length of the code word varies from one to thirteen binary bits. In this case, the reordering unit 300 may be pipelined to handle all threads. Moreover, an encoder is used that associates run accounts with probability classes so that the maximum number of run accounts that can be activated at any time is small and is assumed to be 25 for this embodiment. Note that the present invention is not limited to four interleaved streams, interleaved words from 16 binary digits or codeword lengths from 1 to 13 binary digits, and it can be used for more or fewer streams with variable aemymi words longer than or less than 16 bits of codewords and lengths in the range from 1 digit up to more than 13 bits.

 As shown in FIG. 12, a pointer storage device 901 is connected to receive an input signal of index 713 and generates an address output signal that is supplied to one input of the multiplexer 902. Two other inputs of the multiplexer 902 are connected to receive the address in the form of a head pointer from the head counter 903 and the address in the form of a tail pointer from the tail counter 904. The output of multiplexer 902 is the address supplied to the codeword memory 908 and used to access it.

 The input signal of the index 713 is also supplied as an input signal to the multiplexer 905. The input signal of the codewords 714 is received at the other input of the multiplexer 905. The output of the multiplexer 905 is connected to the input of the validation module 906 and to the data bus 907. Data bus 907 is connected to the code memory words 908 and the input of the multiplexer 905. In addition, the output of the control module 909 is connected to the data bus 907. The input start signal 711 and the input end signal 712 are fed to separate inputs of the control module 909. chasing reliability detection unit 906 comprise the output codewords 803 and signal 804 (FIG. 7). The reordering unit of the run count 801 also includes a logic circuit of a control device (not shown to avoid complicating the description of the present invention), designed to coordinate the operation of the various elements of the reordering unit of the run counting 801.

 To repeat the processing cycle, the input of index 713 identifies the run. In one embodiment, the index indicates one of 25 probability classes. In this case, five binary digits are required to represent the index. Note that if multiple databanks are used for probability classes, then additional binary bits may be required to determine a particular databank. In one embodiment, an index input identifies a probability class for run counting. The input of the codewords 714 is a codeword when the end of the run occurs, and otherwise "does not matter." The trigger input 711 and the termination input 712 are control signals that indicate whether the run is starting, whether the run is ending, or both. A run starts and ends at the same time that the run consists of a single, non-encoded binary bit.

 The reordering unit of the run count 801 reorders the run counts generated by the binary generator in response to its input signals. A codeword memory 908 stores codewords during reordering. In one embodiment, the codeword memory 908 is greater than the number of run accounts that can be activated at the same time. This leads to better compaction. If the codeword memory is less than the number of run accounts that can be activated at the same time, then this can indeed limit the number of activated run accounts to the amount that can be stored in memory. In a system that provides good compaction, it often turns out that when data is accumulated for one codeword with a long run count, then many codewords with short run counts begin (and also end). This requires a large memory to prevent crowding out the long run until it is completed.

 The pointer memory 901 stores the code word memory location addresses for the probability classes that are in the middle of the run, and addresses the codeword memory 908 in a random access mode. The pointer memory 901 has a memory cell for an address in the memory of the codeword 908 for each probability class, which may be in the middle of the run. After the run is completed for a particular probability class, the address stored in the memory of the pointer 901 for this probability class is used to select codewords 908 from the memory, and the completed codeword is written to the codeword memory 908 in this cell. Until this time, this cell in the codeword memory 908 contains an invalid element. Thus, the pointer memory 901 stores the location of the erroneous codeword for each run account.

 The head counter 903 and the tail counter 904 also provide addresses for access to the codeword memory 908. Using the head counter 903 and the tail counter 904 allows the codeword memory 908 to be addressed as a queue or ring buffer (e.g., inverse store type memory). The tail counter 904 contains the address of the next available cell in the codeword memory 908 for allowing codeword input into the codeword memory 908. The head counter 903 contains the address in the codeword memory 908 of the next codeword to be output. In other words, the head counter 903 contains the address of the codeword memory of the next codeword to be canceled from the codeword memory 908. The location of each possible index (e.g., probability class) in the memory of pointer 901 is used to store where the tail pointer 904 was located. when the run has been started so that the appropriate codeword can be placed at this location in the codeword memory 908 at the end of the run.

 The control module 909 generates a validity signal as part of the data stored in the codeword memory 908 in order to show whether the contents of the data of the codewords are correctly stored or not. For example, if the binary bit of confidence has a logic level of "1", then the cell of the codeword memory device contains valid data. However, if the binary digit of confidence represents a logical “0”, then the cell of the codeword memory contains invalid data. The validation detection module determines whether the cell in the memory contains the correct codeword each time the codeword is read from the codeword memory 908. In one embodiment, the validity detection module 906 determines whether the correct codeword or specific Incorrect code.

 When a new run is started, the contents of the invalid data are entered into the codeword memory 908. The invalid data entry acts as gap holders in the data stream stored in the codeword memory 908, so that when the run is completed, the code word for the run can be stored in the memory in proper cell (for proper ordering when modeling a decoding device). In one embodiment of the invention, the input of incorrect data includes an index by a multiplexer 905 and an indication of an invalid (for example, a binary digit of an invalid) from the control module 909. The address in the memory of the code words 908, under which the invalid content is stored, is set by the tail pointer 904, and subsequently stored in the memory of the pointer 901 as a reminder of the cell for counting runs in the memory of the code words 908. The remaining data that appears between head pointer 903 and the tail pointer 904 stored in the memory 908 codewords in the form of completed runs accounts (e.g., accounts reordered runs). The maximum number of invalid memory cells is 0 to l-1, where l is the number of run counts. When the codeword is completed at the end of the run, the run count is populated in the codeword memory 908 using the address stored in the pointer memory 901.

 When the run is started, the run index is stored in the codeword memory 908, so that if the codeword memory 908 is full and the run is not yet completed, the index is used with the signal 804 to reset the corresponding run counter. In addition to storing codewords or indices in the codeword memory 908, one binary bit is used to indicate which of these two types of data is stored.

 If there is no start or end of the run, the reordering block of the run count is idle. If a run is started and there is no end to the run, and if the storage device is full, then the codeword is output from the codeword memory 908. The output codeword is a codeword stored in the address contained in the head pointer 903 for this probability class. Then, if the run is started and there is no end of the run (regardless of whether the memory is full), the input signal of the index 713 is written to the codeword memory 908 through the multiplexer 905 at the address defined by the tail pointer 904. Then, the tail pointer 904 is written to the memory pointer 901 at the address determined by the data in the input signal of index 713 (for example, in the memory cell of the pointer 901 for the probability class). After writing the tail pointer 904, the tail pointer 904 is incremented.

 If there is an end to the run and there is no start to the run, then the address stored in the memory of the pointer 901 corresponding to the index (probability class) is read and used as a cell in the memory of the code words for storing the completed code word in the input signal of the code word 714.

 If there is a run start and end of the run (that is, the run starts and ends at the same time), and the memory is full, then the code word is output from the codeword memory 908. Then, if the run is started and the run ends (regardless of whether the memory is full), the input of the codeword 714 is written to the codeword memory 908 at the address defined by the tail pointer 904. Then, the tail pointer 904 is incremented to contain the next available cells (e.g. increment by 1).

 In the present invention, the reordering unit of the run count 801 may provide codewords at various points in time. In one embodiment of the invention, codewords may be provided when they are true or false. Code words can be issued when they are incorrect, if there is a state of full memory, and the run is not completed. In addition, incorrect codewords may be issued to maintain a minimum speed (i.e., to control the speed). Invalid codewords may also be issued to turn off codewords 908 from the memory when the data is reordered by the run count or when, as a result of the reset operation, the reordering block of the run count goes to the middle of the codeword memory 908. Note that in such In this case, the decoding device should be notified that the encoding device is operating in this way.

 As described above, the code word is issued whenever the codeword memory 908 is full. After the memory is full, whenever a codeword 908 is entered (i.e., start a new codeword) into the memory, the codewords 908 are output from the memory Note that adjusting the content does not cause code words 908 to be output from the storage device when a memory full state exists. That is, the completion of the run with the subsequent recording of the resulting code word in a previously assigned memory cell does not cause output from the filled memory. Similarly, when the run is over, and the corresponding address in the pointer memory 901 and the address in the head counter 903 are the same, the code word can be issued immediately, and after that the head counter 903 can receive a positive increment without accessing the code word memory 908. In one embodiment, a memory full state occurs when the tail pointer 904 is equal to the head pointer 903 after the tail counter is incremented. Therefore, after the tail pointer has a positive increment, the logic of the control device in the reordering unit of the run count 801 compares the tail pointer 904 and the head pointer 903, and if they are the same, the logic of the control device determines that the codeword memory 908 is full and that a code word should be issued. In another embodiment, codewords may be output before the memory is full. For example, if the portion of the queue addressed by the header contains valid code words, it may be returned. This requires that the beginning of the queue be checked repeatedly to determine the status of the code words in it. Note that the codeword memory 908 at the end of the file encoding is cleared.

 Using the reordering block of the run count 801, the code word is issued when the value (for example, data) is first read from the codeword memory 908 at the address defined by the head pointer 903. The logic of the control device controls and coordinates the output of the codewords. A validity detection module 906 checks to determine if the value is a codeword. In other words, the validity detection module 906 determines whether the codeword is correct. In one embodiment of the invention, the validity detection module 906 determines the validity of any content by checking the bit of validity stored with each input message. If the value is a codeword (that is, the correct codeword), then the value is issued as a codeword. On the other hand, if the value is not a codeword (that is, the codeword is incorrect), then any codeword that has a run with the BVS symbol at least as long as the current run count can be returned. Codeword "0" is one codeword that so far correctly represents the current run and can be returned. After issuing the output, the head pointer 903 receives a positive increment for the next cell in the codeword memory 908. Alternatively, using “1N” with the shortest possible run lengths allows the decoding device to check whether only the codeword is crowded out before the MBC is released.

 In one embodiment of the invention, the reordering block of the run count 801 operates with a time period of two synchronization cycles. In the first synchronization cycle, input signals are received in the reordering block of the run count 801. In the second synchronization cycle, the signal is output from the codeword memory 908.

 Although codewords may be output whenever the head pointer 903 addresses the correct codeword, in some implementations it may be desirable to output the codeword only when the buffer is full. This causes a fixed delay in the system in units of the number of code words instead of a variable delay. If the storage device 908 is capable of holding a predetermined number of code words between the time when the run is started and entered and when it is output, the delay is this number of code words, since the output is not made until it is full. Thus, there is a constant delay in codewords. Note that the reordering delay still remains variable in other places, for example, in the amount of encoded or original data. By allowing the storage device 908 to fill up before output, a codeword is generated at the output in one cycle.

 Note that if the cell of the codeword memory device is marked as incorrect, then you can use unused binary digits to remember the identification of what the run count is for (that is, it stores the context element of the encoded signal or the probability class that should fill this cell). This information is useful for manipulation when the memory is full. In particular, the information can be used to indicate a binary generator that has not completed the codeword for this particular run length, which should now be completed. In this case, a decision is made to output the first codeword, which may appear due to the state of full memory. Thus, when the system resets the run counter, the information expressed through binary generators and run counts indicates when the system will start all over again.

 As for the index input, for pipelined reasons, when banks of probability classes are used, the index may include a bank identifier. That is, here for a particular probability class there can be many run accounts. For example, in the case of an 80 percent code, two run accounts can be used when one is used first, then the other.

 Since the codewords have a variable length, they must be stored in the memory of the codewords 908 in a way that allows you to set their length. Although it would be possible to remember the size explicitly, this would not minimize the use of the storage device. In the case of R-codes, storing the value of zero in the memory can indicate a one-bit code word "0", and code words "1N" can be stored so that a priority encoder can be used to determine the length from the first binary bit "1".

 If the codeword memory 908 is multi-port (for example, dual-port), this design can be pipelined to operate with one codeword per synchronization cycle. Since a large number of ports can access any cell in the codeword memory 908, codewords can be recorded in a memory cell, for example, when incorrect information or a codeword is stored, while another section can be read, for example, when the codeword the word is displayed. Note that in this case, the multiplexers can be modified to provide multiple data buses and addresses.

 Whenever the encoder outputs the code word "0" and sets the run counter to its initial state, since the codeword memory is full, the decoder should do the same. This requires the decoding device to simulate the storage queue of the codewords of the encoding device. Below will be described how this is done.

 Note that to save energy when implementing complementary MOS structures, the counters can be blocked for code words "1N" when code words "0" are output for incorrect runs. This is because the decoded codeword "1N" is correct, while only the codeword "0" can be incorrect.

 An alternative embodiment of the invention based on context.

In FIG. 13 is a block diagram of another embodiment of a reordering block of run counts that reorders data received in accordance with a context (as opposed to a probability class). The reordering unit of the run count 1000 performs reordering using R codes. Referring to FIG. 13, note that the reordering unit 1000 includes a pointer storage device 1001, a head counter 1002, a tail counter 1003, a data multiplexer 1004, an address multiplexer 1005, a length calculating unit 1006, a validity detecting unit 1007, and a codeword memory 1008 A codeword memory 1008 stores codewords during reordering. The memory of the pointer 1001 stores the addresses of the cells of the codeword memory for the context elements of the encoded signal that are located in the middle of the run. The head counter 1002 and the tail counter 1003 allow addressing the memory of the codewords 1008 as a queue or a ring buffer in addition to the random access address of the pointer 1001. In the case of R-codes, storing the value of zero in the memory can indicate a one-bit codeword "0" and the code words “1N” can be stored so that a priority encoder can be used to determine the length from the first binary bit “1”. The length calculator 1006 functions like a priority encoder. (If other non-uniform codes were used, it would be more efficient to add the binary digit “1” to the memory to mark the length of the code to mark the start of the code word than to add log ₂ binary digits.) The reordering block of the run count 1000 also includes the logic of the control device in reverse steps to coordinate and control the operation of components 1001-1008.

 The functioning of the reordering block of the run count 1000 is very similar to the functioning of the reordering block of the run count based on probability estimates. If a new run begins, then the incorrect content, including the context element of the encoded signal, is written to the codeword memory 1008 at the address indicated by the tail pointer 1003. After that, the address of the tail pointer 1003 is stored in the pointer memory 1001 at the address of the encoded signal context element current account runs. Then, the tail pointer 1003 receives a positive increment. Upon completion, the pointer in the memory of the pointer 1001 corresponding to the run count is read from the memory of the pointer 1001, and the code word is written in parallel to the memory of the code words 1008 in the cell indicated by this pointer. If neither the start nor the end of the run occurs, and if the cell indicated by the address of the head pointer 1002 in the codeword memory 1008 does not contain invalid data, then the code word addressed by the head pointer is read and displayed. Then, the head pointer 1002 is incremented. In the event that the run starts and ends at the same time, the code word is written to the codeword memory 1008 at the address indicated by the tail pointer 1003, and then the tail pointer 1003 is incremented.

 Similarly, when the run ends and the corresponding address in the pointer memory 1001 and the address in the head counter 1002 are the same, the code word can be output immediately, and the value in the head counter 1002 can be incremented without accessing the code word memory 1008.

 For context-assisted run counting systems, each context requires a memory location in the pointer memory 1001, so that the capacity of the status memory of the bit sequence generator (GPB) and the probability estimation module (MOB) can be increased to provide this memory. The storage capacity of the pointer 1001 is equal to the capacity required for the address of the storage of codewords.

 The number of cells in the codeword memory 1008 may be selected by the developer in a particular implementation. The limited capacity of this memory reduces compaction efficiency, so there is a trade-off between cost and compaction. The capacity of the codeword memory is determined by the size of the largest codeword plus one binary bit to indicate validity.

 To illustrate the reordering, an example of using the R2 (2) code shown in Table 1 will be presented. 14. Table 15 shows the data to be reordered / 0 = BVS (the most probable symbol); 1 = MVS (least probable symbol) /, marked by context. There are only two contexts. Run start and end are indicated, and code words are shown at the end of runs.

 The reordering operation of variable data is shown in Table. 16. A codeword memory device with four cells 0-3 is used that are large enough to avoid overflow in this example. Each line shows the state of the system after the operation, which is either the start or the end of the run for some context or codeword output. The symbol "x" is used to indicate memory cells that are "indifferent." For some non-encoded binary bits, the run does not start or stop, so the reordering block of the run count is idle. For coded bits that have completed runs, one or more codewords may be output, which may cause several changes in the state of the system.

 In accordance with table. 16, the head and tail pointers are set to zero, indicating that nothing is contained in the codeword memory (e.g., a queue). It is shown that the pointer memory has two memory cells, one for each context. Each cell has “indifferent” values until the arrival of discharge number one. Shows a codeword storage device with a depth equal to four codewords, which all initially have "indifferent" meanings.

 In response to the received data for the binary digit number 1, the head pointer stores an indication of cell 0 of the codeword memory device. Since the decoding device will wait for data, the next available cell 0 of the codeword memory is assigned to the codeword, and the incorrect value is written to memory 0. Since the context is zero, the address of the codeword memory cell assigned to the codeword is stored in the pointer memory cell for zero context (cell 0 of the pointer storage device). Thus, in cell 0 of the pointer memory, “0” is stored. The tail pointer increments to the next cell 1 of the codeword memory.

 In response to the data corresponding to bit number 2, the head counter stores an indication of the first memory cell (since there was no output causing the increment). Since the data corresponds to the second context, that is, context 1, the next cell of the codeword memory is assigned to the codeword as cell 1 of the codeword memory indicated by the tail pointer, and incorrect data is written to the cell. The address, that is, codeword cell 1, is recorded in the pointer memory cell corresponding to context 1. That is, the address of the second codeword memory cell is recorded in cell 1 of the pointer memory. After that, the tail pointer is incremented.

 In response to the data corresponding to bits 3, the reordering block is idle because the run does not start and does not end.

 In response to the corresponding binary digit number 4 data for context 1 indicates the end of the run. Therefore, the codeword “101” (cell 1 of the codeword memory device) is written to the codeword memory cell assigned to context 1, as indicated by the pointer memory cell for context 1. The head and tail pointers remain the same, and the value in the pointer memory cell for context 1 will not be used again, therefore it is "indifferent".

 In response to the data corresponding to the binary digit number 5, the reordering block is not busy, because there is no start or end of the run.

 In response to the data corresponding to the binary digit number 6, the same type of operation occurs as described above for the binary digit number 2.

 In response to the data corresponding to bit number 7, the codeword run for context 0 ends. In this case, the codeword "0" is written to the codeword memory cell (cell 0 of the codeword memory), as indicated by the pointer memory cell for context 0 (cell 0 of the pointer storage device). After that, the value in the cell of the pointer memory will not be used again, so that it turns out to be "indifferent". In addition, a codeword memory cell designated by a head pointer contains valid data. Therefore, the correct data is output, and the head pointer is incremented. The increment of the head pointer causes them to point to another cell in the memory of the code words containing the correct code word. Therefore, this codeword is output, and the leading pointer is incremented again. Note that in this example, codewords are output when they are ready, as opposed to when the codeword memory is full.

 Processing of non-encoded bits is continued as described above. Note that codeword memory cells are not assigned to use specific contexts, so codewords from any context can be stored in a given codeword memory cell throughout the encoding of the data file.

 Binary Layout Block.

 The binary arrangement is illustrated in FIG. 7, which shows data processed by a reordering block before and after the arrangement of the bits. In FIG. 7 shows sixteen variable-length codewords numbered 1 through 16 to indicate how they are used by the decoding device. Each codeword is assigned to one of three coded streams. The data in each encoded stream is broken up into words of a fixed length, called interleaved words. (Note that one variable-length codeword can be split into two interleaved words.) In this example, interleaved words are ordered in a single interleaved stream, so that the order of the first variable-length codeword (or partial codeword) in a particular interleaved (interleaved) word ) determines the word order with alternation. Other types of ordering criteria may be fulfilled. The advantage of interleaving a plurality of encoded streams is that one channel of encoded data can be used to transmit data and that variable length shifting can be performed for each stream in a parallel or pipelined manner.

 The binary unit 802 according to the present invention receives variable-length codewords from the reordering unit of the run count 801 and composes them into interleaved words. The binary arrangement unit 802 comprises a logic circuit for manipulating variable-length codewords and a reordering unit of a combined order type for outputting interleaved words of a fixed length in the correct order. In one embodiment, codewords are received from the reordering block of the run count at a rate of up to one codeword per clock cycle. A block diagram of one embodiment of a binary bit arrangement unit 802 is shown in FIG. 14. In a further embodiment of the invention, four interleaved streams are used, each interleaved word consists of 16 bits, and the length of the code word varies from one to thirty binary bits. In one embodiment, a single binary arrangement block is pipelined to manipulate all streams. If a dual-port memory device (or register file) is used in the binary bitmap unit 802 according to the present invention, it can output one interleaved word per clock cycle. This may be faster than required for coordination with the rest of the encoder.

 As shown in FIG. 14, the binary unit 802 includes a component logic 1101, a stream counter 1102, a memory 1103, tail indicators 1104, and a head counter 1105.

 A component logic circuit 1101 is connected to receive codewords and connected to a stream counter 1102. A stream counter 1102 is also connected to a storage device 1103. To the storage device 1103, tail indicators 1104 and a head counter 1105 are also connected.

 A stream counter 1102 monitors the interleaved stream to which the current input codeword is associated. In one embodiment of the invention, thread counter 1102 re-counts threads 0 through N-1, where N is the number of threads. After the stream counter 1102 reaches a value of N-1, it starts counting again from 0. In one embodiment, the stream counter 1102 is a two-bit counter and counts from 0 to 3 (for four interleaved streams). In this embodiment, the thread counter is set to zero (for example, by means of a general reset).

 The component logic 1101 combines the current input codeword with the previous input codewords to form interleaved codewords. The length of each of the code words may vary. Therefore, the component logic 1101 composes these variable-length codewords into fixed-length words. The interleaved codewords generated by the component logic 1101 are output to the memory 1103 in order and stored in the memory 1103 until the appropriate time for output. In one embodiment, storage device 1103 is a random access statistical storage device (RAM) or a register file with sixty-four 16-bit words.

 The interleaved words are stored in the storage device 1103. In the present invention, the capacity of the storage device 1103 is large enough to manipulate words in two cases. One case of normal operation, when one interleaved stream has code words of minimum length, and other interleaved flows have code words of maximum length. This first case requires 3 • 13 = 39 memory cells. Another case is the initialization case, where again one stream has code words of minimum length, or short code words, and other threads have code words of maximum length, or long code words. For the second case, although 2 • 3 • 13 = 78 memory cells are sufficient, the operation of the MOB module makes it possible to more closely link 56 cells.

 Reordering is performed by the storage device 1003 in conjunction with the stream counter 1102 and the tail pointers 1104. The stream counter 1102 indicates the current codeword stream received by the memory 1103. Each of the interleaved streams is associated with at least one tail pointer. The tail pointers 1104 and the head counter 1105 reorder the codewords. The reason why you need to have two tail pointers to the stream follows from the interleaving word N, requested by the decoding device, when the data in the interleaved word N-1 contain the start of the next codeword. One tail pointer defines a cell in memory 1103 for storing the next interleaved word from a given interleaved stream. Another tail pointer identifies a cell in a memory for storing an alternating word after the next such word. This allows you to determine the cell of the word N with alternation, when the time of requesting the decoder for the word N-1 with alternation is known. In one embodiment, the pointers are eight 6-bit registers (two tail pointers to a stream).

 In one embodiment, at the beginning of the coding, the tail pointers 1104 are set so that the first eight interleaved words (two from each stream) are stored in memory 1103 in a sequence of one from each stream. After initialization, whenever the composing logic device 1101 starts a new word with alternation for a particular codestream, the “next” tail pointer is set to “after the next” tail pointer, and the tail pointer “after the next” for the code stream is set to the next available cell memory. Thus, for each stream, there are two tail pointers. In another embodiment, only one tail pointer is used for each stream, and it indicates where the next interleaved word should be stored in memory 1103.

 The head counter 1105 is used to determine a memory location for outputting the next word interleaved from the binary unit 802. In the described embodiment, the head counter 1105 contains a 6-bit counter that increments to output the entire word interleaved at once.

 Storage device 1103, in addition to using it for reordering, can also be used as a reverse store type (FIFO) buffer between the encoder and the channel. It may be desirable to have a memory device with a larger capacity than that required for reordering, so an almost full FIFO signal can be used to stop the encoder if the channel cannot support the encoder. An encoder of the type of one binary digit per cycle cannot generate one interleaved word per cycle. When the encoder is well aligned with the channel, the channel does not receive an interleaved word for each cycle, and therefore some FIFO buffering is required. For example, a channel that can receive a 16-bit word interleaved every 32 clock cycles can be a well-matched option for effectively expanding a bandwidth of 2: 1 or more.

 A block diagram of a component logic circuit is shown in FIG. 15. The component logic circuit 1101 consists of a size block 1201, a set of accumulative adders 1202, a shifter 1203, a multiplexer 1204, a set of registers 1205 and an OR gate 1206. The size block 1201 is connected to receive code words and connected to the accumulative adders 1202. The accumulative adders connected to the shifting device 1203, which also receives code words. The biasing device 1203 is connected to the multiplexer 1204 and the OR gate 1206. The multiplexer 1204 is also connected to the registers 1205 and the output of the OR gate 1206. The registers are also connected to the OR gate 1206.

 In one embodiment of the invention, the codewords are inputted into a 13-bit bus with zero bits unused. These zero bit positions set to zero are located next to “1” in the code words “1N”, so the priority encoder in the size block 1201 can be used to determine the length of the code words “1N” and generate the size of the code words “0”.

 The accumulating adders 1202 comprise a plurality of accumulating adders, one for each interleaved stream. The accumulating adder for each interleaved stream saves a record of the number of binary bits already in the current interleaved word. In one embodiment, each accumulative adder comprises a 4-bit adder (with completion) and a 4-bit register used for each stream. In one embodiment of the invention, the output of the adder is the output of the accumulating adder. In another embodiment, the output of the register represents the output of the accumulating adder. Using the size of the codewords received from the size block 1201, the accumulating adders determine the number of bits to shift in order to concatenate the current codeword into a register containing the current interleaved word for this stream.

 Based on the current value of the accumulating adder, the shifting device 1203 aligns the current codeword so that it properly follows any previous codewords in the alternating word. Thus, the data in the encoder is shifted in decoding order. The output of the shifter 1203 is 28 bits, which corresponds to the case where a 13-bit codeword is to be added to 15 bits in the current word interleaved so that the bits from the current code word end in the highest 12 bits of the 28 output binary discharges. Note that the biasing device 1203 operates without feedback and therefore can be conveyed. In one embodiment, the shifting device 1203 is a multi-register cyclic shifting device.

 Registers 1205 store binary bits in the current interleaved words. In one embodiment, a 16-bit register for each interleaved stream holds the previous binary bits of the current interleaved word.

 Initially, the stream codeword is received by the shifting device 1203, while the size block 1201 indicates the size of the codeword to the accumulating adder corresponding to the stream. The accumulating adder has an initial value of zero, set by means of a general reset. Since the value of the accumulating adder is zero, the code word is not shifted and then passes in the OR mode using the OR logic 1206 with the contents of the register corresponding to the stream. However, in some embodiments, the code words “1N” must be shifted for proper alignment even at the beginning of an interleaved word. Such a register is set to zero and, therefore, the result of the OR operation consists in placing the code word in the positions of the rightmost bits of the output signal of the OR logic circuit 1206 and the direction along the feedback circuit through the multiplexer 1204 into the register for storage until the next code word from the stream. Thus, initially, the shifting device 1203 acts as a transit passage. Note that the number of bits in the first codeword is now stored in the accumulating adder. Upon receipt of the next codeword for this stream, the value in the accumulating adder is sent to the shifter 1203, and the codeword is shifted to the left to combine with the previously entered binary digits in the interleaved word. Zeros are placed in other positions of the binary digits in the shifted word. The binary bits from the register corresponding to the stream are combined with the binary bits from the shifter 1203 using the logic OR OR 1206. If the accumulating adder does not give an indication of completion (for example, a signal), then more binary bits are required to complete the formation of the current word with alternation and the data resulting from the OR operation is entered back into the register through the multiplexer 1204. In one embodiment, the multiplexer 1204 is a 2: 1 multiplexer. When the accumulating adder generates a completion signal, 16 bits that have passed the OR operation from the data from the OR logic 1206 represent the alternating full word and then are output. Multiplexer 1204 causes the register to load with any additional binary bits (for example, the upper 12 binary bits of 28 binary bits leaving the shifter 1203) after the first 16, and the rest are filled with zeros.

 Controlling the multiplexer 1204 and interleaving the word includes outputting a completion signal from the accumulating adder. In one embodiment, multiplexer 1204 comprises sixteen 2: 1 multiplexers, four of which have one input that is always zero.

 The present invention provides numerous embodiments of reordering data. For example, in a system with multiple code streams, code streams should be reordered into interleaved words, as shown in FIG. 7. The present invention provides numerous ways of performing reordering into interleaved words.

 One way to reorder data into interleaved words is to use a search decoder, as shown in FIG. 32. A plurality of run accounts reordering units 2501A-n are connected to receive codeword information along with a codeword stream. Each of them produces code words and size signals at the output. A separate block of binary arrangement logic circuits (1101) of the type of binary arrangement blocks 2502A-n is connected to receive output signals of codewords and sizes from one of the blocks of reordering of run accounts 2501A-n. The blocks of the logic circuits of the arrangement of the binary digits 2502A-n output alternating words that are transmitted to both the multiplexer 2503 and the search decoding device 2504. The decoding device 2504 provides a selective control signal that is received by the multiplexer 2503 and indicates the multiplexer 2503, which from interleaved words to output to the code stream.

 Each encoded data stream has a run count reordering unit comprising a run count reordering unit 801 shown in FIG. 11. Each binary arrangement unit combines a variable-length codeword into alternating words having a fixed length, possibly 8, 16, or 32 binary digits in a word. Each binary arrangement block contains registers and a shifting circuit as described above. The decoding device 2504 contains a complete operational decoding device (including GPB, MOB, and KM) that has access to interleaved words from all binary arrangement blocks (either on separate buses, as shown in Fig. 32, or via a common bus). Whenever the decoding device 2504 selects an interleaved word from one of the binary arrangement blocks, this word is transmitted in the code stream. Since the decoding device at the end of reception requires data in the same order as that of an identical search decoding device, the interleaved words are transmitted in the proper order.

 An encoder together with a search decoder may be suitable for use in a half-duplex system, since a search decoder can also be used as a normal decoder. The advantage of using the search decoding device method is its applicability to any deterministic decoding devices. The alternative solutions described below, regardless of the search decoding device, use simpler models of the decoding device to reduce the cost of hardware. For decoding devices that decode multiple codewords in the same clock cycle, modeling a decoding device using less hardware than the decoding device may not be possible, which inevitably entails the use of a search decoding device. As will be described below, there are simpler models of decoding devices that decode at most only one codeword per cycle.

 Another technique for reordering data for pipelined decoding device systems is that decoding at most one codeword per clock cycle is based on the fact that the information needed to model the decoding device's requests for encoded data is to know the order of the code words (considering all codewords, not independent codewords for coded data streams). If a timestamp is associated with each codeword when it enters the run count reordering unit, regardless of which interlaced word has the highest timestamp associated with it, it represents the next interleaved word to be output.

 In FIG. 33 is a block diagram illustrating an example reordering unit of an encoder. The coding system shown here is the same as described with reference to FIG. 32, except that each run count reordering unit 2501A-n also receives time stamp information. This timestamp information is also advancing into the bitmap blocks 2502A-n. The bitmap units 2502A-n provide interleaved words for multiplexer 2503, and the associated timestamps for logic 2601. Logic 2601 provides a control signal for multiplexer 2503 to select an interleaved word to be output to the codestream.

 In this embodiment, the search decoder is replaced with a simple comparison that determines which of the bitmap units 2502A-n has a codeword (or part of a codeword) with the highest time stamp. Such a system acts for the multiplexer 2503 as a set of queues with time stamps. The 2601 logic circuit simply makes a choice between different queues. The logic of each of the run count reordering blocks 2501A-n only slightly changes (from the run count reordering block 801) to record the timestamp when the run starts. Each run count reordering unit 2501A-n is equipped for storing a time stamp in a codeword memory. Storing timestamps with a sufficient number of binary bits to count each word from the code words in the encoded data stream is sufficient, but in some embodiments, fewer binary bits may be used.

 The following is a brief description of the steps for using multiple timestamped queues. The description is clear to those skilled in the art. Here are the operations of the encoder. For the case when the run begins and ends using the same code word, simplification is not performed. Operations can be checked for each coded character (although in practice not all checks need to be performed). Suppose interleaved words are 32 bits wide.

if (if there is no current codeword for context):
placing a timestamp in a queue (used to determine the next queue),
queuing a context pointer
queuing incorrect data
indication of the context for entering the queue,
incrementing the tail account of the queue,
if (if there is already a codeword and BVS):
incrementing the count of context runs,
if (MAXRUN or MVS):
placing the correct data in the queue
(no context pointer needed)
setting the pointer to zero and counting runs in the context memory,
adjusting the probability estimates in the context memory,
if (reliable data at the beginning of the next queue) (if):
placement of 32 bits of data on the output,
flushing the contents of the queue,
ensuring the increment of the head of the queue,
while (while any queue is almost complete):
finding the next queue that should put the output data,
while less than 32 bits of valid data,
using a context pointer to find context,
setting the pointer to zero and running counts in the context memory,
placing the MAXRUN codeword in the queue data.

 The operations of the decoding device are similar, although there is no need to store the code words in the queue. However, you must save the time stamp of the code words in the queue.

 To store information about the order of code words, the time stamp function described above is used. An equivalent way of expressing the same concept is to use one queue for all codewords, that is, a combined queue. In a combined queue system, as shown in FIG. 34, one run reordering unit 2701 is used for all interleaved flows. Run reordering unit 2701 generates codeword, size, and stream output signals to binary arrangement blocks 2502A-n, output interleaved words for multiplexer 2503, and position information for logic circuit 2702, and these multiplexer signals 2503 are intended to be output as interleaved words as part of a code stream.

 In the case of arbitrary streams, the run reordering memory remembers the identification of the interleaved stream for each codeword. Each interleaved thread has its own head pointer. When the binary unit needs more data, the appropriate head pointer is used to select as many codewords as are necessary to form a new interleaved word. This may include looking at a large number of codeword memory cells to determine which ones are part of the proper stream. Alternatively, this may entail viewing a codeword storage device for additional fields to perform a linked list.

 Another method of interleaving threads in the present invention is to use a combined queue with a fixed distribution of threads. This method uses a single tail pointer, as in the case of a combined sequence, so that no timestamps are required. In addition, numerous head pointers are used as in the previous case, so that there is no overhead when outputting data from a particular stream. In the case of N streams, this assignment of codewords to interleaved streams is carried out according to the following rule: a codeword M is assigned to a stream M modulo N. Note that, in accordance with this method, interleaved streams can have codewords from any context element, encoded signal, or class probabilities. If the number of streams corresponds to an exponent of two, then M modulo N can be calculated by discarding some of the most significant binary bits. For example, suppose that a codeword reordering memory is addressed by 12 bits and that four interleaved streams are used. The tail pointer is 12 bits long, and the two least significant bits identify the encoded stream for the next codeword. Four leading pointers with 10 binary digits, each of which is implicitly assigned to each of the four possible combinations of the two least significant binary digits. Both the tail and head pointers are incremented like regular binary counters.

 In the decoding device, the shifting device has registers for storing alternating words. The biasing device presents properly aligned encoded data to the binary generator. When the binary generator uses some encoded data, it reports this to the shifter. The shifter presents properly aligned data from the next interleaved stream. If the number of encoded data streams is N, the shifter has N-1 clock cycles for shifting the data used and possibly requesting another interleaved codeword before this particular interleaved stream is used again.

 The present invention includes a decoding apparatus that supports real-time encoding of an encoder with limited reordering memory. In one embodiment, the decoding device is also characterized by reduced requirements in capacity and complexity by maintaining a run count for each probability class instead of each contextual collection.

 In FIG. 17 is a block diagram of one embodiment of a hardware system according to the present invention that implements a decoding device. The decoding device system 1400 includes a reverse store type (FIFO) structure 1401, decoding devices 1402, a storage device 1403, and a context model 1404. Decoding devices 1402 include a plurality of decoders. The encoded data 1410 is provided so that it is received by the reverse store type structure 1401. The reverse store type structure 1401 is connected to supply encoded data to the decoding device 1402. Decoding devices 1402 are connected to the storage device 1403 and the context model 1404. The context model 1404 is also connected to storage device 1403. One output of context model 1404 contains decoded data 1411.

 In system 1400, encoded data 1410 is input to a reverse store type structure 1401, ordered, and interleaved. The reverse store type structure 1401 contains data in the proper order. Streams are provided to decoding devices 1402. Decoding devices 1402 request data from these streams in a sequential and deterministic order. Although the order in which decoding devices 1402 require encoded data is non-trivial, it is not arbitrary. By arranging the code words in this order in the encoder, instead of the decoder, the encoded data can be interleaved into a single stream. In another embodiment, encoded data 1410 may comprise a single non-interleaving data stream, where data for each context element of the encoded signal, context class, and probability class are added to the data stream. In this case, the inverse store type structure 1401 is replaced with a memory area for receiving all encoded data before forwarding the data further to decoding devices 1402 so that the data can be segmented appropriately.

 When the encoded data 1410 is received by the inverse store type structure 1401, the context model 1404 determines the current context collection. In one embodiment, the context model 1404 determines the current context collection based on previous pixels and / or bits. Although not shown, linear context buffering can be enabled with the context model 1404. Linear buffering provides the necessary data, or template, with which the context model 1404 determines the current context collection. For example, where the context is based on the values of image elements in the vicinity of the current image element, linear buffering can be used to store the values of those image elements in the vicinity that are used to provide a special context.

 In response to the contextual collector, the decoding system 1400 selects a decoding state from the memory 1403 for the current contextual collector. In one embodiment of the invention, the state of the decoder includes the state of the probability estimation module (MOB) and the state of the binary generator. The status of the MOB determines which code should be used to decode the new codewords. The state of the binary generator supports recording of the binary bits in the current run. The state for the decoding devices 1402 is provided from the storage device 1403 in response to the address provided by the context model 1404. The address selects a cell in the storage device 1403 that stores information corresponding to the contextual collection.

 After selecting the state of the decoding device for the context collector from the storage device 1403, the system 1400 determines the next uncompressed binary bit and processes the state of the decoding device. Then, the decoding devices 1402 decode the new codeword, if necessary, and / or update the run count. If necessary, the state of the MOV, as well as the state of generation of binary digits, is updated. After that, the decoding devices 1402 write the new state of the encoding device to the storage device 1403.

 In FIG. 18 shows one embodiment of a decoding apparatus of the present invention. The decoding device includes a shifting logic 1431, a binary bit generator 1432, a “new value to” logic 1433, a MOV update logic 1434, a new codeword logic 1435, a MOB status block for cache logic 1436, a coding logic for template 1437, extension logic for MaxP1 coding, Pattern and partition R3 1438, decoding logic 1439, multiplexer 1440, and run count update logic 1441. The shift logic 1431 is connected to receive input dnyh coded data 1443, 1442 and the state of the input signal (from the memory). The output signal of the biasing logic circuit 1431 is supplied as an input signal to the logic circuit for generating binary bits 1432, the logic circuit for generating a “new value to” 1433, and the logic for updating the MOB 1434. The logic circuit for generating binary bits 1432 is also connected to receive an input signal state 1442 and generates an output signal of decoded data for the context model. The logic "new value to" 1433 produces an output signal that is input to an encoding logic circuit according to pattern 1437. The update logic circuit MOB 1434 also receives a status input signal 1442 and generates a status output signal (supplied to a storage device). The input state signal 1442, in addition, is fed to the inputs of the logic circuit of the new code words 1435 and the logic state circuit of the MOB for code 1436. The output signal of the logic state circuit of the MOB for code 1436 is received for reception by the expansion logic 1438. The output of the expansion logic 1438 is connected to decoding logic 1439 and run calculation update logic 1441. The other input of the decoding logic is connected to the output of the code circuit according to pattern 1437. The output of the decoding logic 1439 is connected to one the input of the multiplexer 1440. At the other input of the multiplexer 1440 the input state signal 1442 is received. The input of the selection of the multiplexer 1440 is connected to the output of the logic circuit of the new codewords 1435. The outputs of the multiplexer 1440 and the expansion logic 1438 are connected to two inputs of the logic for updating the run count 1441 together with the output the logic of the code for the pattern 1437. The output of the logic of the update of the run count 1441 is included in the status output signal supplied to the storage device.

 The biasing logic 1431 shifts data from the code data stream. Based on the input encoded data and the input mode signal, the binary bit generation logic 1432 generates decoded data for the context model. The new value k logic 1433 also uses a data offset and a state input signal to generate a new value of k. In this embodiment, the new value k logic 1433 uses the MOB state and the first bit of encoded data to generate a new value of k. on the basis of the new value k, the coding logic according to pattern 1437 generates a pattern R1Z for the next codeword. The R1Z pattern for the next codeword is sent to decoding logic 1439 and run count update logic 1441.

 The MOB update logic 1434 updates the status of the MOB. In one embodiment of the invention, the state of the MOB is updated using the current state. The corrected state is sent to the storage device. The logic of the new codewords 1435 determines whether a new codeword is needed. The MOV state logic for code 1436 determines the code for decoding using the input state 1442. The code is entered into the extension logic 1438 to generate the maximum run length of the current template and the splitting value R3. Decoding logic 1439 decodes a codeword to produce a run count output. The multiplexer 1440 selects either the output of the decoding logic 1439 or the input of mode 1442 for the run count update logic 1441. The run count update logic 1441 updates the run count.

 A decoding system 1400 according to the present invention, including a decoding device 1430, operates in a pipelined manner. In one embodiment of the invention, the decoding system 600 of the present invention determines context collections, estimates probabilities, decodes codewords, and generates binary bits from run accounts, all by pipelining. One embodiment of the piping structure of a decoding system is depicted in FIG. 20. The embodiment of the pipelined decoding process shown in the drawing comprises six steps 1-6.

 At the first stage, the current contextual collection (1501) is determined. In the second step, after the determination of the context element, a memory device (1502) is read, in which the current state of the decoding device for the context element is selected from the memory device. As stated above, the state of the decoding device includes the MOB mode and the state of the binary generator.

 In a third step of the pipelined decoding process of the present invention, a decompressed binary bit (1503) is generated. This makes it possible to ensure the suitability of the binary digit for the context model. Two other operations occur during the third stage. The state of the MOV is converted to a code type (1504), and the determination is made as to whether a new codeword (1505) should be decoded, which also occurs in the third stage.

 During the fourth stage, the decoding system processes the codeword and / or updates the run count (1506). When processing the code word and updating the run count, several sub-operations are performed. For example, the codeword is decoded to determine the next run count, or the run count is updated for the current codeword (1506). If necessary, then when decoding new codewords, additional encoded data is selected from the input signal of the inverse store type device. Another suboperation that occurs in the fourth stage is to update the state of the MOV (1507). Finally, in the fourth stage of the decoding pipeline, the new MOB state is used to determine which codeword of zero run length (described below) is suitable for the next code if the run count of the current codeword is zero (1508).

 During the fifth step of the decoding pipeline of the present invention, the state of the decoding device, together with the updated state of the MOB, is written to the storage device (1509), and the offset for the next codeword begins (1510). At the sixth step, the shift to the next codeword is completed (1510).

 The pipelined decoding of the present invention actually begins with a decision as to whether to start the decoding process. This determination is based on whether there is enough data to present them to a decoding apparatus according to the present invention. If there is not enough data from the reverse store type device, the decoding system stops. In another case, the decoding system may be stopped when the decoded data is input to a peripheral device that is not capable of receiving all the output data of the decoding device that it produces. For example, when the decoding device provides the output signal to the video display interface and the associated television circuitry, the video signal may be too slow, so the decoding device must be stopped to capture the video signal.

 After a decision is made to start the decoding process using the context model, the current context element is determined. In the present invention, the current context element is established by examining the prior data. Such previous data may be stored in lowercase buffer devices and may include data from the current line and / or previous lines. For example, in a context template for a given bit, binary bits from a lowercase buffer device (s) can be constructed using a template relative to the previous data, so that the context element for the current data is selected according to whether the verified previous data matches the template. These lowercase buffer devices may include binary shift registers. For each bit matrix of an n-bit image, a pattern can be used.

 In one embodiment of the invention, the context encoded signal element is selected by outputting the address to the memory during the next pipelining step. The address may include a predetermined number of binary bits, for example three bits, to identify the bit matrix. By using three binary bits, the position of the binary bits in the image element data can be identified. The template used to define the context can also be represented as part of the address. The binary digits and the binary digits that identify the pattern used to identify the bit matrix can be combined to create an address for a special cell in a storage device that contains mode information for an element of the encoded context signal defined by these binary digits. For example, using three binary digits to determine the position of the binary digits in the context image element and ten previous binary digits at the same position in each of the previous image elements in the template, you can create a 13-bit context address.

 Using the address created using the context model, a storage device (for example, a random access memory device, RAM) is requested to obtain status information. The state includes the state of the MOB. The MOV status includes a current probability estimate. Since the same code uses more than one state, the state of the MOB does not include a probability class or code designation, but rather a pointer to a table, such as the table shown in FIG. 8. In addition, when using the type table shown in FIG. 8, the state of the MOV also provides the most probable character (BVS) as a means to identify whether the current state of the MOV corresponds to the positive or negative side of the table. The status of the generation of binary digits may include a count value and an indication of whether there is a MVS (least probable symbol). In one embodiment of the invention, a BWS (most probable symbol) value is also included for the current run to decode the next codeword. In the present invention, in order to reduce the space required for run counters, the state of generating binary bits is stored in a storage device. If the cost of the space in the system required for the counters for each context is low, the state of the generation of the binary digits should not be stored in the storage device.

 After the fourth stage is completed, the new state of the binary generator and the state of the MOV are recorded in the storage device. In addition, in the fifth step, the encoded data stream is shifted to the next codeword. The shift operation is completed in the sixth step.

 In FIG. 19 is a block diagram of one embodiment of an inverse store type structure 1401 according to the present invention, illustrating interleaved word buffering for two decoding devices. Note that any number of decoding devices can be supported using the principles of the present invention. As shown, the input data and the inverse store type structure are long enough to accommodate two alternating words. The structure of the inverse store type 1401 contains the structure of the inverse store type 1460, registers 1461 and 1462, multiplexers 1463 and 1464, and a control unit 1465. Two input codewords are provided as alternating input words. The outputs of the reverse storefront structure 1460 are connected to the inputs of the registers 1461 and 1462. The inputs of the multiplexer 1463 are connected to the outputs of the registers 1461 and 1462. The control unit 1465 is connected to provide control signals for the reverse storefront type 1460, the registers 1461 and 1462, and the multiplexers 1463 and 1464. The interlaced words are output (output 1 and 2) provided for two decoding devices. Each decoding device uses a request signal to indicate the use of the current word and the need for the next new word. The request signals from the decoding devices are fed to the inputs of the control unit 1465. The control unit 1465 provides a request signal of the inverse store type structure in order to request additional data from the storage device.

 At the initial stage, the inverse store-type structure and registers 1461 and 1462 are filled with data, and the actual state of the trigger is set in the control unit 1465. Whenever a request appears, the control unit 1465 provides data in accordance with the logic shown in the table. 17.

 In FIG. 21 shows another structural representation of a decoding apparatus according to the present invention. Referring to FIG. 21, note that variable-length (encoded) data is input into the decoding device. The decoding device provides a signal that is fed back as feedback with a delay, which is received as the input signal of the decoding device. In the decoding apparatus of the present invention, the variable length offset used in decoding is based on the decoded data that is available after some delay. Feedback delay does not reduce the bandwidth in decoding devices with an acceptable delay.

 Variable-length input data is divided into interlaced words having a fixed length as described in connection with FIG. 7. The decoding apparatus uses fixed-length words, as described below with reference to FIG. 22. The decoding device and the delay model the conveyor decoding device, as described in connection with FIG. 20, 21 and 39, or a plurality of parallel decoding devices of the type described in connection with FIG. 2-5. Thus, the present invention provides a decoding device that is not critical to delay. Delayed decoding apparatuses of the present invention allow parallel manipulation of variable length data.

 Known decoding devices (e.g., Huffman decoding devices) are delay critical. To perform a variable length shift necessary to decode the next codeword, information is required determined from the decoding of all previous codewords. In contrast, the present invention provides decoding devices with an acceptable delay.

 Shift in the decoding system.

 A decoding apparatus according to the present invention provides a shifting logic circuit for shifting words interleaved into a corresponding binary bit generator for decoding. The shifting device of the present invention does not require any particular type of parallelism “in context” or “in probability”. An encoding device is assumed that assigns a codeword M to a stream M modulo N (M% N in C language), where N is the number of streams. The present invention provides encoded data from a current stream until a codeword is requested. Only after that the data switches to the next stream.

 In FIG. 22 shows one embodiment of a shifting device for a decoding device according to the present invention. The shifter 1600 is designed for four data streams. This provides four clock cycles for each shift operation. Alternating words consist of 16 binary bits, and the longest code word consists of 13 binary bits. The shifter 1600 includes four registers 1601-1604 connected to receive interleaved encoded data signals. The outputs of each of the registers 1601-1604 are connected to the inputs of the multiplexer 1605. The output of the multiplexer 1605 is connected to the input of the multi-register cyclic shift device 1606. The output signal of the multi-register cyclic shift device 1606 is supplied as input signals to the register 1607, the multiplexer and the registers 1608-1610 and the size block 1611. The output of the size block 1611 is connected to the accumulating adder 1612. The output signal of the accumulating adder 1612 is fed back and fed to the multi-register cyclic shift device 1606. The output signal of register 1607 is supplied as an input signal to the multiplexer and register 1608. The output signal of the multiplexer and register 1608 is supplied as an input signal to the multiplexer and register 1609. The output signal of the multiplexer and register 1609 is supplied as an input signal to the multiplexer and register 1610. The output of the multiplexer and register 1610 is aligned encoded data. In one embodiment, registers 1601-1604 are 16-bit registers, a multi-register cyclic shift device 1606 is a 32-13-bit multi-register cyclic shift device, and the accumulating adder 1612 is a 4-bit accumulating adder.

 Registers 1601-1604 receive 16-bit words from the inverse store type device and send them to the input of the multi-register cyclic shift device 1606. At each time point, at least 32 bits of non-encoded data are provided for the multi-register cyclic shift device 1606. To start, four registers 1601 -1604 is initialized with two 16-bit encoded data words. This allows you to always have at least one new codeword for each stream.

 As for R-codes, the dimensional block of codewords 1611 determines whether the codeword is “0” or “1N”, and if this codeword is “1N”, then how many binary bits after the character “1” are part of the current code word. A dimensional block providing the same function has been described in FIG. 15. For other codes, the technique of determining the size of a codeword is well known.

 The biasing device 1600 includes a reverse store type device consisting of four registers, three of which have multiplexed inputs. Each of the registers 1607-1610 is designed to accommodate at least one codeword, so that the length of the registers and multiplexers is 13 bits to accommodate the longest possible codeword. Each register is also associated with one control multivibrator (not shown), which indicates whether a particular register contains a codeword or is waiting for a codeword to be received from a multi-register cyclic shift device 1606.

 A reverse store-like device is never empty. You can use only one codeword per clock cycle and you can shift one codeword per time cycle. The shift delay is compensated because the system starts four codewords in advance. As soon as each codeword is shifted to ensure alignment of the output encoded data, the other codewords in the registers 1607-1610 are shifted towards the lower digits. When the left codeword in the inverse store type device is stored in the register 1602, the multi-register cyclic shift device 1606 causes the codewords to be read from the registers 1601-1604 through the multiplexer 1605 so as to fill the registers 1607-1609. Note that the inverse store type device can be designed to re-populate register 1607 with the next code word as soon as its code word is shifted to register 1608.

 A multi-register cyclic shift device 1606, a codeword size computing device 1611, and a selected accumulative adder 1612 manipulate a variable-length shift. The accumulating adder 1612 has four registers, one for each stream of encoded data, each of which contains a aligned current codeword for each data stream. The accumulating adder 1612 is a four-digit accumulating adder used to control a multi-register cyclic shift device 1606. The accumulating adder 1612 increments its value by the value of the input signal coming from the dimensional block of code words 1611. When the accumulating adder 1612 overflows (for example, every time shift count is 16 or greater), registers 1601-1604 are clocked for shifting. Each other shift of 16 bits causes a request for a new 32-bit word from a reverse store type device. The input signal of the accumulating adder 1611 characterizes the size of the code word, which is determined by the current code and the first one or two bits of the current code word. Note that in some embodiments, registers 1601-1604 must be initialized with encoded data before decoding begins.

 When the system requests a codeword, the registers in the inverse store-type device are clocked so that the codewords move to the output. When the multi-register cyclic shift device 1606 is ready to issue a new codeword, it is multiplexed into the first unoccupied register in the inverse store type device.

 In this embodiment of the invention, the next codeword signal from the binary generator is received before deciding to switch the streams.

 If it is not possible to guarantee that the next codeword signal from the binary generator will be received before deciding to switch the streams, the preview system illustrated in FIG. 23. The drawing shows in block diagram form a shifting device 1620 using a preview system. The shifting device 1620 includes a shifting device 1600, which produces the output signals of the current encoded data and the following encoded data. The current encoded data is fed to the input of the preprocessing logic block of code words 1624. The following encoded data is fed to the input of the preprocessing logic block of encoded words 1622. The outputs of both preprocessing logic 1621 and 1622 are connected to the inputs of multiplexer 1623. The output of multiplexer 1623 is connected to another input logical block processing codewords 1624.

 A logical device using a codeword is divided into two parts: a logical device for preprocessing codewords and a logical device for processing codewords. Two identical pre-processing conveyor units 1621 and 1622 operate before the interleaved stream can be shifted. One of the preprocessing units 1621, 1622 generates the appropriate information if the flow is switched, and the other generates information if the flow is not switched. When the flow is switched, the output of the preprocessing unit of the corresponding codewords is multiplexed by a multiplexer 1623 into a codeword processing logic 1624 that completes the operation with the corresponding codeword.

 Memory and context models outside the crystal.

 In one embodiment of the invention, it may be desirable to use multiple crystals for external storage or external context models. In such embodiments, it is desirable to reduce the delay between generating a bit and providing a bit for a context model that uses many integrated circuits.

 In FIG. 24 is a block diagram of one embodiment of a system with an external crystal of a context model 1701 and a crystal of an encoding device 1702 with memory for each context. Note that only blocks related to the context model are shown on the crystal of the encoder. Those skilled in the art will appreciate that the crystal of the encoder 1702 contains circuits for generating binary bits, probability estimates, etc. The crystal of the encoder 1702 includes a zero order context model 1703, context models 1704 and 1705, a selection logic 1706, a memory control circuit 1707, and a memory 1708. The zero order context model 1703 and context models 1704 and 1705 generate output signals that served on the inputs of the selection logic circuit 1706. Another input of the selection logic circuit 1706 is connected to the output of the external crystal of the context model 1701. The output of the selection logic circuit 1706 is connected to the input th device 1708. In addition, to the input of memory 1708 is connected the output of the control unit memory device 1707.

 The selection logic 1706 allows you to use either an external context model or an internal context model (for example, a zero-order context model 1703, context model 1704, context model 1705). The selection logic 1706 allows the zero-order inner part of the context model 1703 to be used even when the external context model 1701 is used. The zero-order context model 1703 provides one or more binary bits, while the external crystal of the context model 1701 provides the remainder. For example, the immediately preceding bits can represent feedback and return back from the zero order context model 1703, while the preceding bits go to the external context model 1701. Thus, time-critical information remains on the chip. This eliminates the delay in transmitting information off-chip for the last generated binary bits.

 In FIG. 25 is a block diagram of one system with an external context model 1801, external storage device 1803, and an encoding chip 1802. Some address lines of the storage device are driven by an external context model 1801, while others are driven by a “zero order” context model in the chip encoding device 1802. That is, a context from a just past decoding cycle is driven by a zero-order context model. This enables the chip of the decoding device to provide context information from a just past cycle with a minimum information transfer delay. The crystal of the context model 1802 is ahead of the rest of the information using binary bits decoded more long ago in the past, thereby allowing a delay in the transmission of information. In many cases, contextual information from a recently passed cycle characterizes a zero-order Markov state, and contextual information from a more distant past represents a higher-order Markov state. Shown in FIG. 25, an embodiment of the invention eliminates the information transfer delay that is inevitable when implementing the zero-order model in the external crystal of the context model 1802. However, there may still be a definition of the context element in order to delay the generated binary bits due to the chip of the decoding device 1802 and the storage device 1803.

 It should be noted that a different storage architecture may be used. For example, you can use a system with a context model and memory on one chip, and the encoder on another chip. In addition, the system may include an encoding chip with an internal storage device that is used for some contexts and an external storage device that is used with other contexts.

 In FIG. 26 shows a decoding device with a pipelined binary generator using a storage device. As shown in FIG. 26, the decoding device 1900 includes a context model 1901, a storage device 1902, a MOB to code 1903 conversion unit, a pipelined binary digit generator 1905, a storage device 1904, and a shifter 1906. The input to the context model 1901 includes decoded data from the pipelined a bit sequence generator 1905. The inputs of the shifter 1906 are connected to receive encoded data. The output of the context model 1901 is connected to the input of the storage device 1902. The output of the storage device 1902 is connected to the block for converting the state of the MOB to code 1903. The output of the block for converting the MOB mode to code 1903 and the output of aligned encoded data from the shifting device 1906 are connected to the inputs of the binary generator 1905. Storage device 1904 is also connected to the binary generator 1905 using a bi-directional bus. The output of the binary generator 1905 is decoded data.

 Under the influence of encoded data at the input of the context model 1901, a context element appears at its output. The encoded context signal element is used as an address for accessing the storage device 1902 based on the encoded context signal element to obtain a probabilistic state, which is received by the module for converting the state of the MOB into code 1903, which generates a probability class under the action of the probabilistic state. The probability class is then used as an address to access memory 1904 to obtain a run count. After that, the run count is used by the binary generator 1905 to generate decoded data.

 In one embodiment, memory 1902 is a 1024 * 7 binary bit memory (1024 is the number of different contexts), while memory 1904 is a 25 * 14 binary bit memory (25 is the number of different run counts).

 Since the state of the binary digit generator (run counts, etc.) is associated with probability classes, and not with elements of encoded context signals, there is an additional pipeline delay before the binary bit is presented for using the context model. Due to the fact that updating the state of a binary generator takes a lot of clock cycles (the delay for re-accessing the state memory of a binary generator), for each probability class, many states of a binary generator will be used. For example, if the pipeline takes six clock cycles, then the state memory of the binary generator has six input messages per probability class. A counter is used to select the appropriate memory location. Even with a large number of input messages per probability class, the memory size is usually less than the number of contexts. The memory can be implemented either in the form of a plurality of data banks of a random access statistical storage device, or in the form of a multi-port register file.

 Since one run count may be associated with multiple contexts, an embodiment of the invention should update the state of the probability estimate of one or more contexts. In one embodiment of the invention, the state of the MOW context is updated, which causes the end of the run.

 Instead of requiring reading, modifying, and writing the run count before they can be read again, the run count can again be used after the modification is completed. In FIG. 39 is a timing chart of a decoding operation in one embodiment of the present invention. Shown here are three-cycle decoding operations. The names of the signals are listed in the left column of the timing chart. The reliability of the signal during any one cycle is indicated by a bar during the cycle (or part thereof). In some cases, the block or logic responsible for providing a valid signal is shown next to the indication of a valid signal in a dashed box. In addition, designations of examples of specific elements and blocks disclosed herein are provided. Note that any part of the signal that extends into another cycle indicates the reliability of the signal only for that period of time that is occupied by the signal in this other cycle. In addition, some signals are shown as separately reliable for more than one cycle. An example of this is a temporary run count signal, which is valid at one point at the end of the second cycle and then again during the third cycle. Note that this indicates that the signal is simply recorded at the end of the cycle. The list of dependencies is also shown in table. 18, showing the dependence of the same or previous clock cycle to the current time, and this signal is determined reliable.

 In some embodiments of the invention, the decoding device must simulate a limited reordering buffer of the encoding device. In one embodiment of the invention, this simulation is performed with implicit signaling (signaling).

 As explained above with respect to the encoder, when the codeword is started in the encoder, a place for the codeword is reserved in the corresponding buffer in the order of the codewords in which they should be placed in the channel. When reserving the last space in the buffer for a new codeword, some codewords are placed in a compressed binary stream, regardless of whether they are fully defined.

 If you need to complete an incomplete codeword, you can select a short codeword and precisely set the characters accepted so far. For example, in the R-encoder system, if it is necessary to prematurely end the code word for a series of 100 BVS characters in the run code with a maximum run length of 128 characters, you can use the word for 128 BVS characters, since this precisely defines the first 100 characters.

 As an alternative, you can use a code word that defines 100 characters of BVS followed by MVS. When the codeword is finished, it can be removed from the reordering buffer and added to the codestream. This may make it possible to place previously completed codewords in the code stream as well. If forcing the completion of one incomplete codeword results in the removal of the codeword from the filled buffer, then the encoding may continue. If one buffer is still full, the next codeword should end again and be added to the codestream. This process continues until the buffer device, which was full, is no longer complete. A decoding device can simulate an encoding device for implicit signal transmission using a counter for each memory cell for information about the state of the binary generator.

 In one embodiment, each binary counter (in this example of a probability class) has a counter that has the same size as the head or tail counters in encoders (e.g., 6 binary bits). Each time a new run is started (a new codeword is selected), the corresponding score is loaded along with the size of the codeword memory. Each time a run is started (a new codeword is selected), all counters receive a negative increment. Any counter that reaches zero causes the corresponding run count to be cleared (and the sign of the presence of MVS is suppressed).

 Alarm options for destination memory.

 Real-time coding in the present invention requires the decoding device to manipulate runs of BVA characters, followed by no MVC, and which do not represent the maximum run length. This occurs when the encoder starts running the BWS characters, but does not have a sufficiently limited reordering device to wait for the run to complete. Under this condition, it is required that the new codeword be decoded at the next time when this context element of the encoded signal is used, and a signal must be sent to this decoder about this state. Three potential methods for modifying a decoding device are described below.

 When the buffer is full, the count of runs of the element of the encoded context signal or probability class that is being supplanted should be reset. To effectively accomplish this, it is useful to store in the codeword memory a coded context signal element or a probability class. Since this is only necessary for runs that do not yet have codewords associated with them, you can share the storage device used to store the codeword. Note that in some systems, instead of crowding out an incomplete codeword, it is possible to make binary bits go into the context and (or) the probability class of the codeword, which is delayed in the buffer when it is filled. The decoding device determines this and uses the corresponding (wrong) element of the encoded context signal or probability class.

 When signaling in a stream, codewords are used to transmit a signal to a decoding device. In one embodiment of the invention, the definitions of the codes R2 (k) and R3 (k) are changed to include runs of non-maximum lengths of BVA, not followed by MVS. This can be accomplished by adding one bit to the codeword, which should appear with the least probable character. This gives a uniquely decoded prefix for run counts of non-maximum length. In the table. Figure 19 shows the replacement of the R2 (2) codes, enabling signaling in the stream. The disadvantages of this method are that it is necessary to change the decoding logic of the R code, and that there is a cost of compression every time a code word appears with the least probability.

 In some embodiments of the invention, the decoding device performs implicit signaling using timestamps. A counter tracks the current “time”, incrementing each time a codeword is requested. In addition, whenever a codeword is started, the current "time" is stored in a memory associated with the codeword. Always after the first use of the codeword, the corresponding stored value of the “time” plus the size of the reordering buffer of the encoder is compared with the current “time”. If the current “time” is longer, an implicit signal is generated, so a new codeword is requested. In this way, a limited reordering memory is encoded in the encoder. In one embodiment, a sufficient number of bits are used for the "time" values to enable all codewords to be enumerated.

 To reduce the required memory capacity, the number of bits used for time stamps is kept to a minimum. If timestamps use a small number of binary digits so that time values are reused, care should be taken to ensure that all previous timestamps are marked before the counter starts the reused time values. Suppose that N is a larger value from the number of address binary bits for a queue or state memory of a binary generator. You can use timestamps with N + 1 binary digits. The state memory of the binary generator must provide many accesses, for example, two reads and two records per decoded binary bit. For cycling the state memory of a binary generator, a counter is used that gives one increment for each decoded binary bit. Any sufficiently “old” memory cell is cleared, therefore, a new codeword is sampled when used later. This ensures that all timestamps are checked before any time value is reused.

 If the state memory of the binary generator is smaller than the queue, then it is possible to reduce the counting speed (time stamp counter) and the required memory bandwidth. This is because each timestamp (one for the state memory of the binary digit generator) should be checked only once during the set of cycles required to use the entire queue. In addition, storing time stamps in a separate memory can reduce the required memory bandwidth. In systems using the codewords "0" for partial runs, there is no need to check timestamps for the codewords "1N". In systems using the "1N" codewords for partial runs, the timestamp should only be checked before the generation of the MVS.

 In some embodiments, implicit signaling is performed by a queue during decoding. This method may be useful in a half-duplex system where decoding uses encoding hardware. The operation of the queue is almost the same as with encoding. When a new codeword is requested, its index is queued and marked as invalid. When the data from the code word ends, its contents in the queue are marked as true. When data is output from the queue in order to provide a piece of memory for new codewords, then if the output data is marked as invalid, the information about the state of the binary generator under this index is cleared. This cleanup operation may require the state generator of the binary digits to support additional write operations.

 In contrast, explicit signaling reports a buffer overflow in the form of data compression. A possible implementation of this may be to have an auxiliary context element that is used once for each normal decoding of the context element or once for each decoded codeword. The decoded binary bits from the auxiliary context element indicate whether a condition for the need for a new codeword occurs, and the new codeword should be decoded taking into account the corresponding normal context element. In this case, the code words for this special context should be properly reordered. Since the use of this context is to some extent a known function for the reordering block (usually used once for each codeword), the memory required to reorder the auxiliary context can be limited or implicitly modeled. In addition, you can limit the possible codes provided for this auxiliary context.

 Implicit signaling models the encoder's limited buffer during decoding to generate a signal that indicates that a new codeword should be decoded. In one embodiment, a time stamp is stored for each context. In one embodiment, the reordering buffer of a limited size of the encoder is modeled directly. In a half-duplex system, since a decoding scheme of an encoding device is used in decoding, it can be used to generate signals for a decoding device.

 The exact implementation of implicit signaling depends on the features of how the encoder recognizes and operates on the state of a full buffer. In the case of a system using an integrated queue with a fixed location, the use of multiple head pointers allows the selection of the state corresponding to the "full buffer". If you have a specific implementation of the encoding device, you can create the appropriate model.

 The following describes the operation of the encoder and the model for use by a decoder of a combined order with a fixed distribution of flows in parallel with the probability system. For this example, it was suggested that the reordering buffer has 256 cells, 4 interleaved streams are used, and each interleaved word consists of 16 binary bits. When the buffer contains 256 input messages, the contents must be sent to the binary unit (for example, the binary unit) before the 257th codeword can be placed in the queue. If necessary, the contents may be squeezed out earlier.

 In some systems, moving the first message in the buffer requires moving a sufficient number of bits to complete the whole interleaved codeword. Therefore, if 1-bit codewords are possible, moving 0 codewords may also require moving codewords 4, 8, 12, ..., 52, 56, 60 for 16-bit interleaved words. To ensure that the entered buffer data is reliable data, the formation of content filling, as the memory is full, can be performed at the addresses of 64, 192 cells from the cell where the new codeword is entered (256-16 • 4 = 192).

 The decoding device has a counter for each probability. When a new codeword is used to start a run, 192 is loaded into the counter. At any time when a new codeword is used by any probability, all counters receive a negative increment. If any counter reaches zero, the run length for this probability is set to zero (and the sign of the presence of MVS is suppressed).

 It may be convenient to use numerous data banks on the RAM (multi-port memory, high-speed memory simulation, etc.), one data bank for each stream of encoded data. This will allow all the blocks of the arrangement of binary bits to simultaneously receive data, so that the reading of multiple codewords for a particular stream does not interfere with reading by other streams.

 In other systems, a plurality of binary arrangement blocks must make a decision for a single memory based on the order of the codewords as they are stored in the buffer. On such systems, outputting content from the buffer may not complete the interleaved word. Each binary arrangement unit typically receives some portion of the interleaved word in the sequence. Each binary arrangement unit receives at least the number of binary bits equal to the length of the shortest codeword (e.g. 1 bit), as a maximum, the number of binary bits equal to the length of the longest codeword (e.g. 13 bits). Alternating words cannot be released before they are completed, and must be issued in initialization order. In this example, the binary unit may have 13 interlaced words for the buffer, this is the maximum number of words that can be completed with code words of maximum length, while the other stream has an interlaced word delay, that is, it accepts code words of minimal lengths.

 A system in which each codeword requires two records and one memory read may be less suitable for hardware implementation than a system that provides two records and two reads. If, for example, a system with four streams were required, then blocks 1 and 2 of the arrangement of binary digits could share one reading cycle of memory, and blocks 1 and 3 of arrangement of binary digits could share another reading cycle (or any other arbitrary combination) . Although this would not ensure a reduction in the required buffer size, it would allow for a higher transmission rate to the binary unit, which would allow the binary unit to better use the bandwidth of the encoded data channel.

 Systems with a fixed capacity storage device.

 One of the advantages of a system having many binary generator states per probability class is that the system can provide lossy coding when the storage device is full of fixed capacity. This may be useful in the case of image compression for the framebuffer and other applications where only a limited amount of encoded data can be stored.

 In the case of systems with a fixed capacity storage device, each of the multiple states of the binary generator for each probability is assigned a piece of data. For example, each of the eight states can be assigned to a specific bit matrix for eight bit data. In this case, a shifting device is also assigned to each piece of data as opposed to shifting devices sequentially providing the next codeword. It should be noted that there is no need to share data using a bit matrix. In addition, interleaving is not performed in the encoder; each piece of data is simply arranged in bits. Each piece of data is assigned a storage device.

 The memory management of the encoded data is provided in the case of systems storing all data in a storage device of fixed capacity, and in the case of systems transmitting data to a channel with a maximum allowable bandwidth. In both of these systems, a gradual reduction in the capabilities of a lossy system is desirable. Different data streams are used for data of various importance, so less significant streams may or may not be stored when there is not enough memory or bandwidth available.

 When using memory, encoded data must be stored so that sampling can be performed where less important data streams can be discarded without losing the ability to decode important data streams. Since the encoded data is variable in length, dynamic memory allocation can be used. In FIG. 38 shows an example of a dynamic memory allocation unit for three encoded data streams. Register file 3100 (or other storage device) contains a pointer for each stream plus another pointer to indicate the next free memory location. The memory 3101 is divided into pages of fixed capacity.

 In the initial position, each pointer assigned to a stream indicates the beginning of a memory page, and a free pointer indicates the next available memory page. The encoded data from a particular stream is stored in a memory location addressed by a corresponding pointer. Then the pointer increments for the next memory location.

 When the index reaches its maximum for the current page, the following happens. The address of the beginning of the next free page (filled in the free index) is remembered with the current page. (You can use either part of the encoded data memory, or a separate memory or register file.) The current pointer is set to the next free page. A free pointer is incremented. These actions assign a new memory page to a specific thread and provide such a connection that decoding can determine the placement order.

 If all pages of memory are used, and there is still more important data in the stream than less important data in memory, you can proceed as follows. In all cases, the memory allocated to less significant data is intended for the flow of more important data and additional data is not stored from the stream of less significant data.

 First, the page currently in use by the less important stream is simply allocated for more important data. Since in more typical encoding devices, the statistical code uses information about the internal state, all less important data previously stored on this page is lost.

 Secondly, the page currently in use by the less important stream is simply allocated to the more important data stream. Unlike the previous case, the pointer is positioned at the end of the page, and when more important data is written on the page, the corresponding pointer takes a negative increment. This has the advantage of storing less important data at the top of the page if the flow of more important data does not require a whole page.

 Thirdly, instead of the current page of reassigned less important data, you can reassign any page with less important data. This requires independent encoding of the encoded data for all pages, which may reduce compression achieved. It also requires identification of non-encoded data corresponding to the top of all pages. Since you can discard any page of less important data, you get more flexibility in gradually reducing lossy coding capabilities.

 The third option can be especially attractive in a system that achieves a fixed degree of compaction across all areas of the image. Image areas can be assigned a specific number of pages of memory. Whether less important data is stored or not may depend on the compaction achieved in a particular area. The memory assigned to the area may not be fully used if the required lossless compression is less than the capacity of the assigned memory. Achieving a fixed degree of compaction in the image area can provide random access to image areas.

 To make better use of the total capacity available in the memory system, you can use the ability to write data to each page from both ends. When all pages are distributed, any page that has a sufficient free area at the end can be assigned for use from the end. The ability to use both ends of the page needs to be correlated with the cost of maintaining location tracking where two types of data meet. (This is different from the case when one of the data types was not important and could simply be overwritten).

 Now consider a system in which data is transmitted to a channel instead of being stored in memory. Pages of a fixed memory capacity are used, but only one page per stream is needed (or perhaps two if ping-pong reading is required to ensure channel amortization, so that when writing to one page on the other, it can be read to output data). When a memory page is full, it is transferred to the channel, and the memory cell can be reused as soon as the page is transferred. In some applications, the capacity of a memory page may represent the capacity of data packets used in a channel, or the volume of a plurality of packets.

 In some communication systems, for example with asynchronous transfer mode (ATM), packets may be prioritized. ARP has two priority levels: primary and secondary. Secondary packets are only transmitted if there is sufficient bandwidth. To determine which of the packets is primary and which is secondary, a threshold value can be used. In another method, you can use the threshold value in the encoder so as not to transmit streams that are less important than the threshold.

 In FIG. 27 is a block diagram of a system with separate generators for each code. The decoding system 2000 includes a context model 2001, a storage device 2002, a unit for converting the state of the MOB to code 2003, a decoding device 2004, binary generators 2005A-n and a shifting device 2006. The output of the context model 2001 is connected to the input of the storage device 2002. The output of the storage device 2002 is connected to the input of the unit for converting the state of the MOB to code 2003. The output of the unit for converting the state of the MOB to code 2003 is connected to the input of the decoding device 2004. The output signal of the decoding devices and 2004 is supplied as an enable signal to 2005A-n binary generators. The 2005A-n binary generators are furthermore connected to receive the output of the encoded data from the shifter 2006.

The context model 2001, the storage device 2002, and the unit for converting the state of the MOB to code 2003 work similarly to their counterparts in FIG. 26. The context model 2001 produces elements of encoded context data. Storage device 2002 provides a probabilistic state based on a context element. The probabilistic state is adopted by the unit for converting the state of the MOB into code 2003, which generates a probability class for each probabilistic state. The decoding device 2004 unlocks one of the binary generators 2005A-n based on the decoding of the probability class. (Note that the decoding device 2004 is a circuit of a decoding device for converting M to 2 ^M, like the well-known decoding device 74 • 138 3: 8 - this is not a statistical decoding decoding device). Note that since each code has a separate binary generator, some binary generators may use codes other than R codes. In particular, the code for probabilities of the order of 60% can be used to better transition the probability domain between R2 (0) and R2 (1). For example, in table. 20 shows such a code.

 If you want to get the desired performance, then to ensure the required speed of decoding data, you can pre-decode one or more binary bits. In some embodiments of the invention, in order to avoid the need to update a large run count, each clock cycle breaks up both the encoding of code words and the count of runs for these codes.

 The binary digit generator for R2 (0) codes is simple. A codeword is requested each time a binary digit is requested. The generated binary bit is simply a codeword (EXCLUSIVE OR with MOV scheme).

 Codes for a short run length, for example, R2 (1), R3 (1), R2 (2), R3 (2), are manipulated as follows. All binary bits in the codeword are decoded and stored in a state machine, which contains a small counter (1, 2, or 3 binary bits, respectively) and a binary bit of the presence of MVS. The counter and the binary bit of the presence of the MVS function as an R-code decoding device. In the case of longer codes, such as R2 (x), R3 (k) for k> 2, the binary generators are divided into two blocks, as shown in FIG. 28. Here, the binary generator for R2 (k) codes, where k> 2, is shown as consisting of a block of short runs 2101 and a block of long runs 2102. Note that although this design is intended for use with codes R2 (k> 2), her work with R3 codes (k> 2) will be the same (and this is clear to specialists in this field of technology).

 The short run block 2101 is connected to receive an enable signal and a codeword (0 ... 2) as input signals for the binary digit generator, as well as an all-zeros signal (in Fig. 28, all ones) and a zero count signal "(indicating the zero count) from the long run block 2102. In response to these input signals, the short run block 2101 provides a decoded binary bit and an indication of the next signal, which signals that a new code word is needed. The short run block 2101 also generates an account unlock signal, an account load signal and a maximum count signal for the long run block 2102. The long run block 2102 is also connected to receive a code word (k ... 3) as an input signal to the binary generator.

 The short run block 2101 manipulates runs up to 4 in length and is similar to the binary generator R2 (2). In one embodiment, the short run block 2101 is the same for all R2 codes (k> 2). The purpose of the long run block 2102 is to determine when to output the last of 1-4 binary bits of the run. The block of long runs 2102 has inputs, a logical circuit AND, and a counter, the size of which changes with a change in k.

 One embodiment of the long run counting unit 2102 is shown in FIG. 29. The block of long runs 2102 contains a logic circuit And 2201 connected to receive a code word (k ... 3), and gives a signal "all units" in the form of a logical "1" if all the binary digits in the code word are units, thereby showing that the codeword is a “1N” codeword and that the run count is less than 4. A logic circuit NOT 2202 is also connected to receive the codeword and inverts it. The output of the logic circuit NOT 2202 is connected to one input of the binary bit counter 2203. The binary bit counter 2203 is also connected to receive an account unlock signal, an account load signal, and a maximum account signal. In response to the input signals, the binary counter 2203 generates a zero-count signal.

 In one embodiment of the invention, the counter 2203 is a counter of k-2 bits and is used to break the accounts of long runs into runs of four BVS and, possibly, some remainder. The account unlock signal indicates that four BVS characters are displayed and the counter should receive a negative increment. The count loading signal is used when decoding the “1N” code words and causes the counter to be loaded by adding binary bits of the code word from k to 3. The maximum count signal is used when decoding the “0” code words and loads the counter with its maximum value. The output of the zero counter indicates when the counter is zero.

 One embodiment of the short run counting unit 2101 is shown in FIG. 30. The short run counting unit comprises a control module 2301, a two-bit counter 2302 and a three-bit counter 2303. The control unit 2301 receives an enable signal, a code word (0 ... 2), and all-one and zero-count signals from the long run block . A two-digit counter is used to count four-digit runs of BVS characters that are part of longer runs. Counter R2 (2) and the MVC binary digit (a total of three binary digits) 2303 are used to generate 1-4 binary digits at the end of the run. An enable input signal indicates that a binary digit should be generated at the output of the binary digits. Zero counting is input when indications are not confirmed that a run of four BVS characters should be issued. Whenever the counter BVS 2302 reaches zero, an output signal to unlock the account is generated. When the input signal of the zero account is generated, either the MVS counter R2 (2) is used, or a new codeword is decoded and the next output signal is generated.

 When a new codeword is decoded, the actions performed are determined by entering the codeword. If there is a code word "0" at the input, the counter of the BVS 2302 is used and the output signal of the maximum of the count is generated. In the case of new words “1N”, the first three binary digits of the code word are loaded into the counter R2 (2) and MBC 2303, and an output signal to load the account is generated. If an input signal of all units is generated, then the counter R2 (2) and MBC 2303 is used to generate binary digits, otherwise the BVS counter is used until an input signal of zero count is generated.

 From a system point of view, the number of codes should be small for the system to work well, usually 25 or less. The capacity of the multiplexer needed to output the binary bit and the next codeword, and the decoding device needed to unlock a specific binary generator for fast operation should be limited. In addition, the branching of the codeword from the shifting device should not be too high for high-speed operation.

 Separate binary generators for each code provide pipelining capabilities. If all codewords have given at least two binary digits, the processing of codewords can be pipelined in two cycles instead of one. This could double the speed of the decoding device if the binary generators represented the limiting part of the system. One way to accomplish this is with a codeword of zero run length (the codeword indicates only MBC) followed by one binary bit, which is the next non-encoded binary bit. They can be called RN (k) +1 codes, and they can always encode at least two binary bits. Note that the codewords R2 (0) and possibly some of the other short codewords do not need pipelining to improve performance.

 Separate binary generators resort to the use of implicit signaling. Implicit signaling intended for encoding with a finite storage device can be performed in the following way. Each binary generator has a counter having a queue address size, for example, 9 bits, when a 512-bit sequence is used. Each time the binary generator uses a new code word, the counter is loaded with the maximum value. Whenever a generator requests a codeword, the counters of all binary generators receive a negative increment. Whenever the counter reaches zero, the mode of the corresponding binary generator is cleared (for example, the BVS counter, the R2 (2) counter and the MVC and the long run counter are cleared). Since resetting can occur even if a particular binary generator is not unlocked, there is no problem with state counts.

 Initialization of the storage device for each element of the context.

 In cases where the storage device for each context element contains probability estimation information, additional memory bandwidth may be required to initialize a decoding device (eg, storage device) very quickly. Quick initialization of the decoding device can be a problem when the decoding device has many contexts and all of them need to be cleared. When the decoding device provides many contexts (1k or more) and it is not possible to completely clear the memory, an unacceptably large number of clock cycles will be required to clear the memory.

 To quickly clear contexts, in some embodiments of the present invention, an additional binary bit is used, called here the initialized state binary bit, which is stored with each context. Thus, the incremental binary bit is stored along with the state of the MOB (for example, 8 bits) for each context.

 In FIG. 31 shows a storage device for each context element and initialization control logic. A context memory 2401 is shown connected to register 2402. In one embodiment of the invention, register 2402 includes a one-bit register that indicates the current proper state for the initialized state element. The register 2402 is connected to one input of the EXCLUSIVE OR 2403 logic circuit. The other input of the EXCLUSIVE OR 2403 logic circuit is connected to the output of the storage device 2401. The output signal of the logic circuit EXCLUSIVE OR 2403 is a reliable signal and is fed to the input of the control logic 2404. Other inputs of the logic circuit 2404. control circuits are connected to the output of the counter 2405 and the signal of the context discretization element. The output of the control logic 2404 is connected to the selective inputs of the multiplexers 2406 and 2407 and to the input of the counter 2405. Another output of the control logic 2404 is connected to the selective input of the multiplexer 2406. The inputs of the multiplexer 2406 are connected to the output of the counter 2405 and the indication signal of the context sampling element. The output of the multiplexer 2406 is connected to the storage device 2401. The inputs of the multiplexer 2407 are connected to the signal of the new state of the MOB and the signal zero. The output of the multiplexer 2407 is connected to one input of the storage device 2401, the output of the storage device 2401 and the initial MOB signal are connected to the input of the multiplexer 2408. The output signal of the multiplexer 2408 is an output signal of the status of the MOB.

 The value in register 2402 is supplemented with each execution of the decoding operation (i.e., with each data set, and not with each decoded binary bit). The EXCLUSIVE OR 2403 logic circuit compares the validity of each selected memory location with a register value to determine whether the selected memory location is valid for a given decoding operation. This is done using an EXCLUSIVE OR 2403 logic circuit, checking to see if the initial state binary bit matches the proper state in register 2402. If the data in the memory 2401 is not reliable, the control logic 2404 causes the data to be passed by the state to code logic and instead use of the initial state of MOB. This is done using multiplexer 2408. When a new MOB state is written to the memory device, the initialized binary bit is set to the current value of the register, so that when it is accessed again, this value will be considered reliable.

Each context element storage device must have its own initial state binary bit set to the current value of the register before another decoding operation can begin. Counter 2405 performs steps across all memory locations to ensure that they are initialized. Whenever a context element is used, and its MOB mode is not adjusted, an unused write cycle can be used to test or correct the memory cell indicated by counter 2405. After the decoding operation is completed, if counter 2405 has not reached its maximum value, the remaining contexts are initialized before the next operations. The following logic is used for the control operation:
write it = false;
counter = 0;
all initialized = false;
although (counter <maximum context data encoding element +1)
reading the MOB mode from the context memory
if ((counter = reading the context data encoding element) and (writing this))
record this = false
counter = counter + 1
if (MOB mode is changed)
recording a new MOB mode
even if (recording this)
recording the initial mode of MOB in the memory cell "counter"
counter = counter + 1
yet
reading memory "counter"
if (the initialized binary bit in the read cell is in an error state)
spelling it = true
yet
counter = counter + 1
all initialized = true;
although (decoding)
reading the MOB mode from the context memory
if (DOM state is changed)
recording a new MOB mode.

 The MOB module used in the present invention may include an adaptation circuit that allows faster adaptation regardless of the amount of data available. When used, the present invention as a means of providing a more accurate estimate will initially allow for faster decoding adaptation and much slower adaptation when more data is available. Moreover, the MOV can be fixed during the implementation of the state table / finite state machine of the MOB in a user-programmable gate array (PPVM) or application-oriented integrated circuits (ISPO).

 In the table. 21-26 described a number of finite state machines for estimating probability. Some tables do not use R3 codes or long codes for reduced hardware prices. In all tables, with the exception of table. 21, special “fast adaptation” modes are used, which are used for quick adaptation when starting coding before the first MVS appears. These quick adaptation modes in the tables are shown in italics. For example, from table. 22 it can be seen that when decoding starts, the current state represents state 0. If BWS appears, the decoding device goes into state 35. As long as the BWS symbols appear, the decoding device goes up in the direction from state 35, eventually turning into state 28. If in MVS appears for some time, the decoding device switches from clearly defined fast adaptation modes to a mode that represents the correct state of probability in relation to data that has been received so far.

 Note that for each table, after receiving a certain number of BVS symbols, the decoding device leaves the fast adaptation modes. In the desired embodiment, after exiting the quick adaptation modes, there is no mechanism for returning to them, with the exception of restarting the decoding process. In other embodiments, the implementation of the state table can be designed to re-enter these modes of fast adaptation by providing the possibility of faster adaptation, the present invention enables the decoding device to enter more asymmetric codes faster, thereby benefiting from improved compression. Note that quick adaptation can be eliminated for a specific table by changing the contents of the table for the current state 0 so that the table goes only one state up or down depending on the input data.

 For all these tables, the data for each state represents the code for this state, the next state with positive correction (up) and the next state with negative correction (down). Asterisks indicate the states when the BVS symbols should change with a negative correction.

 Adding a quick adaptation to the probability estimate will only help when starting coding. To improve adaptation during coding, other methods can be used when the statistics of the context elements change faster than the MOV status tables described above can track. One way to maintain fast adaptation throughout coding is to add an acceleration element to update the state of the MOB. This acceleration can be entered into the MOV status table by repeating each code a constant number of times (for example, 8). Then the acceleration element M (for example, a positive integer) can be added or subtracted from the current state when updating. When M is 1, the system works the same way as without acceleration, and the slowest adaptation occurs. When M is greater than 1, faster adaptation occurs. Initially, M can be set to a value in excess of 1, providing initial quick adaptation.

 One method of updating the value of M according to the present invention is based on a series of consecutive codewords. For example, if a predetermined number of codewords appears sequentially, then the value of M increases. For example, if four consecutive codewords are "0" "0" "0" "0" or "1N" "1N" "1N" "1N", then the value of M increases. On the other hand, to reduce the value of M, a switching pattern between the code words “0” and “1N” can be used. For example, if four consecutive codewords are "0" "1N" "0" "1N" or "1N" "0" "1N" "0", then the value of M decreases.

 Another acceleration method uses state tables in which each code is repeated S times, where S is a positive integer. S is the reciprocal of the acceleration parameter. When S is equal to one, adaptation is fast, and when S is greater, adaptation is slower. The value of S can initially be set to 1 to provide an initial quick adaptation. Using a method similar to that described above, the value of S can be adjusted when four consecutive codewords are "0" "0" "0" "0" or "1N" "1N" "1N" "1N". In this case, the value of S decreases. In contrast, if four consecutive codewords are "0" "1N" "0" "1N" or "1N" "0" "1N" "0", then the value of S increases.

 The definition of consecutive codewords can have several meanings. In context-based systems, consecutive codewords may refer to consecutive words in a single context element. In a "probability" system, consecutive codewords may refer to consecutive codewords in a single probability class. Alternatively, in one system, consecutive codewords may refer to consecutive codewords in a broad sense (not related to context elements or probability class). In the case of these three examples, the binary digits required to store the codeword archive are 3 x the number of context elements, 3 x the number of probability classes and 3 x, respectively. Storing acceleration for each context element can provide better adaptation. Since poor tracking is often caused by a general change in unencrypted data, a good fit can also be provided by determining the overall acceleration.

 System applications.

 One of the benefits of any compaction system is that it reduces the memory requirements for a data set. The parallel system of the present invention can be replaced for any current application with a lossless coding system, and can be used in systems that work with audio, text data, computer-executable databases, or other digital data, signals or symbols. Examples of lossless coding systems include facsimile compression, database compression, bitmap graphic compression, and conversion coefficient compression in image standards such as the JPEG standard (working group on digital video and cartoon image standards) and the MPEG standard (expert group on moving images - the standard for moving image compression). The present invention provides the ability to implement small efficient hardware and implementations of relatively high-speed software, providing a good choice even in the case of applications that do not require high speed.

 The advantage provided by the present invention compared with the prior art is that it can operate at very high speeds, especially when decoding. Thus, the present invention can make full use of expensive high-speed channels, such as high-speed computer networks, satellite and terrestrial relay communication channels. In FIG. 35 illustrates a system in which a broadcast network or high-speed network of computers provides data for decoding system 2801. System 2801 performs parallel coding of data when generating output data. The current hardware entropy (such as a Q encoder) can reduce the throughput of these systems. All these systems are designed so that at high cost they should have a large bandwidth. The counter is designed to have a decoding device that slows throughput. The parallel system of the present invention not only provides these high throughputs, it does increase effective throughput because data can be transmitted in compressed form.

 The parallel system of the present invention is also applicable to provide more efficient throughput due to moderately fast channels such as a Service Integrated Services Integrated Services Digital Network (ISDN), CD-ROMs, and Small Computer System Interface (SCSI) ) Such a bandwidth matching system is shown in FIG. 36, while data from sources such as a rewritable compact disc, internet, small computer interface or other similar source are supplied to a decoding system 2901 that receives and decodes data in order to generate an output signal. These channels are still faster than some of the currently used encoders. Often these channels are used to serve a data source that requires a larger bandwidth than for a channel, such as real-time video or a computer environment (multimedia). The system according to the present invention can perform a bandwidth matching function.

 The system of the present invention is a transitional embodiment for a part of the encoder of a statistical code of a television system operating in real time, similar to the standards of high definition television (HDTV) and television of the moving picture expert group (MPEG). Such a system is shown in FIG. 37. A real-time television system includes a decoding system 3001, which receives compressed image data. System 3001 decodes data and outputs it to a lossy decoding device 3002. A lossy decoding device 3002 may be a color transmitting, color converting, and downsampling part of a moving picture compression standard (MPEG) high definition television decoder. As a monitor 3003, you can use a television or video monitor.

 While many changes and modifications of the present invention should undoubtedly be apparent to those skilled in the art after reading the description, it should be clear that the specific embodiment shown and described by way of illustration is not intended to be construed as restrictions. Therefore, reference to details of a preferred embodiment of the invention is not intended to limit the scope of the claims, which list only features that are considered as the essence of the invention.

 Thus, a method and apparatus for parallel decoding and encoding are described.

Claims (121)

 1. A method of encoding a data stream, in which the input data stream is converted to obtain a sequence of compressed output data, characterized in that, respectively, the data stream generates code words representing the data stream, the code word information comprising a plurality of code words that are generated from the data the data stream processed in parallel, encoded data is formed according to the codeword information, each of which when generating encoded data nozhestva codewords give in order of respectively the top portion of the data stream representing each code word.  2. The method according to claim 1, characterized in that each of the many code words is issued at the beginning of each run.  3. The method according to claim 1, characterized in that when generating encoded data, variable-length codewords are combined into fixed-length data structures.  4. The method according to claim 3, characterized in that in each of the data structures of a fixed length includes a word formed with alternation.  5. The method according to claim 1, characterized in that the encoded data is output so that the code words are ordered in decoding order.  6. The method according to claim 1, characterized in that they further carry out the ordering of code words.  7. The method according to claim 1, characterized in that when generating codeword information, they generate data of the probabilistic state of the codeword, select the binary generation code based on the probabilistic state, and access the memory to obtain a run count associated with the probability class.  8. A coding system for a data stream comprising a coding device connected to receive a data stream, characterized in that the coding device is configured to generate codeword information comprising a plurality of codewords, wherein a plurality of codewords are generated by the coding device from data of the data stream processed in parallel , and said system further comprises a reordering unit connected to an encoding device for generating encoded data, respectively data codewords, the reordering unit delivers reordering codewords produced by the encoder in decode order so that the order issued by the code words corresponding to the beginning portion of the data stream representing each code word.  9. The system of claim 8, wherein the reordering unit provides storage of code words indicating the size of the code words.  10. The system according to claim 9, characterized in that the code words IN are reordered so that the high order bit "1" indicates the length of each code word.  11. The system of claim 8, wherein the reordering unit includes at least one run count reordering unit for generating each of said plurality of codewords in the codeword information at the beginning of each run, and at least one unit Binary layouts designed to combine variable-length codewords into fixed-length data structures.  12. The system according to p. 11, characterized in that each of the data structures of a fixed length includes a word formed with alternation.  13. The system of claim 8, characterized in that the reordering unit is designed to organize code words.  14. The system according to item 13, characterized in that it contains a storage device connected to the reordering unit for storing code words in a predetermined order.  15. The system of claim 8, wherein the encoding device includes a context model block, a probability estimation block connected to the context model block, and a binary bit generator block connected to the probability estimation block and intended to generate a codeword according to the stream data.  16. The system of clause 15, wherein the encoding device includes a storage device for storing a plurality of run accounts, and when accessing the storage device, probability classes are used from a probability estimation unit for issuing one of a plurality of run accounts to a binary generator block for use as part of the codeword information.  17. The system of clause 15, wherein the block of the binary generator includes a binary generator, configured to generate codeword information in response to an indexing signal and an indication of the most probable symbol or least probable symbol (BVS / MVS), and a storage device connected to the binary generator, designed to issue a run count to the binary generator, moreover, the binary generator is read from the storage device to based on the indexing signal and generating binary bits based on data obtained by reading from the storage device.  18. The system according to 17, characterized in that the codeword information includes a first signal indicating whether the BVS or MVS indication starts the run, a second signal indicating whether the BVS or MVS indication contains the end of the run, and the code signal output words.  19. The system according to claim 11, characterized in that the unit for arranging binary digits is designed to order words formed with interleaving, for forming a flow of encoded data in the form of streams with interleaving, ordered in accordance with the previous N-th code word in each interleaved word each thread.  20. The system according to claim 11, characterized in that the reordering unit comprises a search decoding device for selecting interleaved words output to the code stream.  21. The system according to claim 20, wherein the reordering comprises a plurality of reordering units of run accounts associated with a plurality of binary arrangement blocks, each of the plurality of binary arrangement blocks being used for generating words with interleaving, and the search decoding device provides a word selection interleaving from a plurality of such words as an output signal for a code stream.  22. The system according to claim 11, characterized in that the codeword information includes a time stamp, and the reordering unit further comprises a logical unit for issuing words with interleaving based on the associated time stamps.  23. The system of claim 22, wherein the reordering unit comprises a plurality of run count reordering units associated with a plurality of binary digit arrangement blocks, the logical unit providing interleaving words based on associated timestamps.  24. The system according to item 23, wherein the words with interleaving are issued according to the earliest time stamp.  25. The system according to claim 11, characterized in that by means of a single block of the queue the issuance of code words to many blocks of the arrangement of binary digits, and many blocks of the arrangement of binary digits form words with alternation for issuing as part of the code stream.  26. The system according to p. 25, characterized in that the single block of the queue includes a single block reordering counts of runs, while the logic circuit ensures the determination of the next word with alternation for issuing as a code stream.  27. The system according to p. 11, characterized in that by means of a single block of the queue, the issuance of code words to a single block arrangement of binary digits.  28. An encoding system comprising an encoding device and intended to be used in a compaction system having a decoding device for decoding information generated by the encoding device, characterized in that the encoding device is configured to generate codeword information in response to the data, a reordering unit connected to an encoding device for generating a stream of encoded data, respectively, of codeword information, wherein the reordering unit comprises a run count reordering unit for putting each codeword at the beginning of the data corresponding to it, and a binary digit arranging unit for receiving code words from the run count reordering unit, for combining variable length codewords into a plurality of words interleaving a fixed length and for outputting a plurality words alternating with a fixed length in the order required by the decoding device.  29. The system of claim 28, wherein the reordering unit comprises a storage device for storing codewords during reordering.  30. The system of claim 28, wherein the encoder comprises a context model block, a probability estimation block associated with the context model block, and a binary sequence generator associated with the probability estimation block.  31. The system of claim 30, wherein the reordering unit of the run count comprises a first storage device for storing codewords, a first indicator and a second indicator for addressing the first storage device as a queue, the first indicator for indicating the first content in as the output signal of the first storage device, and the second indicator is designed to indicate the second content for the next available and unassigned memory in the first memory devices of huge capacity.  32. The system according to p. 31, characterized in that it contains a pointer storage device for storing address information corresponding to the cells in the first storage device currently assigned to store code words for each indexing signal.  33. The system of claim 32, wherein each indexing signal indicates a probability class.  34. The system according to p, characterized in that each indexing signal indicates at least one context.  35. The system of claim 28, wherein the reordering unit includes a codeword memory queue for storing codewords, a head pointer for indicating at least one codeword for output, and a tail pointer for indicating at least a memory cell for adding codewords to the queue of the codeword memory device.  36. The system of claim 35, wherein each content of the codewords in the queue of the codeword memory device includes a confidence indication, wherein the code word is issued from the codeword memory queue when the head pointer determines the address of the code word, and the indication Credibility for a codeword shows its credibility.  37. The system according to p. 28, characterized in that the block arrangement of binary digits contains a logical block layout of binary digits, configured to receive code words from the block reordering and combining code words into words with alternation for multiple streams.  38. The system according to clause 37, wherein the logical unit for arranging binary digits contains many accumulative adders and many registers, each of the many registers associated with one of the many accumulative adders and one of the many streams, each register is designed to store a word with interleaving for the corresponding stream, and each accumulating adder indicates the next cell in the associated register to store the current codeword of the stream, so that each codeword for one of a plurality of streams are added to the contents of the register corresponding to said one of the plurality of streams based on the value in the corresponding accumulator.  39. The system according to p. 38, characterized in that it contains a shifting device connected to a plurality of accumulating adders, designed to shift code words in response to at least one signal from a plurality of accumulating adders, the code words being shifted to add one of multiple registers according to the value in the accumulating adder to combine parts of at least two code words to form each word with alternation.  40. The system according to clause 37, characterized in that it contains a memory reordering device for storing words with alternation in the sequence indicated by the decoding device.  41. The system of claim 40, characterized in that it contains a plurality of pointers corresponding to the plurality of interleaved data streams, each of the plurality of pointers indicating a cell of a reordering memory for the next word interleaved for each of the plurality of streams.  42. The system according to p. 28, characterized in that it contains many blocks reordering run counts, each of which is associated with one of the streams of encoded data, many blocks of the arrangement of binary digits for the formation of words with alternation for each stream of encoded data and a decoding device for selecting words interleaved from a plurality of binary arrangement blocks as an encoded output signal.  43. The system according to p. 28, characterized in that it contains many blocks reordering counts of runs, each of which is associated with one of the streams of encoded data and is designed to generate many code words and time stamps associated with each of the many code words, many blocks layout of binary digits for the formation of words with alternation for each stream of encoded data and a logical unit for selecting each of the words with alternation according to the time stamps of the code words in each of the words with alternation .  44. The system according to item 43, wherein the logical unit is configured to select a word with alternation containing a code word with the oldest time stamp.  45. The system according to p. 28, characterized in that the block layout of the binary digits contains many blocks layout of the binary digits connected to receive code words from one of the many streams, and a logical block for selecting words with alternation for issuing from each of the many blocks of layout binary bits according to the next stream.  46. The system of claim 28, wherein the reordering unit comprises a finite memory.  47. A coding system for processing data, characterized in that it comprises an indexing signal generator for generating indexing signals according to the data signals, and a state table unit for providing a probability estimate based on the indexing signals, the state table including a first plurality of states and a second a set of states, each of which corresponds to a code, while transitions between different codes corresponding to the first set of states are faster when the transition between states in the first set of states than the transitions between different codes corresponding to the second set of states in the transition in the second set of states.  48. The system according to clause 47, wherein the first set of states is used only for a predetermined number of indexing signals.  49. The system of claim 47, wherein the first plurality of states is used only for a predetermined number of indexing signals that initially index the state table. 50. The system according to clause 47, wherein each of the first set of states is associated with a code R ₂ .  51. The system of claim 48, wherein the first plurality of states includes at least one transition to the second plurality of states, so that the state table transitions to the second plurality of states from the first plurality of states after a predetermined number of indexing signals.  52. The system of claim 47, wherein each of the first plurality of states is associated with different codes.  53. The system according to clause 47, wherein the state table goes from one of the first set of states to one of the second set of states in response to the least probable symbol.  54. The system of claim 47, wherein the state machine provides a state change by incrementing in response to the most probable symbol.  55. A coding system for processing data, characterized in that it comprises an indexing signal generator for generating indexing signals according to the data signals, and a state table unit for providing a probability estimate based on the indexing signals, the state table including a plurality of states, each of which corresponds to the code, and each code in the state table is repeated a predetermined number of times, and the transition between the states of the state table occurs according to the variable acceleration element, so that the first transition speed between states during the first time period is different from the second transition speed during the second time period.  56. The system of claim 55, wherein updating the state table data includes modifying the state of the probability estimation module (MOW) by positive or negative increment of the acceleration element.  57. The system of claim 56, wherein adaptive acceleration does not occur when the acceleration element is characterized by a predetermined number, which corresponds to the absence of adaptive acceleration.  58. The system of claim 56, wherein the value of the acceleration element is updated based on a series of consecutive codewords.  59. The system of claim 58, wherein the sequential codewords include sequential codewords in context.  60. The system of claim 58, wherein the sequential codewords include sequential codewords in a probability class.  61. The system of claim 56, wherein the value of the acceleration element is updated based on a series of alternating code words. 62. A statistical decoding device for decoding a data stream from a plurality of codewords, comprising a plurality of binary-sequence generators for receiving a data stream, characterized in that it comprises a state table unit associated with a plurality of binary-sequence generators to provide a probability estimate for sets of binary sequence generators designed to generate a decoded result for each code th word in the data stream respectively probability estimation using code R _n (k) for a plurality n of values, wherein the state table includes a first set of states and a second set of states, and transitions between different codes in the first plurality of states are faster, when a transition occurs in the first set of states than transitions between codes when the transition occurs in the second set of states. 63. The device according to p. 62, characterized in that each of the first set of states contains the code R ₂ (k).  64. The device according to item 62, wherein the first set of states is intended for use only during initialization.  65. A statistical decoding device for decoding a data stream from a plurality of codewords, comprising a plurality of binary sequence generators for receiving a data stream, characterized in that it contains a state table unit for providing probability estimates with an indexing signal, the table includes there are many states, each of which corresponds to a code, and each code in the state table is repeated a predetermined number of times, with In this case, the transition between the states of the state table occurs according to the variable acceleration element, and the first transition speed between the states during the first time period differs from the second transition speed during the second time period.  66. The system of claim 62, wherein each code in the state table is repeated a constant number of times.  67. The system of claim 66, wherein updating the state table includes modifying the state of a probability estimation module (MOV) by means of an acceleration element.  68. The system of claim 67, wherein the acceleration element is characterized by a predetermined number, which corresponds to the absence of adaptive acceleration.  69. The system of claim 67, wherein the value of the acceleration element is updated based on a certain number of consecutive codewords.  70. The system of claim 67, wherein the value of the acceleration element is updated based on a certain number of alternating code words.  71. A decoding device for decoding a plurality of words interleaved, comprising a probability estimating unit, characterized in that it comprises a shifting unit for receiving a data stream and outputting properly aligned encoded data, a run length decoding unit connected to the shifting unit, for receiving properly aligned encoded data as codewords for determining the type of codeword, wherein the probability estimation unit is connected to the run length decoding unit, providing data processing of run length and indication of the appearance of the least probable symbol in response to each codeword, moreover, the shifting unit contains a variable-length shift unit for shifting codewords from the data stream and a plurality of registers connected to receive codewords from the stream under the action of the shift unit, to ensure output aligned coded data as a sequence of code words.  72. The device according to p, characterized in that part of the registers is connected with the possibility of receiving data from another set of registers or from a data stream.  73. The device according to p. 71, characterized in that the variable-length shift unit includes a multi-register cyclic shift device designed to shift data from a stream into multiple registers.  74. The device according to p, characterized in that the shifting unit contains a data processing unit in the order of arrival, having many registers, each of which is designed to receive data as an input signal from interleaved encoded data, and at least one of the many registers connected to receive codewords from another of the plurality of triggers.  75. The device according to p, characterized in that the shifting unit contains a first plurality of registers for receiving data of codewords, wherein each of the plurality of registers is associated with a respective one of the plurality of streams, a multiplexer connected to receive data of codewords from each of the plurality of registers as input signals and issuing code words from one of the many streams at the same time, a multi-register cyclic shift device connected to the output of the multiplexer for shifting data code words from the multip a lexor for outputting them in the form of aligned encoded data, a logic unit connected to a multi-register cyclic shift device for indicating the number of bits for shifting the code word and a data processing unit in the order of arrival having a plurality of registers connected to receive code words from said multiplexer, moreover, the data processing unit in the order of receipt includes many registers, each of which is designed to receive data as an input signal from zhaemyh coded data, and at least one of the plurality of registers connected to receive codewords from another of said plurality of registers.  76. A decoding system for decoding data, comprising decoding devices and a context model unit for providing contexts, characterized in that it comprises a data processing unit in the order of receipt connected for receiving data, a storage device connected to the context model unit for storing state information, and the storage device provides state information corresponding to each context provided by the context model block, when this many decoding devices are connected to receive encoded data from the data processing unit in the order received and from the storage device for decoding code words issued by the data processing unit in the order received using state information from the storage device, and many decoding devices generate run counts for a plurality codes.  77. The system of claim 76, wherein the data processing unit, in the order of receipt, is designed to provide encoded data to a plurality of decoding devices, regardless of context and probability class.  78. The system of claim 76, wherein the decoding device comprises a run count memory device for storing run counts, wherein access to the run count memory is in accordance with a probability class.  79. The system of claim 76, wherein the data processing unit in order of receipt provides data for two decoding devices.  80. The system according to p, characterized in that the data processing in the order of receipt contains many outputs, one for each decoding device.  81. The system of claim 80, wherein the data processing unit, in the order of receipt, comprises a pair of multiplexers and a control logic unit for selecting a pair of multiplexers for supplying a codeword to each decoding device.  82. The system of claim 81, wherein the choice of a pair of multiplexers is provided by a control logic unit according to requests received from one of the plurality of decoding devices.  83. An encoding system for encoding input data, comprising an encoding unit connected to receive input data, characterized in that the encoding unit is configured to generate encoded data in the form of multiple streams, the encoded data being assigned to one of the multiple streams based on a number of criteria, with this system contains a storage device of fixed capacity connected to the encoding unit, designed to store multiple streams of encoded data, when than coded data of lesser significance are discarded in case of overflow of a fixed capacity storage device.  84. The system of claim 83, wherein the storage device comprises a plurality of memory plots, and the encoded data stored in each of the plurality of memory plots includes encoded data of a certain significance level.  85. The system of claim 84, wherein the stored encoded data of one significance level is provided in at least one memory location of a storage device storing encoded data of another significance level.  86. The system of Claim 85, wherein the encoded data of said one significance level is provided to overwrite the encoded data of said other significance level in said at least one memory location of the storage device.  87. A method of initializing multiple contexts in the system when encoding data, based on the formation of contexts and assessing the probability of contexts, characterized in that each of the multiple contexts is selected based on the counter value, and the state of the probability estimation module (MOB) of the current context is obtained by performing indication selection operations memory cells for each context showing the state of the MOB, determining the correctness of the selected memory cell for the current operation by comparing the current about the context number with the counter value, so that the data is determined to be reliable if the counter value indicates that the cell has already been initialized, use the initial MOB state for the context and discard the current MOB state for the context if the data of the selected memory cell is invalid, and use the current MOB state if the mentioned data is reliable.  88. The method according to p, characterized in that it additionally record a new state of the MOB, if the state of the MOB has changed.  89. A decoding device for decoding input data containing a context model block for generating a context element and binary sequence generators, characterized in that it contains a storage device connected to the context model block for generating probability state data based on the context element, a logical block, connected to a storage device, configured to generate a probability class according to a state of probability, a decoding unit, sub unified to a logic block, for generating an enable signal according to the probability class, while a plurality of binary sequence generators are connected to a decoding unit and, in addition, are connected to receive encoded data, each of their multiple binary sequence generators corresponds to at least one specific code, moreover, the decoding unit is configured to start one of the many generators of the sequences of binary digits in accordance dance with the class probability for decoding the encoded data by said one of the plurality of bits sequences generators.  90. The device according to p. 89, characterized in that at least one of the many generators of the sequences of binary digits is configured to decode data using the R-code and at least one of the many generators of sequences of binary digits is configured to decode the data using code other than the R code.  91. The device according to p. 89, characterized in that the generators of the sequences of binary digits for short run lengths are used as decoders of the R-code.  92. The device according to p. 89, characterized in that the generators of the sequences of binary digits for long runs contain a block of short runs and a block of long runs, moreover, a block of short runs is intended to manipulate the codes of the first predetermined length, and a block of long runs to manipulate any the remaining bits and to determine which of the remaining bits, if any, should be output.  93. A method of decoding input data, based on the formation of context elements and estimation of the probability state, characterized in that the memory device is accessed using the context element to obtain the probability state, a probability class corresponding to the probability state is generated, one of the plurality of binary sequence generators is launched , each of which corresponds to at least one specific code, resulting in only one of the plural the set bits sequence generators decodes encoded data.  94. An encoding device for encoding input data containing a context model block for generating a context element and binary sequence generators, characterized in that it comprises a storage device connected to the context model block for generating probability state data based on the context element, a logical block, connected to a storage device, configured to generate a probability class according to a probability state, an encoding unit is connected which is connected to a logic block for generating a trigger signal according to the probability class, while many generators of binary sequences are connected to the encoding block and, in addition, are connected to receive input data, each of the many generators of binary sequences corresponds to at least one specific code, moreover, the encoding unit is configured to start one of the many generators of the sequences of binary digits in accordance with the class digits for providing input data encoding by one of a plurality of binary sequence generators.  95. The device according to clause 94, wherein at least one of the plurality of binary sequence generators is configured to encode data using an R code, and at least one of the plurality of binary sequence generators is configured to encode data using code other than the R code.  96. The device according to p. 94, characterized in that the generators of the sequences of binary digits for short runs are used as encoding the device R-code.  97. The device according to p. 94, characterized in that the generators of the sequences of binary digits for long runs contain a block of short runs and a block of long runs, and the block of short runs is designed to manipulate the codes of the first predetermined length, and the block of long runs is designed to manipulate any the remaining binary bits and determining which of the remaining binary bits, if any, should be deduced.  98. A method of encoding input data, based on the formation of context elements and the estimation of the probability state, characterized in that they access the storage device using the context element to obtain the probability state, generate a probability class according to the probability state, start one of the set of binary sequence generators each of which corresponds to at least one specific code, resulting in the said one of the many gene Ator sequence of bits encodes the input data.  99. A method for decoding encoded data containing a plurality of codewords, based on the use of binary sequence generators, characterized in that the count value is loaded into the counter associated with each run counter, the count value corresponding to the capacity of the codeword memory used in the encoding when starting a new run, and the said count value is loaded when selecting a new code word for each run counter, negative a substantial increment of the count value each time when sampling any codeword, and clear the state of the binary sequence generator associated with the aforementioned new codeword when the counter value is reduced to zero.  100. The method according to p. 99, characterized in that each run counter corresponds to the state of the MOU.  101. The method according to claim 99, wherein each run counter corresponds to a context element.  102. A method for decoding encoded data containing a plurality of code words, based on the use of binary sequence generators, characterized in that the counter value is incremented each time a code word is requested, the counter value comprising an indication of the current time, the counter values are stored as an indication of the stored time when starting the first codeword, compare the indication of the stored time plus the memory capacity of the coding devices with an indication of the current time, clear the state of the binary sequence generator for the first codeword and request a second codeword when the indication of the current time is greater than the indication of the stored time plus the memory capacity of the encoder.  103. The method according to p. 102, characterized in that the indication of the stored time contains a time stamp.  104. The method according to p. 102, characterized in that it further comprises the reuse of the indication of the stored time for the subsequent code word.  105. A method for decoding encoded data containing a plurality of code words, based on the use of binary sequence generators, characterized in that the index corresponding to the code word is stored, the index being stored in the queue when the code word is requested, the contents of the index in the queue are marked as invalid, stored the codeword in the content and mark the content as valid at the end of the codeword, output the data to be decoded from the queue, the codeword output t for decoding, if the contents of the queue are valid, and the data is output from the contents of the queue and the data is indicated to the decoding device as invalid if the contents of the queue are marked as invalid when outputting data from the queue, and the state information of the binary sequence generator is cleared by the decoding device in response to reception data from the queue marked as invalid.  106. A decoding device for decoding encoded data, comprising a context modeling unit for creating contexts, comprising a plurality of integrated circuits, characterized in that it comprises a storage device connected to a context modeling unit for storing state information, the storage device being adapted to provide state information in response for each context of the context modeling unit, a plurality of decoding units connected to the storage device and started for decoding codewords using state information from a storage device, the plurality of decoding blocks providing decoding of codewords using a plurality of R-codes, including at least one run of not the maximum length of the most probable characters, followed by the least probable character .  107. The device according to p. 106, characterized in that the scores of the runs are not the maximum length have a unique decoded prefix.  108. A system for decoding a code stream having a plurality of codewords containing a context modeling unit for generating contexts containing a plurality of integrated circuits, characterized in that it comprises a storage device connected to the context modeling unit for storing state information and outputting state information in response to each context of the context modeling unit, and a plurality of decoding devices connected to the storage device for decoding codewords using retrieving status information from the storage device.  109. The system of claim 108, wherein the context modeling unit comprises at least one context model providing contexts with one of a plurality of integrated circuits, and at least one context model providing contexts with a second of a plurality of integrated circuits.  110. The system of claim 109, wherein said at least one context model on said one of a plurality of integrated circuits comprises a zero order context model.  111. The system of claim 108, wherein the contexts of the plurality of integrated circuits are intended to be output directly to the storage device.  112. The system of claim 108, wherein the formation of the first part of the first context is provided by one integrated circuit, and the formation of the second part of the first context is provided by the second integrated circuit.  113. The system according to 17, characterized in that the binary sequence generator is configured to update the state, and the binary sequence generator is reused before writing the updated status to the memory.  114. The system according to p. 113, characterized in that the binary sequence generator is configured to be reused at the stage of modification of the read-modify-write cycle.  115. The system according to 17, characterized in that the binary sequence generator is configured to generate a run count of a minimum length when reused before writing the updated state to the memory.  116. The system according to 17, characterized in that the binary sequence generator is intended to be encoded using R codes, defined so that after each run length at least one non-encoded binary bit follows, so that two codewords of the same run lengths are never decoded side by side.  117. A system for decoding a code stream having a plurality of code words, comprising a context modeling unit for creating contexts, characterized in that it comprises a storage device connected to the context modeling unit for storing state information and outputting state information in response to each context of the context modeling unit , and a plurality of decoding devices connected to the storage device for decoding codewords using the state information from the storage second device, wherein at least one of the plurality of decoders includes a decoder permissible delay.  118. The system of claim 115, wherein at least one of the plurality of decoding devices is configured to shift a variable length based on decoded data generated after the delay.  119. The system of claim 117, wherein each of the plurality of decoding devices uses variable-length data as an input signal.  120. The system according to p, characterized in that many decoding devices are designed for parallel decoding of input data of variable length.  121. The system of claim 117, wherein the output signal of the plurality of decoding devices is divided into interleaved words having a fixed length.

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