DE19536401A1 - Method and device for encoding and decoding data - Google Patents

Abstract

The invention provides an encoder for use in a data compression system having a decoder for decoding information generated by the encodor. The encoder 600 includes a reorder unit 606 that generates 8 coded data stream 608 in response to the codeword information 604 from the coder 602. The reorder unit comprises a run count reorder unit 801 for arranging codewords into a decoding order and a bit pack unit 802 to combine variable length codeword 803 into fixed length interleaved words 805 and to output them in an order required by the decoder. Reorder unit 801 moves codewords from the end of runs as created by the encoder to the beginning of runs as needed by the decoder. The decoder is delay tolerant. <IMAGE>

Description

The invention relates to methods and a device for coding Ren and decoding of data and relates in particular to Ge offers data compression and decompression systems; about that the invention also relates to a method and a device for parallel coding and decoding of data in compresses sions / decompression systems.

Nowadays, data compression is particularly widespread used to store and transfer large amounts of data. At the Various data compression techniques are state of the art known, which can be divided into two broad categories NEN, namely a lossy and a lossless Codie Ren. Lossy coding includes coding, which It boils down to the loss of information so it doesn't ne guarantee for a perfect reconstruction of the original Chen or original data there. With lossless compression all information is received again and the data is stored in one Compressed in a way that allows a perfect reconstruction.

With lossless compression, symbols entered in are off given code words implemented. If the compression is successful the code words are represented in fewer bits than that Number of symbols entered. Contain lossless coding methods dictionary methods of coding (e.g. Lempel-Ziv)  Run length coding, enumerative coding and one Entropy coding.

Entropy coding consists of a lossless coding process which tries to get data close to the Entropy limit with the help of known or estimated symbol probabilities ways to compress. Entropy codes contain Huffman codes, arithmetic codes and binary entropy codes. Binary Entropy encoders are lossless encoders that are only based on binary (yes / no) decisions act that are often considered true most likely symbol (MPS) and the least likely Symbol (LPS) are expressed. Example of binary entropy co These include IBM’s Q coder and a coder that is the B-coder is designated. (For more information on that B-coder, see US Patent No. 5,272,478 entitled "Method and Entropy Coding Device "(J.D. Allen) filed on December 21, 1993 by the applicant of the present Invention. See also M.J. Gormisch and J.D. Allen, "Fini State Machine Binary Entropy Coding ", abstract in Proc. Data Compression Conference, March 30, 1993, Snowbird, UT, p. 449.) The B coder is a binary entropy coder, which has an end automaton used for compression.

Fig. 33 shows a block diagram of a known compression and decompression system with a binary entropy encoder. For coding, data is entered into a text model (CM) 101 , which translates the entered data into a set or sequence of binary decisions, and creates a context bin for each decision. Both the sequence of binary decisions and their associated context subjects are delivered by the context model 101 to the probability assessment or estimation (PE) module 102 . The PE module 102 receives each text subject and generates a probability score for each binary decision. The actual probability rating is usually represented by a class called the P class. Each P class is used for a probability range. The PE module 102 also determines whether or not the binary decision (the result) is in the more likely state (ie, whether the decision corresponds to the MPS). A bitstream generator (BG) module 103 receives the probability rating (ie, the P class) and the determination of whether the binary decision is likely or not as input signals. Accordingly, the BG module 103 generates a compressed data stream that outputs zero or more bits to represent the original input data.

For coding, the context model 104 creates a context subject on the PE module 105 , which creates the probability class (P class) on the BG module 107 based on the context subject. The BG module 106 is provided to accommodate the probability class. According to the probability class and the compressed data, the BG module 106 returns to a bit which represents whether the binary decision (ie the event) is in the most likely state. The PE module 105 receives the bit, updates the probability score based on the received bit, and returns the result to the context model 104 . The context model 104 receives the bit to be returned and uses it to generate the original data and to update the context bin for the next binary decision.

A difficulty with decoders that use binary entropy codes use, like IBM's Q-Coder and B-Coder, is that they are slow, even if they are executed in hardware. This mode of operation requires a single large slow return coupling loop. To redraw the decoding process, ver the context model applies previously decoded data to a con to generate text. The probability assessment module be uses the context to create a probability class The bitstream generator uses the probability class and the compressed data to determine if that  next bit the likely or improbable result is. The probability assessment module uses the true apparent / improbable result to a result bit generate (and the probability rating for the con update text). The result bit is derived from the context mo dell used to update the development of previous data lize. All of these steps are for decoding one bits required. Since the context model is based on the result bit must wait to update its development before it can create the next context, the decoding of the wait next bits. It should be avoided feeling too that the coupling loop before decoding the next most bits is completed. In other words, it should if possible, more than one bit or one code word for a specific one decoded to increase the speed, with which compressed data is decoded.

Another difficulty with decoders with binary entro Pie codes consist of data of variable length must be processed. In most cases they have to be coded code words of variable lengths. On the other hand, others code Systems symbols of variable length (uncoded data). At a Processing the data of variable length must include the data one bit level shifted to the correct next one To create data for the decoding or coding operation. These Bit level manipulations on the data stream can be costly some and / or slow hardware and / or software. Furthermore, in conventional systems this shifting in time-critical feedback loops are made, wel limit the performance of the decoder. It would so be advantageous to the bit level manipulation of the data remove current from time-critical feedback loops, so that parallelism could be applied to the Ge increase speed.

The invention creates a lossless compression and de  compression system. The invention also creates a real time co dierer and a real-time decoder, which data in parallel encode or decode. The encoder and decoder of the Invention create a balanced, parallel entropy sy stem, which is both a real time coding and a real time decoding in an inexpensive, very fast hardware carries out.

According to the invention, this is the case with methods and devices for encoding data according to claim 1, 8, 28, 49, 55, 88, 94 and reached 98. This is also the case with procedures and equipment gene for decoding data according to claim 62, 65, 71, 76, 89, 93, 97, 99, 101, 105, 106, 108 and 117 reached. Beneficial Further training is the subject of one of the previous ones Claims directly or indirectly related claims.

Thus, methods and devices for decompressing and Compress data created. The invention creates one Encoder for use in a compression system, the generate a decoder for coding by means of the encoder ter has information. The encoder of the invention includes one Encoder for generating code word information corresponding to data on. The encoder also includes a reordering unit that an encoded data stream according to the codeword informa tion generated by the encoder. The reordering unit has one Pass count shuffling unit to code words in a deco the order and a bit pack unit to Co words of variable length to nested words of fixed length to link and around the nested words of fixed length in in an order required by the decoder.

The invention is based on preferred embodiments tion forms with reference to the accompanying drawings in described. Show it:  

FIG. 1A according to the dung OF INVENTION a block diagram of an encoding system;

1B is a block diagram of an embodiment of a Codiersy stems according to the invention.

Fig. 1C is a block diagram of an embodiment of the decoding system of the invention, which context subjects processes in parallel;

Fig. 1D is a block diagram of an embodiment of the Decodiersy stems of the invention which processes probability classes parallel;

Figure a non-interleaved code stream of the invention. 2;

Fig. 3 shows an embodiment of the interleaved code stream, which is for example derived from a data set;

Fig. 4 shows an example of a probability evaluation table and a bit stream generator for the R-coder of the invention;

Fig. 5 is a block diagram of an embodiment of an encoder of the invention;

Fig. 6 is a block diagram of an embodiment of a bit generator of the invention;

Fig. 7 is a block diagram of an embodiment of a Umord-drying unit of the invention;

Fig. 8 is a block diagram of an embodiment of the run count reorder unit of the invention;

Fig. 9 is a block diagram of another embodiment of a flow counter reordering unit of the invention;

FIG. 10 is a block diagram of an embodiment of a bit packing unit of the invention;

FIG. 11 is a block diagram of an embodiment of a packing logic of the invention;

Fig. 12 is a block diagram of an encoding bit generator of the invention;

FIG. 13A is a block diagram of an embodiment of the Decodiersy stems of the invention;

FIG. 13B is a block diagram of a decoder of the invention;

FIG. 13C is a block diagram of one embodiment of the FIFO structural structure of the invention;

FIG. 14A is an embodiment of a decoding pipeline ESTABLISHING THE OF INVENTION;

FIG. 14B is an embodiment of a decoder of the invention;

FIG. 15A is a block diagram of an embodiment of a shift unit of the invention;

FIG. 15B is a block diagram of another embodiment of a shift unit of the invention;

FIG. 16 is a block diagram of a system with an external con text model;

Figure 17 is a block diagram of another system with an external context model.

FIG. 18 is a block diagram of an embodiment of a Decodie RERS of the invention;

FIG. 19 is a block diagram of an embodiment of a Decodie RERS with separate bit generators;

FIG. 20 is a block diagram of an embodiment of a Bitgenera tors of the invention;

Figure 21 is a block diagram of one embodiment of a long pass unit of the invention;

FIG. 22 is a block diagram of an embodiment of a short processing unit of the invention;

FIG. 23 is a block diagram of an embodiment of a Initiali sierungs- and control logic of the invention;

FIG. 24 is a block diagram of one embodiment of shuffling data using a "Snooper"encoder;

FIG. 25 is a block diagram of another embodiment of a shuffling unit;

Fig. 26 is a block diagram of another embodiment of a rearrangement with the aid of a mixed queue (queue merged);

Fig. 27 is a block diagram of a wide bandwidth system using the invention;

FIG. 28 is a block diagram of a bandwidth adaptation system that uses the invention;

FIG. 29 is a block diagram of a real-time video system according to the invention;

Fig. 30 shows an embodiment of a memory for coded data of the invention;

Figure 31 is a timing diagram of the decoding process of the invention;

Fig. 32 is a graph of Codiererwirkungsgrades compared to an MPS probability of the invention, and

Figure 33 is a block diagram of a conventional binary entropy encoder and decoder.

Now a method and a device for parallel Encoding and decoding of data described. In the following Many specific details are given in the description, such as a specific number of bits, a number of encoders, specific probabilities, data types, etc. to have a thorough understanding of the preferred embodiment to create men of the invention. For the specialist is self-ver It is understood that the present invention speci fishing details can be carried out in practice. As well are not known circuits in block diagram form in detail NEN illustrated to make the understanding of the invention unnecessary to complicate.

Some parts of the detailed description that follow are in the form of algorithms and symbolic representations of Operations on data bits are shown in computer memory. These algorithmic descriptions and representations are the Means used by data processing professionals applied to the content of their work other professionals to be transmitted as effectively as possible. An algorithm is here and generally as a self - contradicting sequence of Consider steps that lead to a desired result. The steps are those that involve physical processing of physical quantities. Usually, though not necessarily, these sizes take the form of electrical ones  or magnetic signals that are stored, transmitted, ver ties, compared or can be processed in any other way nen. It has always been, principally for reasons of commonality Men application proved to be favorable on these signals as bits To refer to values, elements, symbols, characters, terms, numbers or similar sen.

However, it should be borne in mind that all of these and similar Terms are to be assigned to the corresponding physical quantities and only convenient terms are given in these sizes be applied. If it's not done specifically or otherwise is apparent from the following discussions all in the invention explanations using terms such as "Process" or "Calculate" or "Calculate" or "Determine" or "display" or the like, on the function and processes of a compu systems or a similar electronic calculation direction, which data, which as physical, (electro niche) sizes in the computer system registers and memories are shown, edited and converted into other data, which similarly as physical quantities in the computer system memories or registers or other such information memory transmission or display devices are.

The invention also relates to a device for performing of operations. This facility can be specially designed for the gefor other purposes, or it can be a universal Have computer that selectively by a ge in the computer saved program is activated or reconfigured. The The algorithms and displays shown here are not speci fish on a special computer or other device based. Various universal computers can be used with programs are used in accordance with the teachings presented here, or it may prove beneficial to have one more specialized to run the various Ver carry out driving steps. The required structure of a  Many of these devices result from the following Be spelling. In addition, the invention is not related to any described in a special programming language. Rather you can a variety of programming languages are used to control the Teach the invention as described below respectively.

Parallel entropy coding

The invention provides a parallel entropy coding system. The System has an encoder and a decoder. In a In one embodiment, the encoder performs encoding on data Real time through. Similarly, in an execution form the decoder of the invention a decoding of data in Real time through. The real-time encoder and real-time decoding Together they form a balanced coding system.

The invention creates a system which encodes losslessly Data decoded in parallel. The data is decoded in parallel with the help of several decoding resources. Each of the several Decoding resources is data (e.g. code words) from the de assigned coding data stream. The allocation of the data stream occurs on the fly, using the decoding resources Decode data at the same time, thereby making the data stream paral lel to decode. To get the data mapping in a way possible, which an effective use of the decoding Res enables the data stream to be ordered. this will referred to as parallel processing of the data stream. The order of data allows each decoding resource to have any or decoded all encoded data without feedback to wait from the context model.

Figure 1A shows a decoding system of the invention without the conventional slow feedback loop. An input buffer 204 receives encoded data (ie, code words) and a feedback signal from a decoder 205 and provides encoded data in a predetermined order (e.g. contextual order) to the decoder 205 of the invention, which encodes the Data decoded. Decoder 205 includes multiple decoders (e.g., 205 A, 205 B, 205 C, etc.).

In one embodiment, each of the decoders 205 A, 205 B, 205 C, etc. provides data for a group of contexts. Each of the decoders in decoder 205 provides encoded data for each context bin in its group of contexts from an input buffer 204 . With the help of this data, each decoder 205 A, 205 B, 205 C etc. generates the decoded data for each group of context subjects. The context model is not required to assign coded data to a specific group of context subjects.

The decoded data is output from decoder 205 to a memory 207 for decoded data (e.g. 207 A, 207 B, 207 C, etc.). Here, the memory 207 can store intermediate data that is neither encoded nor uncoded data, such as run counts. In this case, memory 207 stores data in a compact but not entropy-encoded form.

An independently operating context model 206 is provided to store the previously decoded data from memory 207 (ie 207 A, 207 B, 207 C, etc.) in accordance with a feedback signal that it outputs to memory 207 . As a result, there are two independent feedback loops, one between decoder 205 and buffer 204 and a second between context model 206 and memory 207 . Since the large feedback loop is eliminated, the decoders in encoder 205 (e.g., 205 A, 205 B, 205 C, etc.) are able to decode their associated code words as soon as they are received by buffer 205 become.

The context model creates the memory part of the coding system and divides a data record (e.g. an image) into different channels categories (e.g. context subjects) based on memory. In  According to the invention, the context subjects are ordered independently Considered records. In one embodiment, each group has of context subjects their own probability assessment mo dell and each context subject has its own state (where Probability assessment models are shared). Therefore, each context subject could have a different probability valuation model and / or another bitstream generator Zen. So the data is ordered or processed in parallel, and data from the data stream are used for the individual encoders Coding assigned.

Add parallelism to the classic entropy coding model

In order to arrange the data stream in parallel, the data can be divided according to a context, a probability, a tiling, a code word sequence (based on code words) etc. Rearranging the encoded data stream, regardless of parallelism, is a method used to parallel data or probability in another point. A parallel encoder portion of an encoding system of the invention that has been supplied with data that has been differentiated by a context model (CM) is shown in FIG. 1B.

In FIG. 1B, the context-dependent parallel coding part has a context model (CM) 214 , probability assessment modules (PEMs) 215 to 217 and bitstream generators (BGs) 218 to 220 . The context model 214 is provided to receive coded input data and is also connected to the PE modules 215 to 217 , which in turn are connected to bitstream generators 218 to 220 , which emit code streams 1 , 2 and 3 , respectively. Each PEM and BG pair has a coder. Therefore, the parallel encoder is shown with three encoders. Although only three parallel encoders are shown, any number of encoders can be used.

The context model 214 divides a data stream into different contexts in the same way as a conventional context model and delivers the multiple streams to the parallel hardware coding resources. Individual contexts or groups of contexts are directed to separate probability evaluators (PEMs) 215 to 217 and bit generators (BGs) 218 to 220 , each of which emits an encoded stream.

Fig. 1C is a block diagram of an embodiment of the decoding part of the decoding system of the invention. In Fig. 1C is a context-dependent parallel decoder BGs 221 to 223, PEMs 224-226 and presented to a CM 227th Code streams 1 through 3 are connected to BGs 221 through 223 , which are also connected to PEMs 224 through 226 . The PEMs 224 to 226 are also connected to the CM 227 , which delivers the reconstructed input data. The input comes from several code streams, which are shown as code streams 1 to 3 . A code stream is assigned to each PEM and BG. Each of the bit stream generators (BG) 221 through 223 returns a bit that represents whether the binary decision is in a more likely state that PEMs 224 through 226 use to return decoded bits (e.g., the binary decision). Each of the PEMs 224 to 226 is assigned to one of the BGs 221 to 223 , which indicates which code is to be used to generate a data stream from the input code stream. The CM 227 generates a decoded data stream to select the decoded bits from the data stream generators in the correct order, thereby recreating the original data. As a result, the CM 227 receives the decompressed data bit from the corresponding PEM and BG, which actually reorder the data in the original order. The control for this execution flows in the reverse direction of the data stream. The BG and PEM can decode data before the CM 227 needs it, one or more bits in advance. On the other hand, the CM 227 may request (but not receive) a bit from a BG and a PEM, and then request one or more bits from other BGs and PEMs before using the initially requested bit.

The configuration shown in Fig. 1C is designed accordingly to closely couple the PEM and the BG. The IBM Q encoder is a good example of an encoder with a tightly coupled PEM and BG. Local feedback loops between these two components are not a fundamental limitation in system execution. In a different design, the PEM could differentiate the data and deliver it to parallel BG units. As a result, it would only be a CM and PEM, and the BG will be divided. Adaptive Huffmann coding and finite state machine coding could be used in this way.

A similar decoding system that uses the PEM to differentiate the data and send it to parallel BGs is shown in Figure 1D. In this case, probability classes are treated in parallel and each bitstream generator is assigned to a specific probability class and it is aware of the result. In Fig. 1D, the encoded data streams 1 through 3 are coupled to one of a plurality of bit stream generators (e.g., BG 232 , 233 , 234 , etc.) which are connected to receive them. Each of the bitstream generators is connected to the PEM 235 , which in turn is connected to the CM 236 . In this configuration, each of the bitstream generators decodes encoded data and the decoding results are selected by the PEM 235 (rather than the CM 236 ). Each of the bitstream generators receives encoded data from a source associated with a probability class (ie, where the encoded data may be from any contextual subject). The PEM 235 selects the bitstream generators using a probability class. The probability class is prescribed by the context subject provided by CM 236 . In this way, decoded data are generated by parallel processing of probability classes.

There are numerous versions of the parallel Co diersystemen of the invention. In one embodiment, the  encoded data streams that correspond to the multiple context subjects be nested in a stream, which by the An requirements of the various encoders. In a Embodiment of the invention, the encoded data is so ge orders that each encoder is constantly supplied with data whether probably the coded data supplied to the decoder in one stream will. The present invention works with all data types, including image data.

With the help of small simple coders that are inexpensive in inte ized circuits can be divided, coded Da can be quickly decoded in parallel. In one embodiment are the encoders in hardware using field programmable Ga Te array (FPGA) chips or with the help of an application-specific Integrated circuit (ASIC) chips executed. The Com combination of parallelism and simple bitstream generators enables decoding of encoded data with speed ten over that of conventional decoders, where the compression efficiency of conventional decoding systems is retained or exceeded.

Channel ordering of multiple data streams

There are many execution results and problems that affect system execution. Some of these are mentioned below. However, the embodiments shown in Figures 1B and 1C (and 1D) use the multi-code streams. Systems with parallel channels that could be adapted to this embodiment are conceivable: multiple telephone lines, multiple heads from a disk unit, etc. In some applications only one channel is available or suitable. Instead, if multiple channels are requested, bandwidth usage may be poor due to the particular nature of the individual code streams.

In one embodiment, the code streams are concentrated and are delivered contiguously to the decoder. A distribution header contains pointers to the initial bit location of each stream. Fig. 2 shows an embodiment of the arrangement of this data. In Fig. 2, three pointers 301 to 303 indicate the starting point in the concentrated code of code streams 1, 2 and 3 respectively. The complete, compressed data file is available in a buffer on the decoder. If necessary, the code words are retrieved from the right place using the right pointer. The pointer is then updated to the next code word in this code stream.

This method requires an entire coded frame that in the decoder and for practical purposes in the encoder too save is. If a real time system or less disturbed ter (bursty) data flow is required, then two frames menpuffer for accumulation (banking) both on the encoder and can also be used on the decoder.

Data order regarding code word order

A decoder decodes code words in a predetermined de terminological order. With parallel coding this is Order of the requirements for the code stream deterministic. Consequently, it suffices if the code words from parallel code streams nested in the correct order on the encoder that, a single code stream. The code words are then sent to the Decoders in the same order on a just-in-time base sis. A model of the decoder determines the on the decoder Code word order and packs the code words into a single one Electricity. This model can be a current decoder.

A difficulty in passing the data to the parallel ones Decoding elements result when data have variable lengths. Taking out a stream of variable length code words requires a bit shifter to align the code words Bit shifters are often expensive and / or slow when they are executed in hardware. The control of the bit shift unit depends on the size of the special code word. These  Controlling a feedback loop prevents a ver push variable lengths is done quickly. The effect ease of supplying a single stream to several decoders, can not be realized if the process, the current is not to pack done in a single bit shifter that is not fast enough to accommodate the multiple decoders supply.

With the solution offered in the invention, this is Problem of ver the encoded data on the parallel encoder divide from the alignment of the variable length code words for a decoding separated. The code words in each independent Data streams are packed in words of fixed length, so-called ver nested words. At the decoder end of the channel, these can interleaved words onto the parallel decoder units Help of fast working, hard wired data lines and a simple control circuit can be distributed.

It is appropriate to have an interleaved word length greater than the maximum word length so that at least enough bits to complete a code word are included in each interleaved word. The interleaved words can then contain many code words and contain parts of code words. Fig. 3 illustrates an example of the nesting of a set of parallel code streams.

These words are interleaved according to the decoder request. Each independent decoder receives a whole nested word. The bit shift operation is now performed locally on each decoder, thereby maintaining the parallelism of the system. In Fig. 3, the first code word is in each interleaved word, the lowest remaining code word in the sentence. For example, the first interlaced words come from a code stream 1 , which begins with the never third code word (ie # 1). This is followed by the first nested word in code stream 2 and then the first nested word in code stream 3 . However, the next lower code word that is not fully contained in an already nested word is # 7. Thus the next word in the stream is the second interleaved word of code stream 2 .

In a different order, the order in which the later set of interleaved words (e.g., the code word that begins with code word # 8 in stream 1 , the code word that begins with # 7 in stream 2 , the code word that is based on begins with code # 11 in stream 3 ) in the nested code stream, on the first code word of the previous set of nested words (e.g., the code word that begins with code word # 1 in stream 1 , the code word that begins with the Codeword # 2 begins in stream 2 , the codeword that begins with codeword # 4 in stream 3 ) and they go from the interleaved word in the first codeword with the lowest number to the interleaved word with the first codeword with the highest Ordered number. Thus, in this case, since the interleaved word beginning with code word # 1 was the first, the next interleaved word in stream 1 is the first of the second group of interleaved words to be inserted in the interleaved stream, followed by the next most nested word in stream 2 and the next interlaced word in stream 3 follows. After the second group of interleaved words is inserted into the interleaved stream, the next interleaved word in stream 2 would be the next interleaved word that was inserted into the stream, since code word # 7 is the lowest codeword of the second sentence of interleaved Words is (followed by code word # 8 in stream 1 and then code word # 11 in stream 3 ).

Using the current decoder as the model for the Da tenstrom is responsible for the design choice and delays to generate the nested stream. Surrender no big cost for duplex systems that are both coders also have decoders. This can apply to any parallel set of Data words of different lengths (or different  Size) are generalized in one of the deterministi order are processed.

Code types and bitstream generators for parallel decoding

In the invention, existing encoders such as Q-Coder or B coder used as the bitstream generating elements which are arranged in parallel. However, other codes can and encoders can be used. The encoders and their assigned th codes used in the present invention are simple encoders.

In the invention, using one bitstream provides genes rator with a simple code instead of a complex code like the arithmetic code used by the Q coder is, or the multi-state codes provided by the B coders have been used, advantages. A simple code is advantageous because the hardware execution is much faster and one is thinner and requires less silicon than a complex one Code.

Another advantage of the invention is that the Co The efficiency can be improved. A code which is a cannot use finite amount of state information error-free the Shannon entropy limit for each probability meet. Known codes executed in hardware, at which a single bitstream generator likely or contexts have limitations, which reduce the coding efficiency. Resolving the Be constraints that apply to multiple contexts or probability classes are necessary, allows the use of codes that get closer to the Shannon entropy limit.

R codes

The code (and encoder) used in one embodiment of the Er is used is referred to as the R code. R codes are adaptive codes that have a variable number of identical  Convert input symbols into a code word. In an execution form the R codes are parameterized so that many different Probabilities with a single decoder design can be traded. In addition, the R codes of the Er finding decoded by simple, very fast hardware will.

In the invention, the R codes are used by an R encoder to perform coding or decoding. In one embodiment, an R encoder is a bitstream generator that is combined with a probability assessment module. For example, in FIG. 33, an R-encoder could include the combination of a probability assessment module 102 and a bit stream generator 103 and the combination of a probability assessment module 105 with a bit stream generator 106 .

Code words represent runs of the most likely symbol (MPS). An MPS represents the result of a binary decision with a probability of more than 50%. On the other hand the least likely symbol (LPS) represents the result a binary decision with less than 50% probability if two results are equally probable, it doesn't matter which one is MPS or LPS, as long as both the encoder and the decoder have the same loading make drawing. The resulting bit sequence in the kompri mated file is in Table 1 for a given parameter to which reference is made as MAXRUN.

table

Bit generation coding

To encode, the number of MPSs in one pass is calculated using counted by a simple counter. If this count is equal to that MAXRUN count value, a 0 code word is added to the code stream and the counter is reset. When an LPS is encountered then a 1, followed by bits N, which clearly describe the number of MPS symbols in front of the LPS, in introduced the code stream. (There are many options here Allocate the N bits to describe the pass length.) The counter is reset again. The number of bits that required for N depends on the value of MAXRUN. It could also use a ones (1′s) complement of the code words will.

To decode when the first bit in the code stream is 0, the value of MAXRUN is stored in the MPS counter, and the LPS display is deleted. Then the 0 bit is thrown away. If the first bit is a 1, then the following bits are ge checks to extract bits N and the corresponding count value (N) is set in the MPS counter, and the LPS indicator is set. Then the code stream bits, which the 1N Co word included, thrown away.

R codes are generated in accordance with the specifications in Table 1. The definition of a given R code Rx (k) is defined by MAX RUN set, for example:

MAXRUN for Rx (k) = x _* 2 ^k-1

therefore:

MAXRUN for R2 (k) = 2 _* 2 ^k-1
MAXRUN for R3 (k) = 3 _* 2 ^k-1
etc.

R codes are a subset of Golomb codes. It should be noted that Rice codes only use R2 (⚫) codes. The R codes of the invention allow the use of both R2 (k) and R3 (k) codes and other Rn (k) codes if necessary. In one embodiment, R2 (k) and R3 (k) are used. Rn exists for n = 2 and n is equal to an odd number (e.g. R2, R3, R5, R7, R9, R11, R13, R15). In one embodiment, the pass count r is encoded in N for the R2 (k) code; the run count r is described in k bits, so that 1N is represented with (k + 1) bits. Likewise, in one embodiment for an R3 (k) code, the bits may include N ¹ bits to indicate whether n <2 ^(k-1) or n 2 ^(k-1) , and either (k-1) or k bits around to display the pass count r so that the variable N is represented by a total of k or (k + 1) bits. In other embodiments, the 1′s complement of N could be used in the code word. In this case, the MPS aims to generate code streams with many 0's, or LPS aims to generate code streams with many 1's.

Tables 2 through 5 illustrate some efficient R codes which have been used in one embodiment of the invention are. It should be noted that other run length codes in the invention can also be used. An example an alternative run length code for R2 (2) is in Table 6 shown. Tables 7 and 8 show examples of the codes that have been used in one embodiment.  

Table 2 - R2 (0)

Table 3 - R2 (1)

Table 4 - R3 (1)

Table 5 - R2 (2)

Table 6 - Alternative R2 (2)

Table 7 - Alternative R3 (2) code

Table 8 - Another Alternative R2 (2) Code

Probability evaluation model for R codes

In one embodiment, the R2 (0) code does not encode: an input of 0 is encoded into a 0, and an input of 1 is encoded into a 1 (or vice versa) and is optimal for probabilities equal to 50%. The R2 (1) code of the preferred embodiment is optimal for probabilities close to 0.707 (ie 70.7%) and the R3 (1) code is optimal for the 0.794 probability (79.4%). The R2 (2) code is optimal for the 0.841 probability (84.1%). Table 7 illustrates the almost optimal run length code, the probability offset being determined by the following equation:
Probability offset = -log₂ (LPS)

Table 9

The codes are almost optimal, so that the probability range, as indicated by the probability offset is covering the room relatively evenly, even if the optimal probabilities not so much in the higher ones Differentiate k values than in the low k values.

Reference is now made to the probability at which is an optimal R code. In fact, only R2 (2) hits that Entropy curve. A real view shows for which truth range of probabilities a certain R code is better than all R codes in a given class. The following table len see the probability ranges for the class of R2 Codes and for the class of R2 and R3 codes before.

The ranges in apply to the class of R2 codes from 0 to 12 Table 10 below. For example, if only R2 codes are used R2 (0) is the best if 0.50 probability is 0.6180  is. Likewise, R2 (1) is the best if 0.6180 applies Probability 0.7862.

Table 10 - R2 codes from 0 to 12

The solutions for the class of R2 and R3 codes are in table 11 given below. For example, if R2 and R3 use codes R2 (1) is the best if: 0.6180 probability possibility 0.7549.  

Table 11 - R2 and R3 codes

Lengths less than or equal to 13 bits

An R2 (k) for a fixed k is called a track length code. Each but a fixed k is only the best for a probable one range. It should be noted that when close to an optimal one Probability is encoded, an R code according to the invention uses a 0 and 1N code words with approximately the same frequency.  

In other words, in half the time the R-Co a code from the invention, and in the other half time the R encoder gives the other code. By checking The number of 0 and 1N codewords can be a determination whether the best code is to be used. This means, if too many 1N code words are output, then the Pass length too long; on the other hand, if too many 0 code words are output, the run length too short.

The probability evaluation model, which Langdon ver has been used, the first bit of each code word checks to determine whether the source probability is above or below that current estimate is (See G.G. Langdon, "An Adaptive Run-Length Coding Algorithm, "IBM Technical Disclosure Bulletin, Vol. 26, No. 7B, December 1983). Based on this finding k is increased or decreased. For example, if a Co The word that indicates MPS is likely to be seen Quotation too low. Therefore according to Langdon k by 1 increased for every 0 code word. If a code word that is less than MAXRUN MPS indicates what an LPS (e.g. 1N code word) follows will see, the probability estimate is too high. Hence, according to Langdon, k is increased by 1 for each 1N code word drigt.

The present invention leaves a more complex likelihood rate rating than simply increasing or decreasing k by 1 for each code word. The invention contains a truth Probability assessment module state which to use sets the code. Many states can use the same code the. Codes become states using a state table orderly.

In one embodiment of the invention, the probability changes Estimation of each code word submitted. Hence increased or the probability assessment module lowers the Probability estimate depending on whether a  Codeword begins with a 0 or a 1. If, for example If a "0" code word is output, the Estimation of the MPS probability. If, on the other hand, a "1" Co When the word is output, the estimate becomes the MPS probability decreased.

The known Langdon encoder used only R2 (k) codes and increased or decreased k for each code word. The invention, however, uses R2 (k) and R3 (k) codes in conjunction with the status table in order to be able to match the adaptation rate to the application. That is, if there is a small amount of stationary data, the adaptation must be faster in order to result in an optimal coding, and if there is a larger amount of stationary data, the adaptation time can be longer, so that the coding can be chosen, to get better compression on the rest of the data. Where a variable number of changes in state can occur, specific application parameters can also influence the adaptation rate. Because of the nature of the R codes, the evaluation for R codes is simple and requires little hardware, while being very powerful. This is illustrated in FIG. 32 by a graph in which the coding efficiency (the code length, nominated with respect to the entropy) is plotted against an MPS probability. Figure 32 shows how some of the R codes of the invention cover the probable space. As an example, Fig. 32 shows that for an MPS probability of approximately 0.55, the efficiency of the R2 (0) code is 1.01 of the entropy threshold (or 1% worse than this). In contrast, the R2 (1) code has an efficiency of 1.09 (or 9% worse than) the entropy limit. This example shows that using the wrong code in this particular case is less likely to cause an 8% loss in coding efficiency.

The inclusion of the R3 (k) codes makes it possible to cover more probabilities with greater efficiency. An example of a probability evaluation status table le according to the invention is shown in FIG. 5. The table in Figure 5 shows both a state counter and the code associated with each of the separate states of the table. The table contains both positive and negative states. The table has 37 positive states and 37 negative states, including the zero states. The negative states mean a different MPS than the negative states. In one embodiment, the negative states can be used when MPS is 1 and the positive states can be used when MPS is 0 or vice versa. The table shown in Fig. 5 is only an example; other tables can have more or less states and a different state assignment.

Initially, the encoder is in state 0, which is the R2 (0) code (i.e. no code) for the probability advance beat, which is equal to 0.50. After each code word ver is working, the state counter is dependent on the first bit of the code word incremented or decremented. In an out In the embodiment, a code word of 0 increases the size of the memory. Therefore, each code word causes a change in the state the status counter. In other words, the truth Probability assessment module changes state. However, consecutive states are assigned to the same code the. In this case, the probability rating is without a change of codes achieved for each code word. With others Words, the state is changed for each code word; however the condition becomes the same probability at certain times depicted. For example, all states use 5 to -5 the R2 (0) code, while states 6 to 11 and -6 to -11 use the R2 (1) code. Using the state table of the Invention cannot do a probability assessment in one stay with the same encoder linearly.

It should also be mentioned that more states with the same R code for the low probabilities are included, and This is because the loss of efficiency if the wrong one  Code used at low probabilities is great is. The type of run length code state table is this to transfer between states after each code word. In a State table that is designed to hold codes with any state change to change when between states at low Probabilities is changed, the code alternates between a code that is very close to the entropy efficiency limit and a code that is far from the entropy-we efficiency limit is gone. As a result, a disadvantage (in Form of the number of coded data bits) in the transition between conditions. Conventional probability evaluators tion modules, such as the Langdon probability assessment module loses its effectiveness because of this disadvantage.

In the run length codes, the probability is higher part that results from the wrong code is not that big. Consequently, additional states become the in the invention added lower probabilities so that the changes increased when fluctuating between the two correct codes become, whereby the coding inadequacy is reduced.

In certain embodiments, the encoder may initially likelihood assessment state. With others Words, the encoders could be in a predetermined state, state 18, for example. In an execution another state table could be used so that some states would be used for the few first symbols to allow quick adaptation and a second state Table could be slow for the remaining symbols Adaption used to fine-tune the probability enable evaluation of In this way, the Co be able to use more effective code in the Co to use the process. In another embodiment, could the code stream an initial probability estimate specify for each context. In one embodiment the increments or decrements are not a fixed number  (e.g. 1). Instead, the probability Be status by a variable number corresponding to the Amount of data already encountered or the change in the Data (whose stability) are incremented. Examples of such Tables are in the tables described below 21 to 25.

If the state table is symmetrical, as the exemplary table of FIG. 4 shows, only half of it (including the zero state) has to be stored or executed in hardware. In one embodiment, the state number is stored in a sign size (ones) complement form to take advantage of the symmetry. In this way, the table can be used by taking the absolute value of one's complement number to determine the state and to check the sign, thereby determining whether MPS is a 1 or a 0. This enables the hardware needed to increment and decrement the state to be reduced since the absolute value of the state is used to index the table and the calculation of the absolute value of ones complement numbers is trivial. In another embodiment, a state table can be replaced by a hard-wired or programmable state device with respect to greater hardware efficiency. A hard wired state to encode a converter is an execution of the state table.

Overview of the balanced parallel entropy coding system stem

The invention provides a balanced parallel entropy coding system, which is both a real-time coding and a Real-time decoding includes what's in a very fast len / inexpensive hardware has been performed. The present de Invention can be used in numerous lossless coding applications can be used, including real-time compression / De compression of data on recordable discs or magne tables, a real-time compression / decompression of  Computer network data, a real-time compression / decompression of Image data in a compressed frame memory in a multi functional device (e.g. copier, facsimile device, scanner, printer, etc.) and real-time compression / decompression of sound data; however, the invention is not limited to this.

Specifying the performance of the encoder requires a ge know attention. It's easy to design an encoder which reaches a certain rate for the original data that entered into a sufficiently fast coded data channel are. In many applications, however, the goal is with the Encoder to use the encoded data channel efficiently. A co Data channel usage is determined by the maximum burst rate of the original data interface, through the coding speed and the compression achieved on the data is restricted to 99999 00070 552 001000280000000200012000285919988800040 0002019536401 00004 99880. The We These effects must be reflected in some local data which depends on the buffering in the encoder hangs. It is desirable to have an encoder that can uses the encoded data channel efficiently while encoding speed and high compression is maintained and the maximum burst rate is still set.

The encoder of the invention will now be described. On Decoder used in conjunction with the encoder can also be described.

Real time coding in the present invention

Figure 5 is a block diagram of the coding system of the invention. In one embodiment, the encoder of the invention performs real-time coding. In Fig. 5, the coding system 600 includes an encoder 602, with a context (CM) and a state memory 603 is connected, corresponding to coded information in the form of code word information 604 to generate the original data six hundred and first A codeword information 604 generates a coding unit 606, in cooperation with a reordering memory 607 , a coded data stream 608 . Here, the coding system 600 is not limited to working with code words and, in other embodiments, may operate on discrete analog waveforms, variable length bit patterns, channel symbols, alpha, events, etc. within the teachings of the invention.

Encoder 602 includes a context model (CM), a probability assessor (PEM), and a bitstream generator (BG). The context model and the probability estimator (PEM) in the encoder 602 (apart from the direction of the data flow) are essentially identical to the corresponding units in the decoder. The bit generator of encoder 602 corresponds to the decoder bit generator and is described below. The result of coding by encoder 602 is the output signal in the form of zero or more bits representing the original data. In one embodiment, the output signal of the bitstream generator also includes one or more control signals. These control signals create a control path to the data in the bit stream. In one embodiment, the code word information may include a pass indicator start, an end of a pass indicator, a codeword, and an index that identifies the pass count (which is of the context or probability class) for the codeword. An embodiment of the bit generator of the invention is described below.

The reordering unit 606 receives the bits and control signals generated by the bit stream generator (if any) of the decoder 602 and generates encoded data. In one embodiment, the encoded data provided by reordering unit 606 comprises a stream of interleaved words. In one embodiment, reordering unit 606 performs two functions, moving code words from the end of runs generated by the encoder to the start of runs, if necessary by the decoder, and combining variable length code words interleaved fixed length words and outputs them in the correct order as required by the decoder.

The reordering unit 606 temporarily uses a reordering memory 607 . In an embodiment in which coding is performed at a work station, reordering memory 607 can be over 100 megabytes in size. In the balanced system of the invention, reorder memory 607 is much smaller (e.g., approximately 1 Kbyte) and fixed. Thus, in one embodiment, real time encoding is performed using a fixed size memory, even if this increases the memory required by the decoder or the bit rate increases (for example, if an output signal is made before a run is completed). The decoder of the invention is capable of determining the effects of the reorder unit's limited memory using, for example, explicit, explicit, or stream signaling (as will be described below). Reordering unit 606 has finite memory available for reordering; however, the "required" memory is not tied up. Both the effect of limited memory for a pass end to the start of a pass queue and for reordering of nested words must be considered.

In one embodiment, the coding system (and ent speaking decoding system) of the invention encoding (or De encoding) using a single integrated circuit chip by. In another embodiment, a single one contains in integrated circuit including the coding system of the invention Lich its encoder, decoder and memory. A separate one external memory can be added to encode support. A multichip module or an integrated scarf device can encode / decode hardware and memory contain.  

The coding system of the invention can be used to try the effective bandwidth by up to a factor N to increase. If the compression achieved is less than N: 1, then the coded data channel is fully used, but the reached effective bandwidth increase only equal to the compression rate. If the compression achieved is greater than N: 1, then it is effective bandwidth reached, with an additional bandwidth is writable. In both cases, the compression achieved over a local area of the data, which are determined by the buffer value present in the coding system is defined.

The bit generator for the encoder of the invention

Figure 6 shows an embodiment of the encoder bit generator of the invention. Bit generator 701 is provided to receive a probability class and an uncoded bit (e.g., an MPS or LPS display) as inputs. The bit generator 701 outputs a plurality of signals in accordance with the input signals. Two of the output signals are control signals which represent the start of the start and end of a pass (each code word representing a pass), a start signal 711 and an end signal 712, respectively. It is possible to start and end a run at the same time. When a run starts or ends, an "index" output 713 has an indication of the probability class (or context) for the uncoded bit. In one embodiment, an index output signal 713 represents a combination of the probability class for the bit and bank identification for systems in which each probability class is replicated in multiple memory banks. A code word output 714 is used to output a code word from the bit generator 701 when a pass ends.

A memory 702 is connected to bit generator 701 and contains the pass count for a given probability class. During bit generation, the bit generator 701 reads from the memory 702 using the index (e.g. the probability class). After reading the memory 702 , the bit generator 701 performs bit generation in the following manner. First, when the pass count is zero, a start signal 711 is asserted to indicate the start of a pass. If the uncoded bit is equal to the LPS, then the end signal 712 is asserted to indicate the end of the run. If the uncoded bit is equal to an LPS, code word output 714 is set to indicate that the code word is a 1N code word and the pass count is cleared, e.g. B. set to zero (since it is the end of the pass). If the uncoded bit is not equal to the LPS, then the pass count is incremented and a check is made to determine if the pass count equals the maximum count for the code. If so, the end signal 712 is asserted, the code word output 714 is set to zero, and the pass count is cleared (e.g., the count is set to zero). If the check determines that the pass count is not the maximum for the code, then the pass count is incremented. Index signal 713 represents the probability class that has been received as an input signal.

In the invention, the generation of 1N code words is performed so that their length can be determined without additional information. Table 12 illustrates 1N code word representations of R3 (2) code words for the decoder and encoder. The decoder expects the "1" bit in a "1N" codeword to be the least significant bit (LSB) and the "N" count portion in the correct MSB. . . LSB order is present. In the decoder, the variable length code word cannot be distinguished from zero padding without knowing which specific code is used. In the encoder, the code word is reversed and the position of the most significant "1" bit indicates the length of "1N" code words. To generate codewords in an encoder order, the complement of the count must be reversed. This can be accomplished by inverting the 13-bit count and shifting it so that it is aligned with the least significant bit (LSB). As will be described in more detail below, the bit packer reverses the code words into the decoder order. However, this reversal of code words does not result in increased complexity of the bit pack unit 606 since it must somehow perform a push.

Table 12

"2N" code word representations for R3 (2) code words

For R3 codes, generating "N" code words also requires that the bit following the "1" indicates whether a short or there is a long count.

The invention enables the use of several memory banks a pipelining. For example, in the case of a memory multi-port read operation for a memory for an uncoded bit during a read operation on the Memory for the previous uncoded bit occurs.  

An Altera AHDL scanning version

An embodiment of the encoder bit generator of the invention has an FPGA. The execution covers all R2 and R3 codes up to R2 (12). The AHDL (Altera Hardware Description Language) source code is listed below.

The design has several parts, as shown in Fig. 12 is Darge. First, "ENCBG" 1301 is the main part of the design that has the logic to handle the start, end, and continuation of passes. Second, "KEXPAND" 1302 is used to extend the probability class to the maximum run length, a variable length mask and the length of the first long code word for R3 codes. "KEXPAND" 1303 is identical to the decoding function with the same name. Third, the "LPSCW" 1304 takes part in a count and information about the probability class in the form of input values and generates the correct "1N" code word.

The execution uses two pipeline stages. During the he Most pipeline stage increments the count, the true Probability class is expanded, and a subtraction and a comparison for long R3 code words is made. All remaining operations will take place during the second pipeline stage carried out.

The reordering unit of the invention

Fig. 7 is a block diagram of an embodiment of the Umord-drying unit. In FIG. 8, the reordering unit 6 has a through count reordering unit 801 and a bit pack unit 802 . The reordering unit 801 moves code words from the end of runs as generated by the encoder to the start of runs as required by the decoder, while the bit packer unit 802 summarizes variable length code words into nested fixed-length words and delivers them in the correct order as required by the decoder.

A "snooper" decoder can be used to make a deco reorder, with a decoder included in the encoder is, and creates requests for data in order in which the code words for the actual decoder are needed. To support a "snooper" decoder, can rearranging pass counts independently for each stream be performed. For decoders who are easily modeled can, multiple time stamped queues can or a single merged queue can be used, to allow reordering. In one embodiment, a Rearrange each code word using a snake-shaped da structure and is independent of the use of several coded data streams. How to rearrange can be performed, will be described below.

The first reordering operation performed in the encoder is to rearrange each of the pass values so that  the run value is specified at the start of the run, (if the decoder is necessary for decoding). This Rearranging is required because the encoder doesn't finish of a pass can determine what a pass count (and a code word). Hence the resulting through reordered run count value that was generated during coding, so that the decoder is able to read the pass counts decode back into the data stream correctly.

In Fig. 7, the reordering unit 606 of the invention has a pass count reordering unit 801 and a bit packing unit 802 . The reordering unit 804 is arranged to receive a plurality of input signals, which include a start signal 711 , an end signal 712 , an index signal 713 and a code word 714. These signals are described in detail in connection with the run count reordering unit of FIG. 8. According to the input signals, the reordering unit 801 generates a code word 803 and a signal 804 . Signal 804 indicates when the counting value is to be reset. The code word 803 is received by the bit packing unit 802 . According to the code word 803 , the bit packing unit 802 generates nested words 805 . The reordering unit 801 and the bit pack unit 802 will be described in detail later.

Pass count shuffling unit

As described above, the decoder obtains code words the time when the beginning of the data by the code word have been encoded. However, the encoder knows not the identity of the code word until the end of the data have been encoded by the code word.

A block diagram of one embodiment of the run count reordering unit 801 is described with reference to FIG. 8. The described embodiment adapts to four interleaved streams, each interleaved word being 16 bits, and the codewords changing in length from 1 to 13 bits. In such a case, the reordering unit 300 can be processed in the pipeline system to handle all streams. Furthermore, an encoder that maps run counts to probability classes is used so that the maximum number of run counts that may be active at any given time is small, and is assumed to be 25 in this embodiment. The invention is not limited to four interleaved streams, interleaved words with 16 bits or code word lengths from 1 to 13 bits and can be used for more or fewer streams with interleaved words of more or less than 16 bits and for code word lengths that extend from 1 bit to over 13 bits.

In Fig. 8, a pointer counter 901 is provided to receive an index input signal 713 and generates an address output signal which is connected to an input of a multiplexer (MUX) 902 . Two further inputs of the MUX 902 are provided to receive an address in the form of a head pointer from a head counter 903 and an address in the form of a tail pointer from a tail counter 905 . The output of the MUX 902 is an address that is used to access a code word memory 908 .

An index input signal 713 is also provided as an input to the MUX 905 . Another input of the MUX 905 is coupled to the codeword input signal 719 . The output of the MUX 905 is connected to an input of a validity module 906 and a data bus 907 . The data bus 907 is connected to a code word memory 908 and an input of the MUX 905 . An output of a control module 909 is also connected to the data bus 907 . A start input signal 711 and an end input signal 712 are provided to separate inputs on the control module 909 . The output signals of the validity module 906 have the code word output signal 803 and the signal 809 ( FIG. 7). The reordering unit 801 also includes a control logic (not provide Darge to the invention are not to obscure las sen) for the operations of the various components of the order ordering unit to coordinate eight hundred and first

To repeat, an index input 713 identifies a pass. In one embodiment, the index displays one of 25 probability classes. In such a case, who needs the five bits to represent the index. If multiple arrays (banks) of probability classes are used, additional bits may be required to specify the particular array. In one embodiment, the index input signal identifies the probability class for the pass count. A codeword input signal 714 is the codeword when the end of a run occurs and it otherwise becomes "don't care". Start input signals 711 and end input signals 712 are control signals that indicate whether a run begins, ends, or both. A run begins or ends at the same time when the run consists of a single uncoded bit.

The shuffling unit 801 shuffles the pass counts generated by the bit generator according to their input signals. A code word memory 908 stores code words during reordering. In one embodiment, code memory 908 is greater than the number of pass counts that may be active at a particular time. This leads to better compression. Indeed, if the code word memory is less than the number of pass counts that may be active at any given time, this would limit the number of active pass counts to a number that could be held in memory. In a system that provides good compression, it often happens that while data is being accumulated for a code word with a long pass count, many code words start (or maybe end) with short pass counts. This requires a large memory to avoid pushing out the long run before it is finished.

Pointer memory 901 stores addresses for codeword locations for probability classes that are in the middle of a pass and addresses a codeword memory 908 in the manner of a direct access. Pointer memory 901 has a location for the address in code word memory 908 for each probability class, which may be in the middle of a pass. Once a run is completed for all be true probability class, the address stored in the pointer memory 901 for this probability Klas se, used to access a code word memory 908, and the finished code word is written at this point in the code word memory 908 . Up to this point, this location in the code word memory 908 contained an invalid entry. Thus, pointer memory 901 stores the position of the invalid code word for each pass count.

The head counter 903 and the lag counter 904 also generate addresses to access the code word memory 908 . Using counters 903 and 904 , code word memory 908 can be a queue or a circular buffer (e.g., a FIFO memory). The follow-up counter 904 contains the address of the next available location in the code word memory 908, allowing for the insertion of a code word in the memory 908th The head counter 903 contains the address in the memory 908 of the next code word to be output. In other words, the head counter 903 contains the code word memory address of the next code word to be deleted from the memory 908 . A location for each possible index (e.g., a probability class) in pointer memory 901 is used to remember where the lag counter 904 was when a run was started so that the correct codeword places the codeword memory 908 at that location can be when the run ends.

A control module 903 generates a valid signal as part of the data stored in code word memory 908 to indicate whether or not an entry stores valid memory word data. For example, if the valid bit is a logic 1, then the code word location contains valid data. However, if the valid bit is at logic 0, then the code word location contains invalid data. A validity module 905 determines if a memory location contains a valid code word each time a code word is read from the memory 809 . In one embodiment, the validity module 907 senses whether the memory location is a valid code word or a special invalid code.

When a new run starts, an invalid data entry is made in the code word memory 908 . The invalid data entry acts as a placeholder in the data stream stored in memory 908 , so that the pass code word can be stored in memory in the correct location to ensure proper ordering (to model the decoder) when the run is finished. In one embodiment, the invalid data entry includes the index via the MUX 905 and an invalid indication (e.g., an invalid bit) from the control module 909 . The address in code word memory 908 where the invalid entry is stored is entered by a trailing pointer 904 and then stored in pointer memory 901 as a remainder of the location for the pass count in code word memory 908 . The rest of the data completed between the head pointer 903 and the trailing pointer 904 in memory 908 completes run counts (e.g., disordered run counts). The maximum number of invalid memory locations is 0 to | -1, where | is the number of cycle counts. When a code word is complete at the end of a pass, the pass count in memory 908 is filled with the address stored in pointer memory 901 .

When a run starts, the index for the run is stored in memory 908 so that when memory 908 is full but the run is not yet complete, the index in conjunction with signal 804 is used to reset the corresponding run counter . In addition to storing codewords and indexes in memory 908 , a bit referred to as the "valid" bit is used to indicate which of these types of data is stored.

If a run does not start or end, the run count shuffling unit is empty. If a run starts and a run does not end, and if the memory is full, then a code word is output from memory 908 . The code word that is delivered is the code word that has been stored at the address contained in the head pointer 903 for this probability class. Then, when a run starts and a run does not end, (regardless of whether the Spei is cher full) is written, the index input signal 713 to the memory 908 via MUX 903 to the position determined by the trailing pointer 904 address. Trailing pointer 904 is then written to trailing memory 903 at an address determined by the data in index input signal 713 (e.g., at the location in pointer memory 901 for the probability class). After the trailing pointer 904 is written, the trailing pointer 904 is incremented.

If a run ends and a run does not start, then the address stored in pointer memory 901 corresponding to the index (probability class) is read out and used as the location in the code word memory to include the completed word in the code word input 714 store.

When a run starts and a run ends (ie, a run both starts and ends at the same time) and when the memory is full, a code word is output from the memory 908 . When a run starts and a run ends, regardless of whether the memory is full, the code word input 714 is written into the memory 908 at the address specified by the tracking pointer 904 . The trailing pointer 904 is then incremented to obtain the next available location (e.g., it is incremented by 1).

In the invention, a reordering unit 801 can output code words at different times. In one embodiment, code words can be output if they are valid or invalid. Code words can be output if they are valid, if there is a state that the memory is full and a pass has not been completed. Invalid codewords can also be issued to maintain a minimum rate (ie, for rate control). Likewise, invalid code words may be issued to equalize code word memory 908 when all data has been subjected to a run count reordering or when a run count reordering unit jumps to the center of a code word store 908 as a result of a reset operation. In such a case, the decoder must realize that the encoder works in this way.

As described above, a code word is output when the code word memory 908 is full. Once the memory is full, when an input (ie, a new code word is started) to the memory 908 , an output signal is output from the memory 908 . Updating to an entry does not produce an output from memory 908 when there is a condition that the memory is full. That is, the completion of a run followed by the writing of the resulting code word in a previously allocated memory location does not cause an output signal to follow when the memory is full. Likewise, when a run ends and the corresponding address in pointer memory 901 and the address in head counter 903 are the same, the code word can be immediately given and the head counter 903 can then be incremented without accessing code word memory 908 . In one embodiment, a state occurs that the memory is full when the tail pointer 904 is equal to the head pointer 903 after the tail pointer has been incremented. Thus, once the trailing pointer 904 has been incremented, the control logic in the reordering unit 801 is equal to the trailing pointer 904 in the header pointer 903 , and if they are the same, the control logic determines that the code word memory 908 is full and that a code word should be output . In another embodiment, code words can be output before the memory is full. For example, if the part of the queue addressed by the header contains valid code words, it is output. This requires that the beginning of the queue be checked repeatedly to determine the state of the code words therein. Code word memory 908 is cleared at the end of file encoding.

A code word is output by the reordering unit 80 in which a value (eg a data value) is first read from the memory 908 at an address specified by the head pointer 903 . The output of code words is controlled and coordinated using the control logic. The validity module 906 checks to determine if the value is a code word. In other words, the validity module 906 determines whether the code word is valid. In one embodiment, the validation module 906 determines the validity of an entry by checking the validity bit that has been stored for each entry. If the value is a code word (ie the code word is valid), then the value is output as a code word. On the other hand, if the value is not a code word (ie the code word is invalid), then any code word can be output that has a pass of MPSs that is at least as long as the current pass count. The "0" code word is a code word that correctly represents the current run and can be output. After the output is done, the head pointer 903 is incremented to the next position in the code word memory 908 . On the other hand, with the aid of "1N" with the shortest permissible throughput lengths, the decoder can only check whether a code word has been pressed out before an LPS is issued.

In one embodiment, reordering unit 801 operates on two clock cycles. In the first clock cycle, inputs are added to reordering unit 801 . In the second clock cycle, an output occurs at code word memory 908 .

Although code words may be output when a head pointer 903 addresses a valid code word, in some implementations it may be desirable to output only one code word when the buffer is full. This causes the system to have a fixed delay in the form of a number of code words instead of a variable delay. If memory 908 can hold a predetermined number of code words, between the time a pass starts and is entered and when it is issued, the delay is the number of code words since an output has not been made until it is full . Hence there is a constant delay in the codewords. The reordering delay can be modified with other measures, for example with regard to the amount of encoded or original data. If a memory 908 is filled before generating an output signal, one code word is generated per cycle by the output signal.

If a codeword location is marked as invalid, the unused codes can be used to identify for which run count this is (i.e. the context subject or probability class that the Must be filled there is saved there). This information is useful to handle the case where the memory is full. In particular, the information can be used for who to indicate to the bit generator that a code word for this special run length has not ended, and that it has now ended must become. In such a case, a decision will be made  to output an invalid code word which is the result of the State that the memory is full may have occurred. Therefore, when the system resets the pass counter, the information on when regarding bit generators and by run counts, the system begins to restart.

Regarding the entry of the index, for pipelining reasons, if Banks of probability classes are used, the index contain a bank identification. That means there can be several Pass counts for a specific probability give great. For example, two pass counts for the 80% code should be used if only one and then the other is used.

Since the code words are of variable length, they must be stored in memory 908 in such a way that their length can be determined. Although it would be possible to save the size explicitly, this word would minimize memory usage. For R codes, a zero value in memory can indicate a one-bit "0" codeword and the "1N" codewords can be stored so that a priority encoder can be used to determine the length for the first "1" bit.

If memory 908 is one with multiple inputs (e.g., two inputs), this execution can be pipelined to handle one code word per one clock cycle. Since a location in memory 908 could be accessed by multiple inputs, a location in memory 908 can be described as if an invalid code word is to be stored, while another part can be read, such as if a code word is output. In such a case, multiplexers are to be multiplied to support the data and address buses.

However, if the encoder outputs a "0" code word and one Run counter resets because the code word memory is full the decoder do the same. This requires that the decoder  the encoder code word store queue is modeled. Like this is explained below.

To save performance in CMOS implementations, counters can for "| N" codewords can be made effective if "0" codewords are issued for invalid runs. That means there too decoding "1N" code word is valid, while only a "0" Co word may be invalid.

Alternative context based embodiment

Fig. 9 is a block diagram for another embodiment of a pass count reordering which data which have been received in accordance with a context umord net (which is opposite to a probability class). The rearrangement unit 1000 performs rearrangement using the R codes. In FIG. 9, unit 1000 includes a pointer memory 1001 , a head counter 1002 , a tracking counter 1003 , a data multiplexer (MUX) 1004 , an address MUX 1005 , a length calculation block 1006 , a validity lookup 1007 and a code word memory 1008 . Memory 1008 stores code words during the reordering. Memory 101 stores addresses for codeword locations for context bins that are in the middle of a pass. Through the counters 1002 and 1003 , a code word memory 1008 can be addressed as a queue or a circular buffer and additionally in the manner of a direct access through the pointer memory 101 . For R codes, storing a zero value in memory may indicate a one bit "0" code word, and the "1N" code words may be stored so that a priority encoder can be used to determine the length from the first "1" bit. A length calculation block or module 1008 operates like a priority encoder. (If other variable length codes were used, it would be more efficient to add a "1" bit to add the start of the code word than to add log 2 bits to store the length explicitly.) The reordering unit 1000 has one "Backstage" control logic to coordinate and control components 1001 through 1008 .

The operation of the reordering unit 1000 is very similar to the reordering unit, which is based on probability estimates. When a new run starts, an invalid entry including the contextual subject is written into the code word memory 1008 at the address indicated by the trailing pointer 1003 . An address of the trailing pointer 1003 is then stored in the pointer memory 1001 at the address of the context bin of the current pass count. The lag counter 1003 is then incremented. When a pass ends, the pointer in the pointer counter 1001 corresponding to the pass count is read from the pointer 1001 , and the code word is written in parallel to the code word memory 1008 at a location specified by the pointer. If a run neither starts nor ends and if a position in the code word memory 1008 , which is determined by the address of the head pointer 1004 , does not contain invalid data, the code word addressed by the head pointer is read in and output. The head pointer 1004 is then incremented. In the event that a run both simultaneously begins and ends, the code word in the code word memory 1008 at the ger by the Nachlaufzei 1003 specific address written and then the post is run pointer 1003 increments.

Similarly, when a run ends and the corresponding address in pointer memory 1001 and the address in header counter 1002 are the same, the code word can be output immediately, and the value in header counter 1002 can be incremented without resorting to code word memory 1008 .

For run count "context" systems, each context requests a memory location in pointer memory 1001 so that the width of the BG and PEM state memory can be expanded to implement this memory. The width of the pointer memory 1001 is equal to the size required for a code word memory address. The number of digits in code word memory 1008 can be selected by the developer in a very specific implementation. The limited size of this memory reduces compression efficiency so that it is trade-off cost / compression. The width of the code word memory is equal to the size of the largest code word plus one bit for a valid / invalid display.

An example with the R2 (2) code shown in Table 13 is used to illustrate reordering. Ta belle 14 shows the data to be reordered (0 = MPS, probable res symbol; 1 = LPS, less likely symbol) that as Context. There are only two contexts. The unco The number of bits indicates time in uncoded bit clock cycles. Start and end of runs are displayed, and code words are shown at the end of runs.

Table 13 - R2 (2) code

Table 14

Examples of data to be encoded

The reordering operation for the exemplary data is in Table 15 shown. A four-digit code word memory 0 to 3 is used, which is large enough in this case don't overflow. Each line shows the state of the Sy stems after an operation, which is either the start of the run or the end-to-end for a particular context or the Is output of a code word. An "x" is used to save to display jobs that are "don't care". For some unco dated bits neither starts nor ends, so that the reordering unit is empty. For coded bits that pass end, one or more code words can be output, which can cause several changes in the system state.  

Table 15

Example of reordering operations

In Table 15, the head and tail pointers are set to zero ini tialized, indicating that nothing in the code word memory  (e.g. the snake) is included.

The pointer memory is shown with two memory locations, one for each context. Every job has "don’t care" Values before a number of bits 1. The code word memory is with a Depth represented by four code words, all of which don't start care "values.

According to the data obtained for the number of bits 1 remains the head pointer is aimed at the code word storage location 0. Da the decoder expects data, the next available code word memory location, 0, assigned to the code word and an invalid Value is written to location 0. Because the context is zero, the address of the code word location corresponding to the Is assigned to a pointer memory location for the Zero context (pointer storage location 0) written. Consequently a "0" is stored in pointer memory location 0. The night running pointer is incremented to the next code word storage location 1 mented.

According to the data corresponding to the number of bits 2 remains the pointer is aligned with the first memory location (since there there has been no exit to increment). Because the Da ten the second context, context 1 context the next code word storage location the code word as a code word allocated memory location 1, as indicated by the trailing pointer shows, and an invalid value is shouted into the place ben. The address, code word position 1, is in the pointer memory position that corresponds to context 1. That is, the The address of the second code word location is in the pointer location 1 written. The trailing pointer is then in incremented.

According to the data corresponding to the number of bits 3, the Reordering unit empty because a run does not start or end det.  

According to the data corresponding to the number of bits 4 an end of a run for context 1 is displayed. Therefore, it will Code word "101" in the code word memory allocated to context 1 place written (code word location 1), as by the Pointer location for context 1 is displayed. The head and Trailing pointers remain the same, and the value in the pointer Context 1 location is not reused; so is he "don't care".

According to the data corresponding to the number of bits 5, the Reordering unit empty because a run does not start or end det. According to the data corresponding to the number of bits 6, the same type of operations as described above come for Bit 2 before.

According to the data corresponding to a bit number 7, the end of the pass for the code word for context 0 occurs. In this case, the code word "0" is written into the code word storage location (code word storage location 0), as indicated by the pointer storage location for context 0 (pointer storage location 0). Then the value at the pointer storage location is not used again, so that it is a "don't care" value. The code word storage location, which is determined by the head pointer, likewise contains valid data. Therefore, the valid data is output and the head pointer is incremented. By incrementing the head memory, a pointer is made to another code word storage location which contains a valid code word. As a result, this code word is output and the head pointer is incremented again. In this example, code words are output if they are OK, which is in contrast when the code word memory is completely full.

The uncoded bits are processed in accordance with above description constantly before. The code word storage location len are not accessible with the help of very specific contexts made so that code words from one of the context to one  very specific code word location during encoding a data file can be saved.

The bit pack unit

A bit packing unit is shown in FIG. 3, in which data which have been processed by the reordering unit before and after packing a bit are shown. In Fig. 3, 16 variable length code words are shown which are numbered from 1 to 16 to indicate the order of use by the decoder. Each code word is assigned to one of three coded streams. The data in each encoded stream is broken down into fixed length words called nested words. (Here, a single code word of variable length can be broken down into two nested words). In this example, the interleaved words are arranged in a single interleaved stream so that the order in the first variable length code word (or a partial code word) in a particular interleaved word determines the order of the interleaved word. Other types of ordering criteria can be performed. The advantage of nesting multiple encoded streams is that a single encoded data channel can be used to transmit data, and variable length shifting can be performed in parallel or in a pipeline for each stream.

The bit packing unit 802 of the invention receives the variable length code words from the pass count shuffling unit 803 and packs them into nested words. Unit 802 has logic to handle variable length code words and a merged queue reorder unit to output fixed length nested words in the correct order. In one embodiment, the code words are received by the reordering unit at a rate of up to one code word per clock cycle. A block diagram of one embodiment of bit packer 802 is shown in FIG. 10. In the following embodiment, four interleaved streams are used, each interleaved word being 16 bits; the code words change in length from 1 to 13 bits. In one embodiment, a single bit pack unit is provided in pipeline form to handle all streams. If unit 802 of the invention uses two port memory (or a register file), it can deliver one interleaved word per clock cycle. This can be faster than is required to maintain the rest of the encoder.

In Fig. 10, 802 has the Bitpackeinheit on a packing logic 1101 a current meter 1102 a memory 1103, caster pointer 1104 and a head counter 1105th The packaging logic 1101 is provided to accommodate the code words and is connected to the electricity meter 1102 , which is also connected to the memory 1103 . Memory 1103 is also connected to tracking pointers 1104 and head counters 1105 .

The current counter 1102 keeps track of the interleaved current to which the currently entered code word is assigned. In one embodiment, the electricity meter 1102 repeatedly counts the currents from 0 to N-1, where N is the number of currents. As soon as an electricity meter reaches 1102 N-1, it starts counting again from zero. In one embodiment, the electricity counter 1102 is a two-bit counter and counts from 0 to 3 (for four interleaved currents). In one embodiment, the electricity meter 1102 initializes to zero (e.g. via a global reset).

Packing logic 1101 mixes the currently entered code word with previously entered code words to form interleaved code words. The length of each of the code words can change. Therefore, packaging logic 1101 packs these variable length code words into fixed length words. The interleaved codewords generated by the packaging logic 1101 are output to the memory 1103 in order and are stored in the memory 1103 until the correct time to be output. In one embodiment, memory 1103 is a static random access memory (SRAM) or a register file with 64 16 bit words.

The interleaved words are stored in memory 1103 . In the invention, the size of memory 1103 is large enough to handle two cases. One case is the normal operating case where one interleaved stream has minimum length codewords and the other interleaved streams have maximum length codewords. This first case requires (3 × 3 = 39) storage locations. The other case is the initialization case, in which again a stream has short code words or such a minimum length and the other long code words or such a maximum length. For the second case in which (2 × 3 × 13 = 76) memory locations are sufficient, the operation of the PEM allows a denser limit (bound) of 76.

The memory 1103 in cooperation with the electricity meter 1102 and the trailing pointers 1104 carry out a rearrangement. The current counter 1102 shows a current current of a code word received from the memory 1103 . Each nested stream is assigned to at least one tracking pointer. Tracking pointer 1104 and head counter 1105 rearrange the code words. The reason for two tracking pointers per stream results from interleaving of the word N, which is required by the decoder when data in an interleaved word N-1 contains the start of the next code word. A tail pointer determines the location in memory 1103 to store the next interleaved word from a given interleaved stream. The other trailing pointer determines the location in memory to store the nested word after the next one. This enables the location of an interleaved word N to be specified when the decoder request time of the interleaved word N-1 is known. In one embodiment, the pointers are eight 6-bit registers (two tracking pointers per stream).

In one embodiment, at encoding start, the trailing pointers 1104 are set such that the first eight interleaved words (two from each stream) are stored in the memory 1103 one by one from each stream. After initialization, each time the packing logic 1101 a new verschach teltes word for a very specific code stream begins, the "next" follow-up pointer to a value of "the next" after running memory of the code stream is set to the next available memory location. Hence there are two wake pointers for each stream. In another embodiment, only one tracking pointer is used for each stream and indicates where the next interleaved word is to be stored in memory 1203 .

Header memory 1105 is used to determine the location of the next interleaved word to be output from bit packer 802 . In the described embodiment, the head counter 1105 has a 6 bit counter that is incremented to deliver an entire interleaved word at a particular time.

The memory 1103 to be used in addition for reordering can also be used as a FIFO buffering between the encoder and the channel. It may be desirable to have this memory larger than what is required for reordering so that a FIFO mostly full signal can be used to "stall" the encoder when the Cannot keep up with the encoder. A one bit per cycle encoder cannot generate one interleaved word per cycle. If an encoder is well matched to a channel, the channel cannot accept an interleaved word on every cycle and some FIFO buffering is necessary. For example, a channel that can take a nested 16 bit word every 32 cycles would be a well-matched design for an effective bandwidth expansion of 2: 1 if the compression was 2: 1 or greater.

The packaging logic of the invention

A block diagram of the packaging logic is shown in FIG. 11. In FIG. 11, the packaging logic 1101 has a size unit 1201 , a set of accumulators 1202 , a slide unit 1203 , a MUX 1204 , a set of registers 1205 and an OR logic 1206 . The size unit 1201 is provided to accommodate code words and is connected to accumulators 1202 . The accumulators as well as the code words are coupled to the shift unit 1203 . The shift unit 1203 is connected to the MUX 1204 and the OR logic 1206 . MUX 1204 is also connected to registers 1205 and an output of OR logic 1206 . The registers are also connected to OR logic 1206 .

In one embodiment, code words are input to a 13 bit bus with zero bits not used. These zeroed unused bits are adjacent to the "1" in "1N" codewords, so a priority encoder in size unit 1201 can be used to determine the length of the "1N" codewords and a size for "0" codewords to create.

Accumulators 1202 have multiple accumulators, one for each nested stream. The accumulator for each interleaved stream receives a record of the number of bits that are already in the current interleaved word. In one embodiment, each accumulator has a 4-bit adder (with carry) and a 4-bit register that is used for each stream. In one embodiment, the output of the ad dierers is the output of the accumulator. In another embodiment, the output of the register is the output of the accumulator. With the help of the size of the code words which have been recorded in the size unit 1201 , the accumulators determine the number of bits to be shifted in order to concatenate the current code word in the register which contains the current interleaved word for this stream.

Based on the current value of the accumulator, the shifter aligns the current word so that it follows any previous code words in the nested word. As a result, data in the encoder is shifted in the decoder order. The output of the shifter 1203 is 28 bits, dealing with the case where a 13 bit code word must be appended to 15 bits in the current interleaved word so that bits from the current code word end into the higher 12 bits of the 28 bits to be output . Here, the sliding unit 1203 works without feedback, and can therefore be processed in the pipeline system. In one embodiment, push unit 1203 has a barrel push unit.

Registers 1205 store bits in the current nested words. In one embodiment, a 16 bit register holds previous bits in the current interleaved word for each interleaved stream.

Initially, a code word of a current is obtained from the shift unit 1203 , while a size unit 1201 indicates the size of the code word on the accumulator which corresponds to the current. The accumulator has an initial value of 0, which has been set via a global reset. Since the accumulator value is zero, the code word is not shifted and is then OR'd using OR logic 1206 , the content of the register corresponding to the current. However, in some embodiments, 1N code words must be shifted to be properly aligned even at the start of a nested word. This register can be initiated at zero, and clearly the result of the OR operation is to set the code word in the rightmost bit positions of the output of OR logic 1206 and become the register for storage via MUX 1204 fed back to the next code word from the stream. Accordingly, the pusher unit 1203 initially operates as one pass. The number of bits in the first code word are now stored in the accumulator. Upon receipt of the next code word for this stream, the value in the accumulator is delivered to the shifter 1203 and the code word is shifted left to the number of bits for combining with any previously entered bits in the interleaved word. Zeros are placed in the other bit positions in the shifted word. Bits from the register that correspond to the current are shifted with bits from shift unit 1203 using OR logic 1206 . When the accumulator generates a carry indication (e.g., a signal), more bits are required to complete the current interleaved word, and the data resulting from the OR operation is transferred to the MUX 1204 Register reset. In one embodiment, the MUX 1204 has a 2: 1 multiplexer. When the accumulator produces a carry, the 16 bits of the ORED data from OR logic 1206 is a complete interleaved word and is then output. The MUX 1204 causes the register to be loaded with any additional information (e.g., the top 12 bits of the 28 bits output by the shifter 1203 after the first 16 and fills the rest with zeros) .

The control for both the MUX 1204 and for outputting the interleaved word has the carry signal from the accumulator. In one embodiment, multiplexer 1204 has sixteen 12: 1 multiplexers, four of which have an input value that is always zero.

Reorder options

The invention provides many options for performing data rearrangement. For example, in a system with multiple code streams, the code streams must be rearranged in nested words, as shown in FIG. 3. The invention therefore provides numerous ways to achieve reordering in nested words.

One method of reordering data into nested words is to use a so-called Snooper decoder, as shown in FIG. 24. In Fig. 24, a plurality of run count shuffling units 2501 A-n are provided to receive code word information together with the code word stream. Each unit generates a code word output value and a size output value. A separate bit pack logic unit ( 1101 ), such as bit pack units 2502 A-n, are provided to receive the code word and size output values from one of the reordering units 2501 A-n. Bit pack logic units 2502 A-n deliver interleaved words which are supplied to both MUX 2503 and decoder 2504 . The decoder 2504 provides a selection control signal received from the MUX 2503 and indicates to the MUX 2503 which interleaved word is to be put into the code stream.

Each encoded data stream has a pass count shuffling unit which has a pass count shuffling unit 801 in FIG. 7. Each bit pack unit combines variable length code words into fixed length logic words, for example 8, 16 or 32 bits per word. Each bit pack unit contains registers and a shift circuit as described above. Decoder 2504 has a fully operational decoder (including BG, PEM and CM) which has access to interleaved words from all bit pack units (either on separate buses, as shown in Fig. 24, or via a common bus). If decoder 2504 has selected an interleaved word from one of the bit pack units, that word is transferred to the code stream. Since the decoder on the receiving side requests the data in the same order as the identical snoop decoder, the interleaved words are transmitted in the correct order.

An encoder with a Snooper decoder can be done in half Duplex system will be attractive because the Snooper decoder also works as a normal decoder can be used. An advantage that This Snooper decoder solution is applicability regarding  of a terministic encoder. Alternative solutions that to be discussed below without dependency on a Snooper decoder use simpler models of the Deco dierers to reduce hardware costs. For the decode rer, which decode several code words in the same clock cycle ren, modeling the decoder with less hardware as a decoder itself it may not be possible to use what a Snooper decoder. As below is written exist for decoders, which are mostly only one Decode code word per cycle, simpler models.

Another technique to collect data for pipeline-type De reorder coding systems, mostly one code word per clock cycle decode are based on the fact that the only one Information needed to model the decoder requirements for encoded data is needed, is the order of the Know code words (taking all code words into consideration hen, and not the code words for each encoded data current regardless of this). If a timestamp each code word is assigned when it is the run count reordering sets until what bit-packed nested word the the oldest time stamp assigned to it has the next one to be issued nested code word.

An exemplary encoder reordering unit is shown in the form of a block diagram in FIG. 25. In Fig. 25, the coding system is the same as that described in Fig. 24, except that time stamp information is obtained for each pass count shuffling unit 2501 A-1. This time stamp information is also forwarded to bit pack units 2502 A-1. Bit pack units 2502 A-n provide nested words on the MUX 2503 and their associated time stamps on the logic 2601 . Logic 2601 creates a control signal on MUX 2503 to select the interleaved word to be delivered into the code stream.

In this embodiment, the Snooper encoder is replaced by a simple comparator, which determines which of the bit pack units 2502 A-n has a code word (or part of a code word) with the oldest time stamp. Such a system appears on the MUX 2503 in the form of several queues with time stamps. Logic 2601 simply chooses between different queues. The logic of each of the units 2503 A-n changes only slightly (from a reordering unit 801 ) to write a timestamp when a run starts. Each reordering unit 2501 A-n is equipped to store the timestamp in the code word memory. Storing timestamps with enough bits to enumerate each code word in the encoded data stream is sufficient, but fewer bits may be used in some embodiments.

The steps associated with having multiple snakes Time stamps used are briefly described below. These steps are the encoder operation. No simplification is intended for cases when a run with the same Codeword both starts and ends. The operations can checked for each coded symbol (although in Pra xis not all tests have to be carried out). Chess words are assumed to be 32 bits in size.

The decoder operations are similar, although the code words do not need to be secured in line. It is still necessary nimble to save the timestamp of the code words in line.

The function of the time stamps explained above is used to store the order information of the code words. An equivalent way of expressing the same concept is to use a single queue for all code words, ie a mixed queue. In the mixed queue system as shown in Fig. 26, a single pass count shuffling unit 2701 is used for all interlaced streams. The reordering unit 2701 generates codeword size and current output values at bit pack units 2502 A-n, which output interleaved words to the MUX 2503 and position information to the logic 2702 , which MUX 2503 signals to output interleaved words as part of the code stream.

The reordering memory stores one for any streams interleaved stream ID for each code word. Everyone nest te Strom has its own head pointer. If a bit pack unit  the corresponding head pointer is used det to retrieve as many code words as are needed to to form a new nested word. This can be a night be in many code word locations to determine what parts of the right stream are. Alternatively, you can this is a look-up in the code word store for additional fields Include the to make a linked list.

Another method of verifying currents in accordance with the invention nest, use a mixed snake with a fixed one Power allocation. This method uses a single wake pointer, as in the case of the mixed snake, so no time brands are required. Likewise, several head pointers are in the previous case, so there’s no overhead, to deliver the data from a very specific stream. To do this to achieve, the assignment of code words is too nested th currents according to the following specification for N currents carried out: A code word M is a current M modulo (mod) N assigned. Nested streams can contain code words from any according to a context subject or a probability class have this method. If the number of currents is a power of two, M mod N can be calculated by some of the heights significant bits are thrown away. For example, the Co word reorder memory can be addressed with 12 bits and there four nested streams are to be used. The night run pointer is 12 bits long, and the two least significant bits identify the encoded stream for the next code word. Four 10-bit head pointers are implicitly each of the four possible combinations of the two least significant bits sen. Both the trailing and the head pointers are as normal binary counters incremented.

In the decoder, the shifter has registers to ver save nested words. The sliding unit disfigures correspondingly aligned coded data in the bit generator. If the bit generator uses some encoded data, infor  he lubricates the sliding unit. The sliding unit presents ord properly nested data from the next Electricity. If the number of encoded data streams is N, the Shifter N-1 clock cycles to get the data used out slide in, and maybe some other nested code word to request before this special nested stream is used again.

The decoder of the invention

The invention has a decoder which real-time Encoder with a limited reorder memory supports. In In one embodiment, the decoder contains reduced memory requirements and a complexity at which a run count for each probability class instead of each context remains intact.

An embodiment of the decoder system of the invention

FIG. 13A illustrates a block diagram of an embodiment of the de-coder hardware system of the invention. In Fig. 13A, the decoder system 1400 displays a FIFO structure 1401 decoder 1402, a memory 1403, and a context model 1404. Decoder 1402 includes multiple decoders. Coded data 1410 is received by FIFO structure 1401 , which outputs the coded data to decoder 1402 . Decoders 1402 are connected to memory 1403 and context model 1404 . The context model 1404 is also connected to the memory 1403 . The decoded data 1411 is output at an output of the context model 1404 .

In system 1400 , encoded data 1410 , which is input to FIFO structure 1401 , is ordered and interleaved. FIFO structure 1401 contains data in the correct order. The currents are delivered to encoder 1402 . Decoders 1402 request these currents in a serial and deterministic order. Although the order in which decoder 1402 requests the encoded data is non-trivial, it is not arbitrary. By ordering the code words in this order in the encoder instead of in the decoder, encoded data can be interleaved in a single stream. In another embodiment, encoded data 1410 may include a single stream of non-interconnected data, with data for each context subject, context class, or probability class appended to the data stream. In this case, the FIFO 1410 is replaced by a memory area 1410 to hold all the decoded data before the data is passed to the decoder 1402 so that the data can be properly segmented.

When the encoded data 1410 is received by the FIFO 1401 , the context model 1404 times determines the current context. In one embodiment, the context model 1404 determines the current context subject based on previous pixels and / or bits. Although not shown, row buffering for context model 1404 may be included. The line buffering creates the necessary data or the form (tem plate), with the context model 1404 specifying the current context subject. For example, if the context model is based on pixel values near the current pixel, row buffering can be used to store the pixel values of those nearby pixels that are used to create the specific context.

Corresponding to the context subject, the decoding system 1400 queries the decoding state from the memory 1403 for the current context subject. In one embodiment, the decoder state reads the probability assessment module (PM) state and the bit generator state. The PEM state determines which code to use to decode new code words. The bit generator state maintains a record of the bits in the current pass. The state is provided on decoders 1402 from memory 1403 in accordance with an address created by context model 1404 . The address accesses a location in memory 1403 which stores the information corresponding to the context model.

Once the decode state for the current context bin has been queried from memory 1403 , system 1400 sets the next recompressed bit and processes the decoder state. Decoders 1402 then decode the new code word and / or update the pass count if necessary. The PEM state is updated as necessary, as is the bit generation state. Decoders 1403 then write the new encoding state to memory 1403 .

FIG. 13B illustrates one embodiment of the invention. In FIG. 14B, the decoder includes shift logic 1431 , bit generator logic 1432 , "new-k" logic 1433 , PEM update logic 1434 , new code word Logic 1435 , PEM state cache logic 1436 , encoding mask logic 1437 , encoding MaxPL, mask and R3 split expansion logic 1438 , decoding logic 1439 , multiplexer 1440, and run count update logic 1441 . Sliding logic 1431 is provided to accept coded data input 1443 and state input 1442 (from memory). The output signal of the shift logic 1431 is also provided as an input to the bit generation logic 1432 , the "new-k" generation logic 1433 and the PEM update logic 1432 . Bit generation logic 1432 is also provided to accept state input 1442 and generates the decoded data output value on the context model. The "new-k" logic 1433 generates an output signal which is applied to an input of the coding mask logic 1437 . The PEM update logic 1434 is also applied to a state input 1432 and it generates the state output signal (on the memory). Status input 1442 is also applied to inputs of re-encode word logic 1435 and PEM status encode logic 1436 . The logic 1436 output is received by expansion logic 1438 . The output of expansion logic 1438 is connected to decode logic 1539 and also to update logic 1441 . The other input to the decoding logic is connected to the output of the encoding mask logic 1437 . The output of decoding logic 1439 is connected to an input of MUX 1440 . The other input of the MUX 1440 is connected to the state input 1442 . The selection input of the MUX 1440 is connected to the output of the new code word logic 1435 . The output of the MUX 1440 , the expansion logic 1438 and the logic 1437 are connected to inputs of the update logic 1441 . The output of logic 1441 is included in the state output to memory.

Shift logic 1431 shifts data from the code stream. Based on the encoded data input and the state input, logic 1432 generates encoded data on the context model. Logic 1433 also uses the inserted data and state input to generate a new value of k. In one embodiment, logic 1431 uses the PEM state and the first bit of encoded data to generate the new value of k. Based on the new k value, logic 1437 generates an RLZ mask for the next code word. The RLZ mask for the next code word is then provided to the decoding logic 1439 and to the updating logic 1441 .

Logic 1434 updates the PEM state. In one embodiment, the PEM state is updated using the present state. The current status is then transferred to the memory. The new code word logic 1431 determines whether a new code word is needed. PEM logic 1436 determined the code for decoding using state input 1442 . The code is entered into the expansion logic 1438, Gene To erzeu the maxima le run length, the current mask and a R3-split value. The logic 1439 decodes the code word to a run count to generate output signal. The MUX 1440 selects either the output signal from the decoding logic 1439 or the status input 1442 at the logic 1441 , which updates the run count.

The decoding system 1400 including the decoder 1430 of the invention operates in a pipeline manner. In one embodiment, the decoding system 1400 of the invention determines context bins, evaluates probabilities, decodes code words, and generates bits for pass count in a pipeline manner, respectively. In one embodiment of the pipeline structure of the decoding system is shown in Fig. 14A. In Fig. 14A is an off guide form the pipelined decoding process of the invention in six with the digits 1 to 6 numbered stages shown.

In the first stage, the current context subject is determined ( 1501 ). In the second stage, after the context compartment has been determined, a memory read-in occurs ( 1402 ), the current decoding state for the context compartment being queried from the memory. As previously stated, the decode state includes the PEM and bit generator states.

In the third stage of the pipeline decoding process of the invention, a decompressed bit is generated ( 1503 ). This makes one bit available on the context model. Two more operations happen during the third stage. The PEM state is converted to a code type ( 1504 ) and it is determined whether a new code word needs to be decoded in the third stage ( 1505 ).

During the fourth stage, the decoding system processes a code word and / or updates the pass count ( 1506 ). Several sub-operations are involved in processing a code word and updating the pass count. For example, a code word is decoded to determine the next pass count, or the pass count is updated for the current codeword ( 1506 ). If necessary, when new code words are decoded, multiple encoded data are interrogated by the input FIFO. Another sub-operation that occurs in the fourth stage is the update of the PEM state ( 1507 ). Finally, in the fourth stage of the decoding pipeline, the new PEM state is used to determine what the runlength zero code word (described later) for the next code is when the pass count of the current code word is zero is ( 1508 ). During the fifth stage of the decoding pipeline of the invention, the decoder state is written ( 1509 ) along with an updated PEM state, and the shifting begins for the next code word ( 1510 ). In the sixth stage, the shifting to the next code word is finished ( 1510 ).

The pipeline coding of the invention actually begins with a decision as to whether to start the decoding process. These Determination is based on whether there is enough data to de to represent the encoder of the invention. If not enough data from If the FIFO is present, the decoding system remains stalled. In another case, the decoding system can get stuck, when decoded data is given to a peripheral device that is unable to view the data from the deco which have been given to record how they are created the. For example, if the decoder makes a delivery to a Video display interface and the video circuit assigned to it intends the video to be too slow so that the decoder is indicated must be stopped in order to be able to obtain a video.

Once the decision has been made, the decoder pro The current context subject is started by the context model determined. In the invention, the current context subject determined by checking the previous data. Such before Data can be stored in line buffers and can data from the current line and / or previous lines included, for example in a context model for a pre given bit. Bits of line buffer (s) can be saved using a Mo dells (template) based on the previous data den, so that the context subject for the current data accordingly is selected accordingly whether the previous checking data for the Model fit. These line buffers contain bit shift registers. A pattern can be used for each bit level of an n bit image  will.

In one embodiment, the context subject is chosen by that an address to a store during the next pipeli ne level is given. The address can be a predetermined one Number of bits, such as 3 bits included, around the bit ne to identify. With the help of three bits, the bit posi tion in pixel data. The shape that uses to determine the context can also be part of the Address. The bits that are used to identify the bit level and the bits that iden the form tify can be combined to one address for one to generate a specific location in the memory, which the Zu status information for the context defined by these bits compartment contains. For example, by using three bits, to determine the bit position in a particular pixel, and by using the previous ten bits in the same position tion in each of the previous pixels in the model is a 13 bit Context address are generated.

The memory (e.g. RAM) is accessed with the aid of the address which was generated by means of the context model in order to obtain the status information. The state contains the PEM state. The PEM state includes the current probability estimate. Because more than one state uses the same code, the PEM state includes a probability class or code determination, but not an index in a table, such as the table shown in FIG. 4. If a table such as that used in Fig. 4, the PEM state creates the most likely symbol (MPS) as a means to identify whether the current PEM state is on the positive or negative side of the table. The bit generation state may include the count and an indication of whether an LPS is present. In one embodiment, the MPS value for the current pass is also included to decode the next code word. In the invention, the bit generator state is stored in memory in order to reduce the space required for the flow counter. If the space cost in the system is low for each context, the bit generation state need not be stored in memory.

Once the fourth stage has been completed, a new one will be created Bit generator state and a PEM state in the memory wrote. Likewise, in the fifth stage, the encoded data current shifted with the next code word. The sliding operation is finished in the sixth stage.

FIG. 13C shows a block diagram of an embodiment of a FIFO structure 1401 of the invention, by means of which an interleaved word buffering for two decoders is explained. A number of decoders can be supported using the teachings of the invention. As shown, the data entered and the FIFO are wide enough to hold two interleaved words. FIFO 1401 has a FIFO 1460 , registers 1461 and 1462 , MUXs 1463 and 1464 and a control block 1465 . The two code words entered are used as the input nested words. Inputs on MUX 1463 are connected to the outputs of registers 1461 and 1462 . Control block 1465 is provided to provide control signals to FIFO 1460 , registers 1461 and 1462 and to MUXs 1463 and 1464 . Interlaced words are the output data (output data value 1 and 2) which are provided on two decoders. Each decoder uses a request signal to indicate that the current word has been used and that a new word is needed next. The request signals from the decoders are applied to inputs of control block 1465 . Control block 1465 also issues a FIFO request signal to request more data from memory.

Initially, the FIFO and registers 1461 and 1462 are filled with data and a valid flip-flop is set in the control unit 1465 . Whenever a request comes in, control block 1465 generates the data according to the logic shown in Table 16.

Table 16

Fig. 14B illustrates another conceptual view of the decoder of the invention. In Fig. 14B, (encoded) variable length data is input to an encoder. The decoder outputs (decoded) data of fixed length. The output data is coupled as a delayed feedback which is received as an input to the decoder. In the decoder of the invention, variable length shifting used in decoding is based on decoded data that is available after a certain delay. The feedback delay does not reduce the throughput in the delay tolerant decoders.

The input variable length data is divided into nested words of fixed length, as described in connection with Fig. 3 be. The decoder uses the fixed length words as described below in connection with FIG. 15. The decoder and delay models a pipeline decoder, as described in connection with FIGS. 14 and 32, or several parallel decoders, as described in connection with FIGS. 1A to 1D. Thus, the invention provides a delay tolerant decoder. The delay tolerant decoders of the invention enable parallel handling of variable length data.

Conventional decoders (e.g. Huffman decoders) are not always tolerant of delays. Information from a decode all previous code words is determined, is required to perform the variable length shift that is necessary is to decode the next code word. On the other hand creates the invention delay-tolerant decoders.

Moving in the decoding system

The decoder of the invention provides shift logic to the nested words in the correct bit generator for a de to postpone coding. The displacement unit of the invention does not require a special type of start character "context" ("by context ") or" probability "-" Pa parallelism. An encoder is assumed, which is a code word M assigns the current M mod N (M% N in the C language), where N the number of streams is. In the invention, encoded data from the current stream until a code word is requested is changed. Only then will the data be transferred to the next stream switches.

Figure 15 illustrates one embodiment of the shift unit for the decoder of the invention. The slide unit 1600 is designed for four data streams. This allows four clock cycles for each shift operation. The interleaved words have 16 bits and the longest code word has 13 bits. In Fig. 15, the shift unit 1600 has four registers 1601 to 1604 which are provided to receive inputs from the interleaved coded data. The outputs of the respective registers 1601 to 1604 are provided as input signals to MUX 1605 . The output of MUX 1605 is connected to the input of a barrel or barrel sliding unit 1606 . The output value of the sliding unit 1606 is also provided as an input value on a register 1706 , on MUX & registers 1608 to 1610 and a size unit 1611 . The output of the size unit 1611 is connected to a battery mulator 1612 . An output of the accumulator 1612 is fed back to the sliding unit 1606 . An output of register 1607 is provided as an input to MUX & register 1608 . An output from MUX & Register 1608 is provided as an input to MUX & Register 1309 . An output from MUX & Register is provided as an input to MUX & Register 1610 . The output value from MUX & Register 1610 is the aligned encoded data value. In one embodiment, the registers 1601 to 1604 are 16 bit registers, the shift unit 1606 is a 16 bit to 13 bit shift unit and the accumulator 1612 is a 4 bit accumulator.

Registers 1601 through 1604 receive 16 bit words from the FIFO and input them to shift unit 1601 . At least 32 bits of the uncoded data are always seen on the shift unit 1606 . The four registers 1601 through 1604 are initialized to begin with two 16 bit words of encoded data. Thus there is always at least one new code word that is available for every stream.

For R codes, code word size unit 1611 determines whether there is a "0" or "1N" code word, and if it is a "1N" code word, how many bits after the "1" are part of the current code word . The size unit, which is provided for the same function, has already been described in connection with FIG. 11. For other codes, determining the size of a code word is known.

The shift unit 1600 has a FIFO, which consists of four registers, three of which have multiplex inputs. Each register of registers 1607 through 1610 holds at least one code word so that the width of the registers and the multiplexers is 13 bits to accommodate the longest possible code word. Each register also has an associated control flip-flop (not shown) that indicates when a particular register contains a code word or when it is waiting for shift unit 1606 to create a code word.

The FIFO is never empty. Only one word can be used per clock cycle, and only one code word can be shifted per clock cycle. The delay to perform the move is compensated for because the system starts four code words beforehand. When each codeword is shifted to be aligned coded data output, the other codewords in registers 1607 through 1610 are shifted down. If the codeword on the left is stored in the FIFO in the register 1620 , the shift unit 1606 causes code words from registers 1601 to 1604 to be read out via the MUX 1605 in order to fill the registers 1607 to 1609 . The FIFO can be designed accordingly to fill the register 1607 again with the next code word as soon as its code word has been moved into the register 1608 .

The shift unit 1606 , a codeword size calculator 1611 and an accumulator selection unit 1612 handle variable length shifting. The accumulator 1216 has four registers, one for each encoded data stream, which contain the alignment of the current code word for each data stream. The accumulator gate 1214 is a 4 bit accumulator that is used to control the sliding unit 1606 . The accumulator 1612 increases its value by the value that has been entered by the code word size unit 1611 . If the accumulator 1612 overflows (e.g. each time the shift count is 16 or greater), who shifted the registers 1601 to 1604 under clock control. Any other 16 bit shift causes a new 32 bit word to be requested from the FIFO. The input value at the accumulator 1611 is the size d 62981 00070 552 001000280000000200012000285916287000040 0002019536401 00004 62862es code word, which is determined by the current code and the first one or the first two bits of the current code word. In some embodiments, the registers must be initialized 1601 to 1604 with the encoded data who, before decoding may begin.

When a code word is requested by the system, the registers in the FIFO are clocked so that code words are moved in the direction of the output. When shift unit 1601 is ready to deliver a new code word, it is multiplexed into the first empty register in the FIFO.

In this embodiment, the next code word signal is received in the bit generator before the decision to switch currents is made. If the next codeword signal cannot be guaranteed to be received by the bit generator prior to deciding to switch currents, a predictive system, such as one shown in Figure 15B, can be used. In Fig. 15B is a shift register 1620, in which a look ahead is applied, shown ei nes in block diagram form. The shift unit 1620 has a shift unit 1600 , which generates output signals of the current encoded data and the next encoded data. The current coded data are applied to an input of a code word preprocessing logic unit 1621 and to an input of a code word processing unit 1622 . The next encoded data is applied to an input of a code word preprocessing logic unit 1622 . Outputs from the two logic units 1621 and 1622 are applied to inputs of a MUX 1623 . The output of MUX 1623 is connected to another input of code word processing logic 1624 .

The logic using the code word is divided into two parts, a code word preprocessing logic and a code word processing logic. Two identical pipeline preprocessing units 1621 and 1622 operate before the nested stream can be shifted. One of the preprocessing units 1621 and 1622 generates the correct information when the power is switched, and the other generates the information when the power is not switched. When the power is switched, the output signal at the correct code word preprocessing is multiplexed from the multiplexer 1623 to the code word processing logic 1624 , which ends the operation with the correct code word.

Off-chip memory and context model

In one embodiment, it may be desirable to have many chips to be used for external storage or external context models. In these embodiments, it is desirable to use the delay between generating a bit and having the Decrease where available bits on the context model can be used with multiple integrated circuits.

Fig. 16 shows a block diagram of an embodiment of a Sy stems both with an external context model chip 1701 and a Codiererchip 1702 of a memory for each context. Only the units that are relevant for the context model in the coding chip are shown here; Here, the coding chip 1702 contains a bit generation, a probability evaluation, etc. In FIG. 16, the coding chip 1702 has a zero-order context model 1703 , context models 1704 and 1705 , a selection logic 1706 , a memory controller 1707 and a memory 1708 . The zero order context model 1703 and the context models 1704 and 1705 generate output signals which are applied to inputs of the selection logic 1706 . Another output of the selection logic 1706 is connected to an output of the external context model chip 1701 . The output of logic 1706 is connected to an input of memory 1708 . An output of the memory controller 1707 is also connected to an input of the memory 1708 .

Via the selection logic 1706 , either an external context model or an internal context model (e.g. the zero order context model 1703 , the 1704 and 1705 context models) can be used. Via the selection logic 1706 , the internal zero order part of the context model 1703 can be used even if the external context model 1701 is used. The zero order context model 1703 creates one bit or more, while the external chips 1701 context model generates the rest. For example, the immediately preceding bits can be fed back and found again by the context model 1703 , while previous bits go into the external context model 1701 . In this way, time-critical information remains on the chip. This precludes an off-chip communication delay for bits that have just been generated.

Fig. 17 is a block diagram of a system with an external context model, an external memory 1803 and an encoder chip 1802nd In Fig. 17, some memory address lines from the external context model 1801 are driven, while other "zero-order" are ert angesteu in the encoder chip 1802 by the context model. That is, the context from the immediately preceding coding cycle is driven by the context model of the zero order. This allows the encoding chip to provide context information from the immediately preceding cycle with a minimal transmission delay. The context model chip 1802 precedes the rest of the context information, which uses bits that have only been decoded in the previous cycle, and therefore takes into account a transmission delay. In many cases the context information from the immediately preceding cycle is a zero order Markov state and the context information from others in the previous cycle is a higher order Markov state. The embodiment shown in FIG. 17 eliminates a transmission delay that is inherent in a zero order execution chip 1802 in the external context model. However, there may still be a context bin determination with a bit generated delay due to decode chip 1802 and memory 1803 .

It should be noted that another memory architecture ver could be applied. For example, a chip with the context model and a memory on a chip and the Co used on another chip. Likewise, a System a coding chip with an internal memory, which for some contexts is used and external storage is on indicate which is used for other contexts.

Bit generators with one memory

Figure 18 shows a decoder with a pipeline bit generator with memory. In Fig. 18, decoder 1900 includes context model 1901 , memory 1902 , PEM state coding block 1903 , pipeline bit generator 1905 , memory 1904, and shift unit 1906 . The input of the context model 1901 has the decoded data from the pipeline bit stream generator 1905 . The coded data is received at the inputs of the sliding unit 1906 . The output of the context model 1901 is connected to an input at the memory 1902 . The output of the memory 1902 is connected to the PEM block 1903 . The output signal of PEM block 1903 and the aligned encoded data at the output of shift unit 1906 are applied to inputs of bit generator 1905 . Memory 1904 is also connected to bit generator 1905 by a bidirectional bus, and the output of bit generator 1905 is the decoded data.

The context model 1904 delivers a context subject correspondingly coded data at its inputs. The context model is used as an address based on the context bin for accessing the memory 1902 to obtain a probability state. The probability state is obtained from the PEM module 1903 , which generates the probability class according to the probability state. The probability class is then used as an address to access memory 1904 to obtain the run count; this is then used by bit generator 1905 to generate the decoded data.

In one embodiment, memory 1902 has (1024 x 7 bits) memory (where 1024 is the number of different contexts) while memory 1404 has (25 x 14 bits) memory (where 25 is the number of different run counts ).

Since bit generator states (pass counts, etc.), probability classes, not contextual subjects, exist an additional pipeline delay before a bit on the con text model is available. Because updating a Bitgenera gate state takes several clock cycles (the bit generator closes state memory causes a delay) are several bit genes rator states used for each speed class. If For example, if the pipeline is six clock cycles, then the Bit generator state memory six entries per probable class. The counter is used to ensure the correct memory selection. Even with multiple entries per truth Probability class is usually the size of the memory less than the number of contexts. The store can either with several banks from SRAM or with a multi-tour regi must be executed.

Because a pass count is assigned to multiple contexts one embodiment, the probability evaluator Expand the state of one or more contexts. In In one embodiment, the PEM state of context, wel cher causes a continuous end, updated. Instead of reading Modify or write a pass count a pass can be done before it can be read again  count value can be used again as soon as the modification is canceled is closed.

Fig. 31 illustrates a timing diagram of a Decodiero peration in an embodiment of the invention. In Fig. 32, a decoding operation is described with three cycles. Signal names are listed in the left-hand column of the timing diagram. The validity of a signal during any cycle is indicated by a dash during the cycle (or part of it). In certain cases, the unit or logic that responds to generating the signal or applying the valid signal is shown in a block shown in dashed lines in the valid signal display. In each case, the specific elements and units that are shown are also provided, if provided.

Part of the signal that is in another cycle stretches, shows the validity of the signal only for this time cut, in which the signal is shown, which is in the extends another cycle. Certain signals are shown which are valid separately for more than one cycle. An exem Plar of it is the Temp-through counting signal, which at one Place is valid at the end of the second cycle, and then again during the third cycle. This indicates that the signal is only on At the end of the cycle. A list of dependencies ten is also shown in Table 17 below, which is the Dependencies for the same or previous clock cycle on that represents the instant of the signal valid specified.  

Table 17

Implicit signaling

In some embodiments, the decoder in the endli Model the reorder buffer of the encoder. In an out This modeling is implemented with an implicit signa lize achieved. As before with regard to the encoder is explained when a code word is started in the encoder will, space in the corresponding buffer for the code word in the Reserved order in which the code words on the channel should be placed. If the last place in a buffer is reserved for a new code word, then some code words placed in the compressed bitstream whether they are full have been constantly determined or not.

If a partial code word needs to be terminated, a code word, which is short and the correct one received symbols specified. For example, in one R coding system, if necessary, a code word for one Row of 100 MPSs in a pass code with 128 maximum To complete run lengths prematurely, the code word for 128 MPSs are used because this correctly matches the first 100 symbols specified.

On the other hand, a code word that specifies 100 MPSs can be that follows an LPS can be used. When the code word completes it is removed from the reorder buffer and added to the code stream. This allows you to complete beforehand constant code words are placed in the code stream. When a Force the completion of a partial code word too removing a code word from the full buffer, then coding may continue. If a buffer is still full then the next code word must be completed and be added to the code stream. This process continues until the buffer that was full is no longer full. Of the Decoder can model the encoder for implicit signaling a counter for each bit generator state information tion storage location is used.  

In one embodiment, each pass counter (probability class in this example) a counter which contains the same size as the head or trailing counters in the encoders (e.g. 6 bits). Every time a new run is started is (a new code word is queried), the corresponding The corresponding count value is loaded with the size of the code word memory. Each whenever a run is started (a new code word from all counters are decremented. Some toughness The one who reaches zero causes the corresponding one Pass count is deleted (and the existing LPS ge is deleted).

Signaling options for finite memory

Real time coding in the invention requires that the deco ters runs of MPSs that are not addressed by an LPS for and which are not the maximum run length. This happens when the encoder starts to run MPSs, but not has a sufficiently limited reorder space to wait for the run is completed. This condition requires that is to decode a new code word, and next time this Context subject is used; this condition must go to the decoder be signaled. Three possible ways to get the decoder modify are described below.

If the buffer is full, the pass count for that Context subject or probability class, that is forced to be reset. To make this effective is to save the context subject or the Probability class useful in the code word store. There this is only required for runs that have not yet been added orderly codeword, the memory which is used for storage chern of the code word is used to be shared. In some system, instead of extracting an incomplete word force bits into the context / probability class of (or any) code word that is not forced in the buffer is cleared when the buffer is full. The decoder provides  this is fixed and uses the corresponding (wrong) context subject or the corresponding probability class.

In the case of in-stream signaling, code words are used to to signal this to the decoder. In one embodiment the R2 (k) and R3 (k) code definitions are changed to not- to get maximum run lengths of MPS on which not an LPS follows. This can be done by assigning a bit to the Codeword is added that has the lowest probability should occur. This enables a clear deco adjustable prefix for the non-maximum run length counts. Table 18 shows a replacement for R2 (2) codes, which is an im Current signaling allowed. The disadvantages of this method are that the R code decoding logic needs to be changed and that there are compression costs every time the code word with the least likelihood occurs.

Table 18

In some embodiments, the decoder implicitly signaling with the help of time stamps. A counter keeps track of the current "time" by incrementing each sometimes when a code word is required. However, if a co dewort is started, the current "time" in a Co  saved memory. After the first time If a code word is used, the corresponding one is saved "Time" value plus the size of the encoder reorder buffer with compared to the current "time". If the current "time" is greater an implicit signal is generated so that a new code word is required. Hence the limited reorganization game simulated in the encoder. In one embodiment enough bits are used for "time" values so that all code words can be enumerated.

To reduce the memory required, the number of bits used for the time stamps on one Kept to a minimum. If the timestamps a small number of bits use so that time values are used again, must be used be made sure that all old time stamps are noted before the Reuse times counter starts. Here N is the size the number of address bits for queue or the bit generator close stand memory. Time stamps with (N + 1) bits can be used will. The bit generator state memory must have multiple accesses have maybe two reads and two writes per deco dated bit. A counter is used to cycle the bit genes to go through rator state memory by once for each decoded bit is incremented. A storage location that too old is deleted, so that a new code word is queried will when it is needed in the future. This guarantees that all time stamps are checked before any time value like that is used.

If the bit generator state memory is smaller than the queue the count rate (the timestamp counter) and the required memory bandwidth can be reduced, because: each timestamp (one per bit generator state memory) only one times must be checked with regard to the number of cycles required are necessary to use the whole snake. Also one can Store the timestamps in another memory as required Reduce the memory bandwidth. In a system what "0" code  words used for partial runs need time stamps not to be checked for "1N" code words. In a system that "1N" code words used for partial runs is just that Check the time stamp before an LPS is generated.

In some embodiments, implicit signaling performed with a queue during decoding. The Process may be useful in a half duplex system which is the hardware for coding during decoding is available. The effect of the snake is mostly the same like during coding. When a new code word is requested the index is placed in the queue and is considered invalid marked. When the data is completed by a code word the queue entry is marked as valid. If there were taken out of line to make room for new codewords ter will create if the extracted data as un are marked as valid, the bit generator status information from deleted this index from. This delete operation may require that the bit generator state memory has an additional write operation can support.

In contrast, explicit signaling divides a buffer overflow Form of compressed data with. An example of this is a to have an additional context subject that is once for every normal Context box decoding or used once for each code word that is decoded. Bits resulting from the additional con Text decoded indicate if the state is up occurs in which a new code word is required, and new code word must de for the corresponding normal context subject be encoded. In this case, the code words for this correct context to be rearranged. Because the use this context, a function of something known about the Reordering unit (usually it is only once for each of the codeword used), the memory required is to rearrange the additional context, limited or in be modeled explicitly. Likewise, the possible codes for  limit this additional context.

Implicit signaling models the limited code rer buffer when decoded to produce a signal that indicates that a new code word has to be decoded. In a Embodiment will get a timestamp for each context. In one embodiment, the reorder buffer becomes finer Size of the encoder modeled directly. Half a duplex stem, since the encoder reordering circuit during deco which is available, these are used to transmit the signals to generate for the decoder.

How exactly implicit signaling is achieved depends on the details of how the encoder fully buffers recognizes and treats. In a mixed system Fixed assignment snake can use multiple Allow pointers to choose what "buffer full" means tet. With a corresponding design of the decoder, a corresponding model can be dimensioned.

An encoder operation will now be described, and a model for use by the encoder in a mixed queue with a fixed current allocation, parallel to a probability system. For this example, the reorder buffer should have 256 digits, four interleaving streams should be used, and each word should be 16 bits. If the buffer contains 256 entries, an entry must be submitted to a bit packer (e.g., a bit pack unit) before the entry for the 257th code word can be placed in the queue. If necessary, entries can be forced out earlier. In some systems, removing the first entry in the buffer requires removing enough bits to complete an entire scrambled code word. If 1-bit code words are therefore possible, removing a code word 0 can also remove code words 4, 8, 12,. . . 52, 56, 60 require for interleaved 16 bit words. To ensure that all of these buffer entries have valid entries, enforcing an entry to be filled, since the memory is full, can be performed at addresses 64, 192 from the point at which a new word is entered (256-16 × 4 = 192).

In the decoder there is a counter for every probability speed. When a new code word is used to make a pass to start, the counter is loaded with 192. If to any Time a new code word at any probability all counters are decremented. If any When counter reaches zero, the run length for this probability set to zero (and the existing LPS flag is set deletes).

It can be advantageous to have several RAM banks (one multi-speed Memory, a simulation with a fast memory, etc.) too use one bank for each encoded data stream. This allows all bit pack units to record data at the same time men, so that a reading of several code words for a whole be agreed current did not hinder reading at other currents.

In other systems, several bit pack units have to be used for a single memory based on a code word order decide how it is stored in the buffer. In these Systems can remove an application from a buffer Do not complete the nested word. Every bit unit usually takes a fraction of a nested word as a result of. Each bit pack unit takes at least one number Bits that are equal to the shortest code word lengths (e.g. 1 bit) and at most a number of bits that are equal to the largest Co word length are (e.g. 13 bits). Nested words can not be submitted until the are complete and must be in in the order of initialization. In this case a bit pack unit for buffering 13 can be nested Have words; this is the maximum number of nested ones Words that are completed with maximum length codewords  that can while another stream is chess pending has a word that contains code words of minimal length.

A system in which each code word requires two writes and one read to memory may be less desirable for hardware execution than a system which performs two writes and two reads. If so desired for the exemplary four stream system, bit pack units 1 and 2 could share a memory read cycle and bit pack units 1 and 3 together use another read cycle (or any other combination). Although this would not reduce the amount of buffering required, it would allow a higher transfer rate in the bit packer. This can allow the bit pack units to better utilize the capacity of the encoded data channel.

Systems with a fixed size memory

One advantage of a system that has multiple bit generator states has a high probability class is that the Sy can support lossy coding when a memory Fixed size overflows. This can be the case with image compression usable for a frame buffer and other applications that only store a limited amount of encoded data chern.

For systems with a fixed size memory, the multiple ren bit generator states for each probability assigned to part of the data. For example, each eight states of a very specific bit level for eight bit data be assigned to. In this case, a pushing unit is used by everyone Part of the data assigned, unlike sliding units, which successively generate the next code word. It should be noted that the data does not have to be divided by a bit level. Likewise, no interleaving is carried out in the encoder; ever the part of the data is simply bit packed. A memory will assigned to every part of the data.  

Memory management for encoded data is for systems which stores all data in a fixed size memory chern, and for systems that data to a channel with a maxi times allowed bandwidth. In these two systems is a moderate deterioration in a lossy System wanted. Different data streams are used for data used different importance so that few important Streams can be stored or not transmitted if insufficient storage capacity or bandwidth is available.

If memory is used, the encoded data must be stored so that it can be accessed so that less important data streams can be discarded without losing the ability to decode important data streams. Because encoded data is of variable length , dynamic memory allocation can be used. Fig. 30 shows at play, a dynamic memory allocation unit for three coded streams. A register file 3100 (or other memory) holds a pointer for each data stream plus another pointer to indicate the next free location. Memory 3101 is divided into fixed size pages.

Initially, each pointer that is associated with a stream points to the beginning of a memory page, and the free pointer to the next available memory page. Coded data from a whole certain electricity are stored in a storage location that is addressed by the corresponding pointer. The pointer will then incremented to the next storage location.

When the pointer reaches the maximum for the current page, the following results. The address of the start of the next free page (which is stored in the free pointer) is marked with the current page. (Either part of the coded Data storage or a separate memory or a register file could be used). The current pointer turns to  the next free page is set and then incremented. These Actions assign a new memory page to a specific one Power and create connections that the assignment order ge can be determined during decoding.

When all the pages in the memory are used and there is more da out of a data stream, one of three things can be done will. In all three cases, a memory that is the least most important data stream is assigned to an important one ren data stream and there will be no more data of the least important data stream.

First, it will just be the site that is least of the least main stream used, assigned to the more important data. There the typical entropy encoder be internal state information use, all of the least important data is lost, previously saved on this page.

Second, the side that is of the least important When electricity is used, it simply becomes the more important data stream assigned. Unlike the previous case, the Zei put on the bottom of the page and since more important data the page will be written, the corresponding pointer will de incremented. This has the advantage that the least important data at the top of the page can be obtained if the important data stream does not require the entire page.

Third, instead of the current page with the least important To relocate data, either side of the least most important data reassigned. This makes it necessary Lich that the encoded data for all pages independently are to be coded otherwise, whereby the compression achieved ver is wrestled. This also requires that the uncoder data that corresponds to the start / start of all pages be certified. Because one of the least important data is gone can be thrown is greater flexibility in terms  for a reasonable deterioration in lossy Co available. The third alternative can in particular be attractive to a system that has a fixed compression rate above Areas of the image reached. A specified number of Memory pages can be assigned to an area of the image. Whether less important data is retained or not can depend on the compression in the particular area he is enough. (The memory allocated to an area cannot be fully exploited if a lossless Compression is required that is less than the associated one Amount of memory required). Reaching a firm compress Sionsrate in an area of the image can be any Zu reached to support the image area.

The ability to get data into each side from both ends write can be used to represent the whole in the system make better use of available storage space. If all sides too are ordered, a page that has sufficient free space End has to be allocated for use from the end. The ability to use both ends of a page must be compared Be balanced over the cost, track to the spot too hold that the two types of data match (this is difficult in case one of the data types was not important and a could be written about it).

Now consider a system in which data in one Channel transmitted instead of being stored in a memory. Fixed size memory pages are used, but only one side per stream needed. (Or maybe two if they are According to the ping-pong method, buffering is required to create for the channel so that while the one described the other is read out for output). When a Memory page is full, it is transferred to the channel, and the location can be used again as soon as the page is transferred. In some use cases, the page size of the memory the size of data packets that ver in the channel  have been used, or a multiple of a packet size.

In some transmission systems, for example ATM (asynchronous Transfer mode) can be assigned to priority packages. ATM has two priority levels, a priority and a secondary ren. Secondary packets are only transmitted if sufficient Bandwidth is available. A threshold can be used to determine which streams are priority and which are secondary. Another method would be one To use threshold on the encoder so as not to receive currents which were less important than a threshold.

Separate bit generators for each code

Figure 19 is a block diagram of a system with separate bit generators for each code. In Fig. 19 in 2000, the decoding system, a context model 2001, a memory 2002, a PEM to stand-coding block 2003, a decoder 2004, bit generators 2005 A-n and a disk unit for 2006. The output of the context model 2001 is connected to an input of the memory 2002 . The output of the memory 2002 is connected to an input of the PEM block 2003 . The output of block 2003 is connected to an input of decoder 2004 . The output of the decoder 2004 is provided as an enable for bit generators 2005 A-n. Bit generators 2005 A-n are provided to receive coded data which have been output by the shift unit 2006 .

The context model 2001 , the memory 2002 and the PEM block 2003 work similarly to their counterparts in FIG. 18. The context model 2001 creates a context subject. The memory 2002 outputs a probability state based on the context subject. The probability state is recorded by the PEM block 2003 , which generates a probability class for each probability state. The decoder 2004 enables one of the bit generators 2005 A-n to encode the probability class. (The decoder 2004 is an M to 2 ^M -De coding circuit which corresponds to a (74 × 138 3: 8) decoder which is known - and is not an entropy coding decoder). Since each code has a separate bit generator, some bit generators can use codes and not R codes. In particular, a code for probabilities close to 60% can be used to better cover the probability space between R2 (0) and R2 (1). For example, Table 19 shows such a code.

Table 19

To achieve the desired speed, may require If necessary, pre-decoding one or more bits be performed to guarantee that decoded data are quickly available. In some embodiments, to avoid the need for a large pass count to update every clock cycle, both the codeword deco dieren as well as the pass count for long codes.

The bit generator for R2 (0) codes is straightforward. A code word is required every time a bit is requested. The generated bit is simply the code word (XORed with the MPS).

Codes for short run lengths, e.g. R2 (1), R3 (1), R2 (2) and R3 (2) are treated in the following manner. All bits in a code word are decoded and in a state device  stored, which is a small counter (1, 2 or 3 bits) and an LPS bit. The counter and the LPS bit operate as an R code Decoder.

For longer codes, such as R2 (k) and R3 (k) for k <2, bit generators are divided into two units, as shown in FIG. 20. In Fig. 20 a Bitgeneratorstruktur for R2 (k) code is shown for k <2, with a unit 2101 for a short pass, and a unit 2102 for a long run. Although the structure is used for R2 (k <2), its operation is similar to that of R3 (k <2) codes (and is known to those skilled in the art).

The short pass unit 2101 is provided to generate an enable signal and a code word [0. . . 2] as input values to the bit generator and a signal from "all zeros" and a count zero signal (indicating a zero count), both of which come from the long pass unit 2102 . Accordingly, at these inputs, unit 2101 outputs a decoded bit and an indication of the next signal, thereby signaling that a new code word is required. Unit 2101 also generates a count enable signal, a counter load signal, and a "count max" signal to unit 2102 for a long run. Unit 2102 is also provided to convert code words [k. . . 3] as an input to the bit generator.

Unit 2102 handles runs up to a length of 4 and corresponds to an R2 (2) bit generator. In one embodiment, unit 2101 is the same for all R2 (k <2) codes. The purpose of the long pass unit 2102 is to determine when to deliver the last 1 to 4 bits of the pass. Unit 2102 has inputs, AND logic, and a counter, which vary in size with k.

An embodiment of the count unit 2102 for a long run is shown in FIG. 21. In Fig. 21, unit 2102 has AND logic 2201 which is provided to code word [k. . . 3], and outputs a "all ones" signal as a logical 1 when all bits in the code word are 1 's, thereby indicating that the current code word is a 1N code word and that the pass count is less than 4 . A non-logic 2202 is also provided to receive the code word and to invert it. The output of non-logic 2202 is connected to an input of a bit counter 2203 . The bit counter 2203 and the count value enable signal, the counter load signal and the "count value max" signal. In accordance with the input signals, the bit counter 2203 generates a "count zero" signal.

In one embodiment, counter 2003 is a k-2 bit counter and is used to break long run counts into runs of four MPSs and possibly some remainder. The count enable signal indicates that four MPSs have been delivered and the counter should be decremated. The counter load signal is used when "1N" code words are decoded and the counter is to be loaded with the complement of code word bits k by 3. The signal "count value max." is used when "0" code words are decoded and loads the counter with the maximum value. The output signal "count value zero" indicates when the counter is zero.

An embodiment of the short pass counting unit 2102 is shown in FIG. 22. Fig. 22 contains the Zählein integral of a control module 2301, a 2-bit counter 2302 and a 3-bit counter 2303rd The control module 2301 receives the enable signal (the code word [0... 2], and all ones and signals "count zero" from the long pass count unit. The 2 bit counter is used to count four bit passes of MPSs An AR (2) counter and an LPS bit (3 bits in total) 2303 are used to generate the 1 to 4 bits at the end of a run, and the enable input signal indicates that a bit at the bit output should be generated The "count zero" input signal, if not asserted, indicates that a pass of four MPSs should be issued, however, when the MPS counter 2302 reaches zero If the "count zero" input signal is asserted, either the R2 (2) counter, the LPS, is used or a new code word is decoded and the next output signal is asserted.

When the new code word is decoded, the actions performed are determined by the code word input. If the input is a "0" code word, the MPS counter 2302 is used and the output "Count value max." is asserted. For "1N" code words, the first three bits of the code word are loaded into the R282) counter and LPS 2303 , and the counter load output signal is asserted. If all entered 1's are asserted, then the R2 (2) counter and LPS 2303 are used to generate bits. Otherwise, the MPS counter is used until the zero count input signal is asserted.

From a system perspective, the number of Co small for the system to work well, usually 25 or less. The size of the multiplexer used for bit and the next code word related outputs are needed, and the Decoder to release a specific bit generator must be limited for quick surgery. The Co deword from the sliding unit not too high for one high fast operation.

Separate bit generators for each code allow a pipeli ne processing. If all code words consist of at least three bits could result in code word processing in two Cycles instead of being made in a pipeline. This can double the speed of the decoder if the bit counter is a limiting part of the system wa One way to achieve this is to rely on the  Code word with a run length of zero (the code word shows exactly one LPS on) is followed by a bit, which is the next uncoded bit. These could and would be called RN (k) +1 codes always code at least two bits. R2 (0) code words and a lot easily need some of the other short code words for one appropriate speed not connected to a pipeline to be.

Separate bit generators are even suitable for use in connection with an implicit signaling. An implicit signaling for coding with a finite memory cher can be achieved in the following ways. Any bit generator has a counter that is the size of a queue address for example, has 9 bits if a queue is 512 in size is used. Every time a new code word of one bit generator is used, the counter with the maximum value loaded. Whenever a bit generator requests a code word, the counters are decremented for all bit generators. Each when a counter reaches zero, the corresponding bitge nerator state cleared (for example, the MPS counter, the R2 (2) counter and LPS as well as the counter for a long through run count are deleted). Since deletion can occur even if a very specific bit generator is not released there are no problems with used up counts.

Memory initialization for each context subject

In cases where a memory is true for each context subject probability evaluation information, an additional memory bandwidth required to the decoder (e.g. the memory) to initialize very quickly. A quick one Initializing the decoder can be a problem if the Decoder has many contexts and they all need to be deleted sen. If the decoder has many contexts (1K or more) under supports and the memory could not be deleted globally an unacceptable large number of clock cycles may be required to to clear the memory.  

To quickly delete contexts, use some execution form the invention an additional bit, which here as the ini tialized status bit is referred to that with any context is saved. As a result, an additional bit in the PEM state (e.g. 8 bits) saved for each context.

The memory for each context bin and the initialization control logic are shown in FIG. 23. In Fig. 23, a text memory 2401 Kon is connected to a register 2402nd In one embodiment, register 2402 has a one bit register that indicates the current correct state for the initialized state compartment. Register 2402 is connected to an input of XOR logic 2403 . Another input on XOR logic 2403 is stored with an output connected to 2401. The output of the XOR logic 2403 is the valid signal and connected to an input of a control logic 2404 . Other inputs to control logic 2404 are connected to the output of counter 2405 and the next context bin signal. The output of control logic 2404 is connected to dial inputs from MUXs 2406 to 2407 and to an input of a counter 2405 . Another output of control logic 2404 is connected to the dial input of MUX 2408 . The inputs of MUX 2406 are connected to the output of a counter 2405 and the context tray display. The output of MUX 2406 is connected to memory 2401 . The inputs of MUX 2407 are connected to the new PEM status and zero. The output of MUX 2407 is connected to an input of memory 2401 and the initial PEM state is connected to the input of MUX 2408 . The output of MUX 2408 is the PEM state output signal.

The value in register 2402 completes every decode operation (ie, every set, not every decoded bit). The XOR logic 2403 compares the validity of the accessed location with the register value to determine whether the accessed location is valid for this decoding operation. This is accomplished using XOR logic 2403 to match the initialized status bit to the correct status in register 2402 . If data in memory 2401 is not valid, control logic 2404 causes the data to be ignored in the state at the coding logic and the initial PEM state to be used instead. This is achieved with the help of MUX 2403 . When a new PEM state is written into memory, the initialized bit is brought up to the current value of the register so that it is considered valid when it is accessed again.

Each context bin memory entry must be an initialized state bit that is brought up to the current value of the register before another decoding operation can begin. Counter 2405 cycles through all of the memory locations to ensure that they are initialized. However, if a context bin is used but its PEM state is not updated, the unused estimation cycle can be used to test or update the memory location pointed to by counter 2405 . After a decode operation is completed, if counter 2405 has not reached the maximum value, the remaining contexts are initialized before the next operation begins. The following logic is used to control an operation:

PEM with fast adaptation

The PEM used in the present invention can be an Adap tion scheme included for faster adaptation independently of the amount of data available. Present inven dung can enable decoding to start faster adapt and to adapt more slowly when more data ver are available as a facility to be more precise To create a proposal or an estimate. Furthermore, the PEM in a field programmable word arrangement (FPGA) to or a ASIC implementation of a PEM state table / facility be laid.

Tables 20 to 25 below describe a number of probability assessment state facilities. Some Tables do not use R3 codes or do not use co for long to reduce hardware costs. All tables except of Table 20 use special fast "adapt" states,  which are used to adapt quickly when coding starts, until the first LPS occurs. These fast adaptation states are shown initialized in the tables. For example in Table 21, when decoding begins, is the current Zu was a state 0. If an MPS occurs, the decoder goes to state 35 above. The decoder goes as long as MPSs occur from state 35, finally it goes to state 28 about. If there is an LPS at any time, it will go Decoder based on the fast adaptation states a state that indicates the correct probability represents the data received so far are.

For each table goes after a certain number of MPSs are received has been the decoder of fast adaptation states out. In the desired embodiment there is because the quick len adaptation states have been stimulated, no mechanism, to go back to this unless the coding process is back started. In other embodiments, the state table be designed accordingly in order to adapt these rapidly to be entered again to allow a faster adaptation sen. In the invention, it is possible for the decoder to to reach the more staggered codes faster, thereby possibly gain improved compression. The quick adaption for a specific table can be done by changing of the table entry for a current state 0 be made so that the table only goes up one state or down depending on the data entered goes.

For all tables, the data for each state is the code for this state is the next state with a positive current one Value and the next state if the current value is negative (below). Asterisks indicate conditions in which the MPS appears a negative current value must be changed.  

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

Adding a quick addition to a probable Movement only helps when coding starts. Other methods can be applied to an adaptation during coding improve when the statistical value of a contextual subject change faster than the previously described PEM states tables can follow.

A method for quick adaptation during coding to obtain an acceleration term to the ak add the current PEM state value. This acceleration could be placed in a PEM state table by each code is repeated a constant number of times (e.g. 8). Then an acceleration term M (e.g. a positive whole Number) added or from the current state when it updated, subtracted. If M is 1, work the system just like one without an acceleration and it comes to the slowest adaptation. If M is greater than 1, there is a faster adaptation. Initially, M can refer to ir set a value greater than 1 to initially one to create fast adaptation.

One method of the invention to update the value of M is based on the number of successive code words. If for example, a predetermined number of code words in succession that has occurred, the value of M is increased. If at for example four successive code words "0" "0" "0" "0" or "1N" "1N" "1N" "1N", then the value of M is increased. There can sweep a switching pattern between "0" and "1N" code words used to decrease the value of M. If at for example four successive code words "0" "1N" "0" "1N" or "1N" "0" "1N" "0", the value of M is decreased.

In another acceleration method, state states barking in which each code is repeated S times, where S is a positive integer. S is an inverse Be acceleration parameters. If S is one, it is adaptation  fast, and if S is larger, the adaptation slows down. Of the The value of S can initially be set to 1 to initially to get a quick adaptation. With the help of a similar one Method of any of the above may have the value of S be updated when four consecutive code words "0" "0" "0" "0" or "1N" "1N" "1N" "1N". In one In this case, the value of S is reduced. In contrast, if four successive code words "0" "1N" "0" "1N" or "1N" "0" "1N" "0", the value of S increases.

The definition of successive code words can be several Have meanings. In a "context" system, successive code words on successive code indicate words in a context subject. In a "Probably speed "system can consecutive code words on each other the following code words in a probability class sen. On the other hand, successive Co dewords to code words globally (regardless of a Context subject or a probability class). For these three Example and the memory bits required to make one Obtain code word history, 3 × number of context subjects, 3 × number of probability classes or 3. One offsetting The acceleration can be maintained for each context subject create the best adaptation. Because bad tracking often occurs attributed to a global change in the uncoded data global determination of an acceleration can also be a create good adaptation.

System applications

One success of any compression system is Spei reduce the requirements for a record. The paral The system of the invention can be used as a replacement serve that continuously through a lossless coding system has been filled, and can be applied to systems that with sound, text, databases, computers or other digital data signals, or symbols. For example, close  lossless coding systems a facsimile compression, a da ten basis compression, a compression of graphic bitmap images and compression of transformation coefficients in image compression standards such as JPEG and MPEG. The Erfin dung enables a small efficient hardware implementation and relatively quick software implementation so it does a good choice even for applications that do not have high Ge require speed.

The actual advantage that the invention has over the prior art is the ability to operate at very high speeds, particularly when decoding. In this way, expensive high-speed channels, such as high-speed computer networks, satellites and terrestrial radio channels, can be fully used with the aid of the invention. Fig. 28 illustrates such a system in which radio data or a high-speed computer network provides data to a decoding system 2801 , which decodes the data in parallel to produce output data. Current hardware entropy (like the Q-Coder) would slow the throughput of these systems. All of these systems are designed to have a high bandwidth at high cost. It is counterproductive to have a slow pass decoder. The parallel system of the invention not only adapts these high bandwidths, but actually increases the effective bandwidth since the data can be transmitted in a compressed form.

The parallel system of the invention is also applicable to obtain effective bandwidth outside moderately fast channels such as ISDN, CD-ROM and SCSI. Such a bandwidth adjustment system is shown in Fig. 28, in which data from sources such as DC-ROM, Ethernet, a narrow computer standard interface (SCSI), or other similar source are coupled to a decoding system 2901 which the Receives and decodes data to produce an output signal. These channels are even faster than some current encoders. These channels are often used to serve a data source that requires more bandwidth than the channel, such as real-time video or computer-based multimedia systems. The system of the invention can perform the role of bandwidth adjustment.

The system of the invention is an excellent choice for an entropy encoder portion of a real time video system similar to the high definition television (HDTV) system and the MPEG video standards. Such a system is shown in FIG. 29. In Fig. 29, the real-time video system has a decoding system 3001 which works with compressed image data. The system 3001 decodes the data and delivers it to a lossy decoder 3002 . The lossy decoder could be the transform color conversion and subsampling part of an HDTV or MPEG decoder. Monitor 3003 can be a television or video monitor.

Consequently, a method and a device for parallel Decoding and encoding of data have been described.

Claims (121)

1. A method for coding a data stream, which comprises the steps:
Generating code word information representing the data stream corresponding to the data stream, the code word information comprising a number of code words and furthermore a plurality of code words being generated from data of the data stream to be processed in parallel, and
Generating coded data according to the codeword information, the step of generating coded data each having the number of codewords in the codeword information to be output so that the order of the codewords to be output is based on the beginning of the part of the data stream represented by each codeword . 2. The method of claim 1, wherein each of the number of Co words is output at the beginning of each run. 3. The method of claim 1, wherein the step of generating of coded data combining variable codewords Has length in data structures of fixed length. 4. The method of claim 3, wherein each of the data structure doors of fixed length has a nested word. 5. The method of claim 4, wherein encoded data out are given so that code words in decoded order are arranged. 6. The method of claim 1, in which code words are ordered will.   7. The method of claim 1, wherein the step of generating codeword information comprises the steps of:
Generating the probability state of a code word; Selecting a bit generation code based on the probability state and
Access memory to obtain a pass count associated with the probability class. 8. Coding system for coding a data stream, with an encoder, which is provided for recording the data stream is to get code word information including code words testify, and further comprising a plurality of code words from the encoder are generated from data to be processed in parallel, and a reordering unit connected to the encoder to to generate encoded data according to the codeword information gene, the reordering code words derived from the code rer have been generated in a decoder order net, so that the order of code words to be output the beginning of part of that represented by each code word Data stream based. The encoding system of claim 7, wherein the reordering is unit stores the code words in such a way to code word size. 10. Coding system according to claim 9, wherein 1N code words so rearranged that the most significant "1" bit the length each of the code word. 11. Coding system according to claim 8, wherein the reordering unit comprises:
at least one pass count shuffling unit to generate each of the number of code words in the code word information at the beginning of each pass, and
at least one bit pack unit to combine variable length code words in fixed length data structures. 12. The encoding system of claim 11, wherein each of the data structures of fixed length has a nested word. 13. The coding system of claim 8, wherein the reordering unit arranges the code words. 14. Coding system according to claim 13 with a memory which with the reordering unit is connected to code words in a Save order. 15. The coding system of claim 8, wherein the encoder comprises:
a contextual model;
a probability assessment module associated with the context model, and
a bit generator structure connected to the probability evaluation module to generate a code word corresponding to the data stream. 16. The coding system of claim 15, wherein the encoder further comprises a memory that has a number of passes saves count values, and with which the memory with the help of probability classes from the probability rating unit of evaluation has been accessed by one of the number Run counts on the bit generator for output as part of the Provide code word information. 17. The coding system according to claim 15, wherein the bit generator structure comprises:
a bit generator to provide code word information corresponding to an index and an MPS / LPS display, and
a memory connected to the bit generator for providing a pass count to the bit generator, the bit generator reading the memory based on the index and performing bit generation based on data obtained from reading the memory. 18. Coding system according to claim 17, wherein the codeword-in formation a first signal that indicates whether the MPS / LPS display ge has the start of a run, a second signal that indicates whether the MPS / LPS indicator indicates the end of a run points, and has an output code word. 19. Coding system according to claim 11, wherein the Bitpack-Lo gik maps nested words to the encoded data stream as generating nested streams that correspond to one Nth previous code word in each nested word each Electricity are ordered. 20. The coding system of claim 11, wherein the reordering a Snooper decoder to select nested ones Has words that have been delivered into the code stream. 21. The coding system of claim 20, wherein the reordering unit a number of run count reordering units points that are connected to a number of bit pack units, where each of the number of bit pack units nested words generated, and the Snooper encoder from a nested word the number of nested words as an exit into the Has code stream. 22. Coding system according to claim 11, wherein the codeword-in formation contains a timestamp, and the reordering unit further comprises logic to interlace nested words to assign assigned time stamps. 23. The coding system of claim 22, wherein the reordering unit a number of run count reordering units points that are connected to a number of bit pack units, and where logic causes nested words ba based on an assigned time stamp. 24. The encoding system of claim 23, wherein nested  Words are submitted based on the oldest timestamp. 25. Encoding system according to claim 11, in which a single Queue delivers code words to a number of bit pack units, and where the number of bit pack units nested wor generated for output as part of the code stream. 26. The coding system of claim 25, wherein the only one Queued up a single run count reordering unit closes, and at what logic the next nested word set to output as the code stream. 27. The coding system of claim 11, wherein a single Queue provides code words to a single bit pack unit. 28. Encoding system for use in a compression system with an encoder for decoding information generated by the encoder, which encoding system comprises:
an encoder for generating code word information corresponding to data;
a reordering unit connected to the encoder, the reordering unit generating an encoded data stream corresponding to the code word information, the reordering unit having a run count reordering unit to arrange each code word at the beginning of the data corresponding to it, and a bit pack unit provided is to obtain code words from the run count shuffling unit, to combine code words into a number of interleaved words of fixed length and to output the number of interleaved words of fixed length in an order required by the decoder. 29. The coding system of claim 28, wherein the reordering unit further comprises a memory for code words during of rearranging to save. 30. The coding system of claim 28, wherein the encoder  also a contextual model, a probability assessment module that is connected with the context and one with the Probability evaluation module connected bitstream genera gate has. 31. The coding system of claim 30, wherein the pass count shuffling unit further comprises:
a first memory for storing code words;
a first indicator and a second indicator to address the first memory as a queue, the first indicator pointing to a first entry determined as an output of the first memory and the second indicator pointing to a second entry which has been determined as a next available and unallocated location in the first memory. 32. Coding system according to claim 31, with a pointer memory for Store address information, the digits in the first Corresponds to memory that is currently used to store codeword has been determined for each index. 33. The encoding system of claim 32, wherein each index is one Probability class. 34. Encoding system according to claim 32, wherein each index to indicates at least one context. 35. Encoding system according to claim 28, wherein the reordering unit also a code word store queue for storage of code words, a head pointer to at least one code word for display an output and has a tracking pointer to at least one memory location for inserting code words to display in the code word store queue. 36. Encoding system according to claim 35, wherein each code word entry in the code word storage queue  show includes, and in which also a code word from the Codeword memory queue is released when the head game specifies the address of the code word and the valid display for the code word shows its validity. The coding system of claim 28, wherein the bit packs are one unit has bit-packing logic to separate code words from the order order unit and encoded codewords To mix words for a number of streams. 38. Encoding system according to claim 37, wherein the bit-packing logic a number of accumulators and a number of registers , in which each of the number of registers one of the An number of accumulators and one is assigned to the number of currents, each register for storing a nested word for its assigned current and each accumulator the next one Place in the assigned registers for storing an ak indicates current code word for the stream, so that each code word for one of the number of streams attached to the contents of the register depends on one of the number of currents based on the value in the associated accumulator. 39. Coding system according to claim 38, with a sliding unit, which is associated with the number of accumulators to code words corresponding to at least one signal from the number of accumulators ren, whereby code words for appending to content in one of the number of registers is shifted to what's on the battery is based on parts of at least two code words in to pack every nested word. 40. Coding system according to claim 37, with a reordering to include nested words in one by the decoder agreed to save order. 41. Encoding system according to claim 40, having a number of pointers correspond to a number of nested data streams, where each  the one number of pointers in the reorder memory for the next nested word for each of the number of streams Right. 42. Coding system according to claim 28, with a number of passes count reordering units, each of the run count reordering order units assigned to one of the coded data streams and further a number of bit pack units to generate nested words for each encoded data stream and one Decoder has to get the nested words from the An Select bit pack units as the encoded output signal len. 43. Coding system according to claim 28, with a number of passes count reordering units, each of the run count reordering order units assigned to one of the coded data streams and generates a number of code words and a time stamp that is associated with each of the number of code words, and further being a number of bit pack units to generate nested ones Words for each encoded data stream and logic, around each of the nested words based on timestamps of code words in each of the nested words len. 44. Encoding system according to claim 43, wherein the logic selects nested word that is a code word with the oldest Includes timestamp. 45. The encoding system of claim 28, wherein the bit packs are one unit has a number of bit pack units provided are to take codewords from one of a number of streams and further comprises logic to include nested words for outputting from each of the number of bit pack units rend to select on the next stream. 46. Encoding system according to claim 28, wherein the reordering  unit also has a finite memory. 47. Coding system for processing data, with
an index generator for generating indexes based on the data, and
a state table which is provided to provide a probability estimate based on the indices, where the state table has a first number of states and a second number of states, each of the states corresponding to a code, and furthermore transitions between different codes, that correspond to the first number of states occur more quickly when transitioning between the states in the first number of states than states between different codes that correspond to the second group of states when transitioning in the second number of states. 48. Encoding system according to claim 47, wherein the first number Verify states only for a predetermined number of indexes be applied. 49. Encoding system according to claim 47, wherein the first number Verify states only for a predetermined number of indexes are used, which initially index the state table. 50. The encoding system of claim 47, wherein each of the first Number of states a R2 code is assigned. 51. Encoding system according to claim 48, wherein the first number States at least one transition to the second number of states de includes, so that the state table to the second to number of states from the first number of states after the previous one certain number of indexes. 52. The encoding system of claim 47, wherein each of the first Number of states is assigned to a different code.   53. Encoding system according to claim 47, wherein the status table from one of the first number of states to one of the second number states corresponding to a least true apparent symbol. 54. The encoding system of claim 47, wherein the states are towards a state most likely Symbol increased. 55. Coding system for processing data, with
an index generator for generating indexes based on the data, and
a state table provided to provide a probability estimate based on the indices, where the state table includes a number of states, each of the states corresponding to a code, and each code in the state table being repeated a predetermined number of times,
wherein a transition between states of the state table occurs based on an acceleration term that is modifiable so that a first transition rate between states during a first time period differs from a second transition rate during a second time period. 56. Encoding system according to claim 55, wherein updated Values (updates) to the state table a modification of the Show PEM state by incrementing the acceleration term is decremented. 57. Encoding system according to claim 56, in which no adaptive Acceleration occurs when the acceleration term occurs has a predetermined number. 58. Encoding system according to claim 56, wherein the acceleration gung term based on the number of consecutive codes words is updated.   59. Coding system according to claim 58, in which successive consecutive codewords in a con have text. 60. Coding system according to claim 58, in which successive code words consecutive code words in a true have probability class. 61. Encoding system according to claim 56, wherein the acceleration gung term based on the number of changing code words is updated. 62. Entropy decoder for decoding a data stream of a number of code words, with
a number of bit stream generators for receiving the data stream, and
a state table associated with the number of bit stream generators to provide a probability estimate on the number of bit stream generators, the number of bit stream generators providing a decoded result for each code word in the data stream corresponding to the probability estimate using an Rn (k) code for multiple values of n, and the state table further includes a first number of states and a second number of states, with transitions between different codes in the first number of states occurring faster when there is a transition in the first number of states than transitions between codes when in the second number of states. 63. The entropy decoder of claim 62, wherein the first Number of states each contains an R2 (k) code. 64. The entropy decoder of claim 62, wherein the first Number of states used only during initialization will.   65. Entropy decoder for decoding a data stream of a number of code words, with
a number of bit stream generators for receiving the data stream, and
a state table which is provided to provide a probability estimate based on the indices, where the state table includes a number of states, each of the states corresponding to a code, and each code in the state table being repeated a number of times,
wherein a transition between states of the state table occurs on the basis of an acceleration term which can be modified so that a first transition rate between states during a first time period differs from a second transition rate during a second time period. 66. The coding system of claim 62, wherein each code in the status table is repeated a constant number of times. 67. The coding system of claim 66, wherein updated Values to the state table modifying the PEM state by an acceleration term. 68. Encoding system according to claim 67, wherein a non-adap tive acceleration occurs when the acceleration term is one has a predetermined number. 69. Encoding system according to claim 67, wherein the acceleration gung term based on the number of consecutive codes words is updated. 70. Encoding system according to claim 67, wherein the acceleration gung term based on the number of changing code words is updated. 71. Decoder for decoding a number of interleaved words, with
a pushing unit for receiving the data stream and for delivering correctly aligned coded data;
a run length decoder connected to the shifter to receive the properly aligned, encoded data as codewords to determine the codeword type;
a probability assessment module connected to the run length decoder to determine the code for the run length decoder so that the run length decoder generates a run length and an indication of whether the LPS has occurred in accordance with each code word,
the pusher unit having a variable length pusher mechanism to pusher code words from the data stream, and
a number of registers which are provided to receive codewords from the stream according to the shifting mechanism so that aligned coded data is output as a series of codewords. 72. Decoder according to claim 71, in which a part of the regi ster is connected to register data from others of the number or record from the data stream. 73. The decoder of claim 71, wherein the mechanism variable length has a barrel pushing unit to Move data from the data stream to the number of registers. 74. The decoder of claim 71, wherein the shift unit comprises a FIFO with a number of registers, each of the Register data as an input from the nested co dated data, and at least one of the number of registers is connected to code words from another of the number regi to record. 75. The decoder of claim 71, wherein the shift unit comprises:
a number of registers arranged to receive code word data, each of the first number of registers being connected to a different one of the number of streams;
a multiplexer which is provided to receive code word data from each of the first number of registers as an input and to output code words from one of the number of registers at a specific time;
a barrel shifter connected to the output of the multiple xer for shifting code word data from the multiplexer for output as aligned encoded data;
logic connected to the shifter to indicate a number of bits to shift the code word and a FIFO with a number of registers arranged to receive code words from the multiplexer ( 1605 ), the FIFO a number of registers includes, each of the number of registers receiving data as an input from the interleaved encoded data, and at least one of the number of registers connected to receive code words from another of the number of registers. 76. Decoding system for decoding data, with
a FIFO structure provided to receive the data;
a contextual model for providing contexts;
a memory connected to the context model for storing data information, the memory creating status information corresponding to each context provided in the context model;
a number of decoders arranged to receive encoded data from the FIFO structure and the memory to decode codewords supplied by the FIFO structure and status information from the memory, the number of decoders being provided so that run counts can be generated for a number of codes. 77. The decoding system of claim 76, wherein the FIFO structure  encoded data to the number of decoders independently of context and probability classes. 78. The encoding system of claim 76, wherein the decoder has a memory for storing run count values, and the pass count memory based on a true probability class is assessable. 79. The decoding system of claim 76, wherein the FIFO structure creates data for two decoders. 80. The decoding system of claim 76, wherein the FIFO structure a number of output signals, one for each Decoder. 81. The decoding system of claim 80, wherein the FIFO structure a pair of multiplexers and control logic for selection len of the multiplexer pair to ensure that a Codeword is provided for each decoder. 82. The decoding system of claim 81, wherein the multiple xerpaar through the control logic based on requirements is selected which is obtained from one of the number of decoders have been. 83. Coding system for coding input data, with
a coding unit which is provided to receive the input data, to generate coded data in the form of a number of streams, coded data being assigned to the one of the number of streams on the basis of a set of criteria, and
a fixed size memory connected to the encoding unit for storing the number of streams of encoded data, the less important encoded data being discarded when the fixed size memory overflows. 84. The encoding system of claim 83, wherein the memory has a number of storage areas and encoded data encoded in each of the number of storage areas Have data with a different level of importance. 85. Encoding system according to claim 84, in which encoded data an importance level in at least one memory area of the Memory are stored, the encoded data on another stores its importance level. 86. Encoding system according to claim 85, in which the encoded Data of one level of importance encoded data of the other Importance level in the at least one memory area of the Overwrite memory. 87. A method of initializing a number of contexts in a system, the method comprising the steps of:
Initializing the number of contexts, each of the contexts having access based on a counter value;
Obtaining a PEM state of the current context, the step, obtaining, comprising the steps:
Accessing a memory indicator for each context that indicates the PEM state;
Determining whether the accessed memory location is valid for a current operation by comparing the current context number to the counter value so that the data is determined to be valid if the counter value indicates that the location has already been initialized;
Using an initial PEM state for the context and ignoring an instant PEM state for a context when data of the accessed location is not valid, and
Use the currently assigned PEM state for the context if the data is valid. 88. The method of claim 87, comprising the step of:
Write a new PEM state if the PEM state has changed. 89. Decoder for decoding input data, with
a contextual model to create a contextual subject;
a memory connected to the context model to create a probability state based on the context subject;
logic connected to the memory to generate a probability class based on the probability state;
a decoder connected to the logic to generate an enable signal based on the probability class;
a number of bit generators connected to the decoder and provided to receive the encoded data, each of the number of bit generators being given at least one different code, the decoder enabling one of the number of bit generators based on the probability class, so that one of the number of bit stream generators decodes the encoded data. 90. The decoder of claim 89, wherein at least one of the Number of bit generators data decoded using an R code, and at least one of the number of bit generators data with one Non-R code decoded. 91. Decoder according to claim 89, wherein bit generators for short run lengths work as an R code decoder. 92. A decoder according to claim 89, wherein bit generators for long run lengths a short run unit and a long run unit, the short running unit codes a first treats predetermined length and the long running unit ir any remaining bits handled and determines which if to be output at all from the remaining bits.   93. A method for decoding input data, comprising the steps of:
Provision of a context subject;
Accessing a memory using a context pocket to obtain a probability state;
Generating a probability class based on the probability state;
Enabling one of the number of bit generators, each number of bit generators being left to at least one different code, so that only one different code is used for decoding, so that one of the number of bit generators decodes the encoded data. 94. Coding system for coding input data, with
a contextual model to provide a contextual subject;
a memory connected to the context model to create a probability state based on the context subject;
logic connected to the memory to generate a probability class based on the probability state;
an encoder connected to the logic to generate an enable signal based on the probability class;
a number of bit generators connected to the decoder and provided to receive the input data, each of the number of bit generators being left with at least one different code, the encoder releasing one of the number of bit generators based on the probability class, so that one of the number of bit stream generators encodes the input data. 95. The encoder of claim 94, wherein at least one of the Number of bit generators data encoded with an R code and at least least a number of bit generator data using a Non-R codes encoded.   96. The encoder of claim 94, wherein bit generators for short run lengths work as an R code encoder. 97. The decoder of claim 94, wherein bit generators for long run lengths a short run unit and a long run unit, the short running unit codes a first treats predetermined length and the long running unit ir any remaining bits handled and determines which if to be output at all from the remaining bits. 98. A method for encoding input data, comprising the steps of:
Provision of a context subject;
Accessing a memory using the context pocket to obtain a probability state;
Generating a probability class based on the probability state;
Enable a number of bit generators, each of the number of bit generators dedi ced on at least one different code, so that only the one different code is sent for coding, so that one of the number of bit stream generators encodes the input data. 99. A method of decoding encoded data having a number of code words, the method comprising the steps of:
Loading a count into a counter associated with each pass counter, the count corresponding to the size of a code word memory used during encoding when a new pass is started, the count being loaded when a new code word is fetched for each pass counter becomes;
Decrementing the count each time a code word is retrieved, and
Clear the bit generator state associated with the new code word when the counter decrements to zero. 100. The method of claim 99, wherein each pass counter corresponds to a PEM state. 101. The method of claim 99, wherein each pass counter corresponds to a context subject. 102. A method for decoding encoded data having a number of code words, which method comprises the steps:
Incrementing a counter value each time a code word is requested, the counter value having a current time display;
Storing the counter value as a stored time indication when a first code word is started;
Comparing the stored display plus the size of a encoder memory to the current time display;
wherein the bit generator state for the first code word is deleted and a second code word is requested if the current time display is larger than the stored time display plus the size of the encoder memory. 103. The method of claim 102, wherein the stored Time display has a time stamp. 104. The method of claim 102, wherein the stored Time display for a subsequent code word used again becomes. 105. A method for decoding decoded data having a number of code words, which method comprises the steps of:
Storing an index corresponding to a code word, the index being stored in a queue, and the index being stored when the code word is requested;
Marking the entry of the index in the queue as invalid;
Storing the code word in the entry and marking the entry as valid when the code word is complete;
Outputting data from the queue to be decoded, the code word being provided for decoding when the queue entry is valid, and
Outputting data from the queue entry and indicating that the data is invalid to the decoder if the queue entry is marked invalid if data is being output from the queue, the bit generator state information in the decoder corresponding to data received from the Snake is deleted that are marked invalid. 106. Decoder for decoding coded data, which decoder has:
a context modeling mechanism for providing contexts, the context modeling mechanism having a number of integrated circuits;
a context-related memory for storing state information, the memory providing state information corresponding to each context provided by the context model, and
a number of decoders connected to the memory for decoding code words from the memory using the status information, the number of decoders decoding code words using a number of R codes, the number of R codes being at least one non-maximum Length sweep of probably most symbols that are not followed by a least probable symbol. 107. The decoder of claim 106, wherein the pass count value a maximum decipherable prefix that can be uniquely decoded have. 108. A code stream decoding system having a number of code words, the system comprising:
a context modeling mechanism for providing contexts, the context modeling mechanism having a number of integrated circuits;
a memory connected to the context model for storing status information, the memory providing status information corresponding to each context provided in the context model, and
a number of decoders connected to the memory for decoding code words from the memory using the status information. 109. The system of claim 108, wherein the context model mechanism at least one context model, the contexts of one of the number of integrated circuits, and at least least has a context model, the context models of one second of the number of integrated circuits. 110. The system of claim 109, wherein the at least one Context model on one of the number of integrated circuits has a zero order context model. 111. The system of claim 108, wherein contexts from the An number of integrated circuits provided directly on the memory are. 112. The system of claim 108, wherein a first portion is egg nes first context of an integrated circuit and a second part of the first context of one second integrated circuit is provided. 113. Encoding system according to claim 17, in which a bit generator gate state of the bit generator is updated, and at which also the bit generator before the current state, which in the Memory to be written is used again. 114. The encoding system of claim 113, wherein the bit generator during the modification stage of a read-modify-write cycle is used again.   115. Encoding system according to claim 17, wherein the bit generator tor generates a non-minimal length pass count if a current state on the memory again before writing is used. 116. The encoding system of claim 17, wherein the bit generator data is encoded using R codes that are defined that at least one uncoded bit follows each run length, so that two code words of the same run length are never on one line be decoded. 117. System for decoding a code stream having a number of code words with
a context modeling mechanism for providing contexts;
a memory connected to the context model for storing status information, the memory creating status information corresponding to each context provided by the context model, and
a number of decoders connected to the memory for decoding code words with the aid of the status information from the memory, at least one of the number of decoders having a delay-tolerant decoder. 118. The system of claim 115, wherein at least one of the Number of decoders shift based on variable length of decoded data after a delay Are available. 119. The system of claim 117, wherein each of the number De Encoder data of variable length as an input signal points. 120. The system of claim 119, wherein the number of decoders Decode input of variable length in parallel.   121. The system of claim 117, wherein an output signal the number of decoders in nested words of fixed length is shared.