RU2103825C1 - Module for compressing voice messages by data bursts - Google Patents

Abstract

FIELD: communication engineering; data transmission over digital pulse-code modulated and time-shared communication channels. SUBSTANCE: module has first data terminal equipment wire 1, universal line transceiver 2, digital channel transmitter 3, first digital transmission system wire 4, nine-bit bus 5, AND1, AND2, AND3 gates 6, 10, 24, third data terminal equipment wire 7, first shaper 8, delay circuit 9, second digital transmission system wire 11, digital channel receiver 12, second data terminal equipment wire 13, eight-bit bus 14, second shaper 15, third and fourth digital transmission system wires 16, 17, adder 18, flip-flop 19, counter 20, fifth, sixth, and seventh digital transmission system wires 21, 23, 23, fourth data terminal equipment wire 25, subscriber detector 26, eighth ant ninth digital transmission system wires 27, 28. EFFECT: improved capacity of information transmission over digital communication channels, improved data transmission speed over them. 9 dwg

Description

 The invention relates to the field of communication, in particular to a technique for transmitting data via digital communication channels (CCP) with pulse-code modulation (PCM) and time division of channels.

 A well-known multiplexer with a static temporary channel multiplexing (MSVU) [1], in which a common communication channel (CCU) with a fixed bandwidth is divided into several separate channels with a bandwidth dynamically redistributed between these channels, depending on the presence or absence of information in them. This distribution is carried out in accordance with various communication protocols, for example, such as HOLC or SOLC. Thus, the throughput of an individual communication channel can be achieved, depending on the adopted communication protocol, from the minimum part of the throughput equal to the total throughput of the common communication channel divided by the number of individual channels (in the case of activity of all individual channels) to the common communication channel (if individual channels are currently not active).

 The advantage of this device is a more complete use of the bandwidth of the common communication channel (increased information content of the transmission) and the possibility of obtaining higher transmission speeds in individual communication channels.

 The disadvantage is that they cannot perform this multiplexing on existing digital communication channels with a fixed format of a data transmission frame (for example, for telephone transmission systems (s / n), such as PCM-30), without updating the s / n data.

 A device for input-output data into a digital communication channel with PCM, selected as a prototype [2].

This device is characterized by the fact that it enters and outputs data in a digital communication channel with the coordination of speeds by stuffing method of combination of characters and contains:
the first wire of the data terminal equipment connected to the first input of the line receiver [2 scheme p. 48 (input node), a wire included in the input device], which consists of the input device, the receiver of the starting package, the first trigger And, the first divider, the first counter, the receiving drive;
the second wire of the data terminal equipment connected to the output of the linear transmitter [2 scheme p. 55 (output node), the wire included in the output device], which consists of the output device, circuits OR, AND, I2, inverter, zero decoder, six counter, trigger;
the first wire of a digital transmission system connected to the output of a digital channel transmitter [2 scheme p. 48 (input node), the wire included in the output circuit AND], which consists of the first and second transmitting drive, circuit OR, second trigger, output circuit And, decoder, second and third dividers, circuits I8, I9;
the second wire of the digital transmission system connected to the first input of the digital channel receiver [2 scheme p. 55 (output node), the wire included in the input device], which consists of a shift register (B1, B2), a controlled divider, the first and second decoders (B1, B2 = 10; B1, B2 = 01), a phasing device;
the third wire of a digital transmission system connected to the second input of a digital channel receiver [2 scheme p. 55 (output node), the wire included in the controlled divider and in the shift register (в1, в2)], and to the first input of the linear transmitter [2 scheme p. 55 (output node), the wire included in the second input of the circuit And];
the second input of the linear transmitter is connected to the output of the digital channel receiver [2 scheme p. 55 (output node), a wire connecting the shift register (B1, B2) and the second input of the I2 circuit];
the first, second, third, fourth, fifth, sixth output of the line receiver are connected respectively to the first, second, third, fourth, fifth, sixth input of the digital channel transmitter [2 scheme p. 48 (input node)], five wires connecting the receiving drive with the first and second transmitting drives (five wires with the first inputs of circuits I1-I5, I1'-I5 ', and the sixth wire connects the output of the first counter to the second inputs of circuits I1-I6, I1'-I6 '), hereinafter this connection is called a six-bit bus connection;
output of the master oscillator [2 scheme p. 48 (master oscillator and driver)], connected to the second input of the line receiver [2 circuit p. 48, connection to the second input of the circuit And] and to the seventh input of the transmitter of the digital channel [2 circuit p. 48, (connection to the input of the second divider)].

 This device receives start-stop combinations on the first wire from the data terminal equipment (OOD) and converts them into parallel five-bit packages in a linear receiver, which operates under the action of a frequency from the master oscillator, which is fed to the second input of the linear receiver. Five-bit packages are sent from the line receiver to the five inputs of the digital channel transmitter, and its sixth input is used to record the five-bit package supplied from the sixth output of the linear receiver, the digital channel transmitter operates under the influence of the frequency from the master oscillator, which is fed to the seventh input of the digital channel transmitter , and he makes the input of five-bit packages to the central digital signature, with the coordination of speeds by the method of stuffing the combination of characters.

 This five-bit package is introduced into the digital communication channel sequentially, from the output of the digital channel transmitter via the first wire to the digital s / n, and from the second digital s / p wire, it is output from the digital communication channel to the first input of the digital channel receiver, in which these five-bit packages under the action of clock pulses arriving at the second input of the receiver of the digital channel on the third wire from the digital s / n. The receiver of the digital channel performs phasing of the input and output device and the removal of staffing combinations.

 From the receiver of the digital channel, this five-bit package is sequentially fed to a linear transmitter, which operates under the action of clock pulses arriving at its first input from the third digital s / n wire. The linear transmitter converts the five-bit package into a start-stop combination and transfers it through the second wire of the OOD to the OOD.

 The advantage of this device is that it can be connected to existing digital s / p, without their modification, and they also have the ability to compact the common communication channel (CCS) with information from several such input-output devices.

 The disadvantage is that the information content of the transmission of such a device is low (data transfer rate is not higher than 8 kBt / s per digital communication channel, for s / n type PCM-30). This is due to the fact that the input of a five-bit message in the digital communication channel is performed under the action of a separate master oscillator, and the output is sequentially from the receiver of the digital channel to the linear transmitter, in addition, the device cannot transmit data together with other information (for example, voice information), which does not allow to increase the information content of the transmission of the common communication channel, the maximum of which for s / p type IKM-30 is 64 kbit / s.

 The problem solved by the invention is to increase the information content of transmission over digital communication channels and to increase the data transfer rate on the CCS.

 This is achieved by the fact that in the voice message compaction module, data packets containing serially connected, the first wire of the data terminal equipment, a line receiver, a digital channel transmitter, and a first wire of a digital transmission system, the line receiver and the digital channel transmitter connected by a six-charge bus, and a second wire of a digital transmission system, a digital channel receiver, a line transmitter, a second wire of data terminal equipment, and a third wire The digital transmission system is connected to the input of the digital channel receiver and the input of the linear transmitter, according to the invention, a universal linear transceiver, first and second formers, a subscriber detector, a delay circuit, circuits I1, I2, I3, a counter, an adder are introduced as a linear receiver and transmitter a trigger, the third and fourth wires of the data terminal equipment, the fourth, fifth, sixth, seventh, ninth wires of the digital transmission system, the first wire of the terminal equipment being connected in series data, a universal linear transceiver, a digital channel transmitter, and the first wire of a digital transmission system, where a universal linear transceiver and a digital channel transmitter are connected by a nine-bit bus, in addition, the output of circuit I1 is connected to the first input of the transmitter of the digital channel, the first input of which is connected to the third terminal wire data equipment, the first output of the first driver is connected to the second input of the digital channel transmitter, the second output of which is connected to the first input universally linear transceiver, and the third input of the digital channel transmitter is connected to the first output of the delay circuit, the second output of which is connected to the first input of the I2 circuit, and the second wire of the digital transmission system, the digital channel receiver, universal linear transceiver, the second wire of the data terminal equipment are connected in series moreover, the digital channel receiver is connected to a universal linear transceiver by an eight-charge bus, while the first input of the digital channel receiver is connected to the output of watts a shaper, the first input of which is connected to the third wire of the digital transmission system, and the second input to the fourth wire of the digital transmission system, in addition, the first output of the digital channel receiver is connected to the first input of the adder and to the second input of the universal linear transceiver, the second output of the digital channel receiver is connected with the second input of the adder with the first input of the trigger, the third output of the receiver of the digital channel is connected to the third input of the adder and the second input of the trigger, and the fourth output of the receiver and the second input of the trigger, and the fourth output of the receiver of the digital channel is connected to the first input of the counter, the output of which is connected to the fourth input of the adder, the second input of the circuit I1, the third input of the trigger, the second input of the receiver of the digital channel and the fifth wire of the digital transmission system, the sixth wire of which is connected to the first input of the first driver and to the second input of the I2 circuit, and the seventh wire of the digital transmission system is connected to the second input of the first driver, while the fourth trigger input is connected to zero by potential, and its output is connected to the first input of the I3 circuit, the output of which is connected to the fourth wire of the data terminal equipment, and the second input of the I3 circuit is connected to the output of the subscriber detector and to the input of the delay circuit, in addition, the input of the subscriber detector is connected to the eighth wire of the digital transmission system , the ninth wire of which is connected to the output of circuit I2, and the output of the adder is connected to the second input of the counter.

 Thus, the similarity of the prototype with the voice message compression module with data packets makes it possible for the module to implement a data transfer method with the parallel accumulation of start-stop signals and rate matching between the data transfer rate and the speed in the CCS using the stuffing method of character combination.

The difference from the prototype is expressed in that:
introduced as a linear receiver and transmitter a universal linear transceiver, first and second formers, subscriber detector, delay circuit, circuits I1, I2, I3, counter, adder, trigger, third and fourth wires of data terminal equipment, fourth, fifth, sixth, seventh , the eighth, ninth wires of a digital transmission system - this together gives the technical result indicated below;
the first wire of the data terminal equipment, the universal linear transceiver, the digital channel transmitter, and the first wire of the digital transmission system, where the universal linear digital channel transceiver are connected by a nine-bit bus, which increases the sending format to eight information bits, are connected in series;
the output of the I1 circuit is connected to the first input of the digital channel transmitter, the first input of which is connected to the third wire of the data terminal equipment, which allows the implementation of any exchange protocols between the OOD;
the first output of the first driver is connected to the second input of the digital channel transmitter to clock the digital channel transmitter to achieve the specified technical result;
the second output of the first driver is connected to the first input of the universal linear transceiver, which gives the clock of the universal linear transceiver;
the third input of the digital channel transmitter is connected to the first output of the delay circuit, the second output of which is connected to the first input of the I2 circuit, which provides speech compression with data, and the compression of any existing CCS;
the second wire of the digital transmission system, the digital channel receiver, the universal linear transceiver, the second wire of the data terminal equipment are connected in series, the digital channel receiver being connected to the universal linear transceiver by an eight-bit bus, which gives an increase in the sending format to eight information bits, and speech compression with data;
the first input of the digital channel receiver is connected to the output of the second driver, the first input of which is connected to the third wire of the digital transmission system, the second input to the fourth wire of the digital transmission system, which gives the clock of the digital channel receiver to achieve the specified technical result, and speech compression with data;
the first output of the digital channel receiver is connected to the first input of the adder and the second input of the universal linear transceiver, the second output of the digital channel receiver is connected to the second input of the adder and the first input of the trigger, the third output of the digital channel receiver is connected to the third input of the adder and the second input of the trigger, and the fourth output of the receiver of the digital channel is connected to the first input of the counter, the output of the counter is connected to the fourth input of the adder, the second input of circuit I1, the third input of the trigger, the second input of reception nickname of the digital channel, and with the fifth wire of the digital transmission system, the sixth wire of which is connected to the first input of the first driver, and to the second input of the I2 circuit - this together gives speech compression with data and the implementation of any exchange protocols between the OOD;
the seventh wire of the digital transmission system is connected to the second input of the first driver, which gives an increased data rate;
the fourth trigger input is connected to zero potential - for the implementation of functions it is a trigger;
the trigger output is connected to the first input of the I3 circuit, the output of which is connected to the fourth wire of the data terminal equipment, and the second input of the I3 circuit is connected to the output of the subscriber detector and to the input of the delay circuit, where the input of the subscriber detector is connected to the eighth wire of the digital transmission system, the ninth wire of which connected to the output of the I2 circuit, and the adder output is connected to the second input of the counter - this together gives speech compression with data and the implementation of any exchange protocols between the OOD.

The technical result is expressed in:
increased data transfer rate (64 kBit / s instead of 8 k / Bit / s for one module on one DSS);
compiling the CKS with data and speech information without finalizing this s / p (type PCM-30);
compaction of any existing CCS;
implementation of any exchange protocols between OOD (synchronous, asynchronous, with software and hardware control of data transfer between OOD (acknowledgment));
increase the sending format to eight information bits;
the above leads to increased information content of the transmission of the common communication channel (CCS) and to the integration of voice / data services.

 In FIG. 1 shows a diagram of a voice message compression module with data packets; in FIG. 2 - connection of wires of the data terminal equipment from the module to the data terminal equipment; in FIG. 3 - inclusion of digital s / n wires from the module to digital s / n; in FIG. 4 - diagrams and timing diagrams of the first and second formers; in FIG. 5 is a subscriber discovery scheme; in FIG. 6 is a delay circuit; in FIG. 7 is a fragment of a digital channel transmitter circuit; in FIG. 8 is a fragment of a receiver circuit of a digital channel; in FIG. 9 - time diagrams of the module (the signal coming from the module to the CSC and received from the CSC, respectively).

 As information confirming the operation, we present the diagrams of FIG. 1 and 2 and describe their work.

 The voice message compression module with data packets contains (Fig. 1) a first wire 1 of the data terminal equipment, a universal linear transceiver 2, a digital channel 2 transmitter, a digital channel 3 transmitter and a first wire 4 of a digital transmission system, where the universal linear transceiver 2 and transmitter digital channel 3 are connected by a ten-digit bus 5, in addition to the first input of the digital channel transmitter the output of circuit I1, 6 is connected, the first input of which is connected to the third wire 7 of the window data equipment, the first output of the first driver 8 is connected to the second input of the digital channel transmitter, the second output of which is connected to the first input of the universal linear transceiver 2, and the third input of the digital channel 3 transmitter is connected to the first output of the delay circuit 9, the second output of which is connected to the first input of the circuit I2, 10, and also connected in series to the second wire 11 of the digital transmission system, the receiver of the digital channel 12, universal linear transceiver 2, the second wire 13 of the terminal equipment data, and the receiver of the digital channel 12 is connected to a universal linear transceiver 2, an eight-bit bus 14, in addition, the first input of the receiver of the digital channel 12 is connected to the output of the second driver 15, the first input of which is connected to the third wire 16 of the digital transmission system, and the second input to the fourth wire 17 of the digital transmission system, while the first output of the receiver of the digital channel 12 is connected to the first input of the adder 18 and to the second input of the universal linear transceiver 2, the second output of the digital receiver the first channel 12 is connected to the second input of the adder 18 and the first input of the trigger 19, the third output of the receiver of the digital channel 12 is connected to the third input of the adder 18 and the second input of the trigger 19, and the fourth output of the receiver of the digital channel 12 is connected to the first input of the counter 20, the output which is connected to the fourth input of the adder 18, the second input of the circuit I1, 6, the third input of the trigger 19, the second input of the receiver of the digital channel 12 and with the fifth wire 21, a digital transmission system, the sixth wire 22, which is connected to the first input of the first driver 8, and to the second input of the circuit I2, 10, and the seventh wire 23 of the digital transmission system is connected to the second input of the first driver 8, in addition, the fourth input of the trigger 19 is connected to zero potential, and its output is connected to the first input of the circuit I3, 24, the output of which is connected to the fourth wire 25 of the data terminal equipment, while the second input of the I3,24 circuit is connected to the output of the subscriber detector 26 and to the input of the delay circuit 9, in addition, the input of the subscriber detector 26 is connected to the eighth wire 27 of the digital transmission system, the ninth wire 28 of which It is connected to the output of circuit I2, 10, and the output of the adder 18 is connected to the second input of the counter 20.

Four wires (1, 13, 7, 25) of the OOD are connected to the OOD 29 (Fig. 2) as follows:
the first wire 1 is connected to the data transmitted from the OOD (in the standard V-24 MKKTT, 103 circuit) [1];
the second wire 13 is connected to the data received by the OOD (in the standard V-24 CCITT: 104 circuit) [1];
the third wire 7 is connected to the transmission request, or to the readiness of the OOD (in standard V-24 MKKTT, 105, or 108 circuit) [1];
the fourth wire 25 is connected to the readiness of the module (ADF) for transmission (in the standard V-24 MKKTT, 106, or 107 circuit) [1].

Nine wires (4, 11, 16, 17, 21, 22, 23, 27, 28) of the digital s / n are connected to the digital s / n IKM-30, 30 [3] (Fig. 3), as follows:
the first wire 4 is connected to a digital s / n IKM-30, to connector Ш1, in the FLS (linear signal conditioner) pin 3 (discrete information, transmission);
the second wire 11 is connected to a digital s / p IKM-30, to connector X1, in PC. pin 9 (discrete information, reception);
the third wire 16 is connected to a digital s / n IKM-30, to connector X1, PK.Pr., pin 5 (strobe. 2);
the fourth wire 17 is connected to the digital s / n IKM-30, to connector Ш1, in the receiver's DK (channel divider), pin 1-32 (depending on which channel interval is selected for data transmission by this module, channel intervals from 1 to 31, except 16 and 0);
the fifth wire 21 is connected to a digital s / n IKM-30, to connector X1, in the decoder, pin 14 (inhibit decoder);
the sixth wire 22 is connected to a digital s / n IKM-30, to connector Ш1, in the transmitter DC, pin 1-32 (depending on which channel interval is selected for data transmission by this module, channel intervals from 1 to 31, except for 16 and 0);
the seventh wire 23 is connected to a digital s / n IKM-30, connector X2, generator board, pin 5 (strobe 2);
the eighth wire 27 is connected to a digital s / n IKM-30, a resistor R5 (Fig. 3), in a transceiver;
the ninth wire 28 is connected to a digital s / n IKM-30, to connector Ш1, in the FLS, pin 10 (telephone prohibition).

 The component parts of the module of FIG. 1 consists of the following parts.

 Universal linear transceiver consists of one chip type KR581VAA.

 Circuits I1, I2, I3, 6, 10, 24 are two-input circuits of type I.

 The adder 18 is a four-input logic circuit, for example, type OR.

 Counter 20 may consist of any suitable counter, for which the first input is reset and the second is countable.

 Trigger 19 is a regular D-flip-flop, with inputs R and S. Moreover, its first input is C input, the second input is S input (with an active setting level - one), the third is R input (with an active reset level - zero), the fourth - D input, and output without inversion.

 The first and second shapers 8, 15 consist of two-input AND type circuits, the outputs of which are outputs 8 and 15, and the inputs are the first and second inputs in 8 and 15 of FIG. 4. The first driver 8 also has a divider 31, for example, a 555IE7 counter connected to the second input 8 (wire 23) and its second output.

 The subscriber detector circuit 26 is shown in FIG. 5, where the wire 27 of FIG. 1 is included in the input of amplifier 32, (which is the input of the subscriber detector 26 of FIG. 1), the output of which is connected to the input of the comparator 33, the output of which is the output of the detector of the subscriber 26 of FIG. one.

 The delay circuit 9 is shown in FIG. 6, where the output of the subscriber’s detector 26 is included in the inputs S of two delay triggers 34, 35 connected in series, and the master oscillator 36 is included in the inputs S of these triggers. The input D of the trigger 34 is connected to zero. The output of the trigger 34 is the first output of the delay change 9, and the output of the trigger 35 is its second output (Fig. 1).

The transmitter of digital channel 3 consists of the same components as in the prototype [2 diagram p. 48 (input node)], i.e. from FIG. 7:
the first and second transmitting drive 37, the 38 capacities of which are increased to ten bits (inputs of the nine-bit bus 5) and the input of the sequential loading of the transmitting drives (the first input to the transmitter of digital channel 3) is introduced;
circuits OR, 39; second trigger (not shown); output circuit And, 40, (the second input of which is the third input to the transmitter of the digital channel 3, Fig. 1); a decoder (not shown); second, 41, and third (not shown) dividers (input 41, is the second input in 3 of Fig. 1); schemes I8, I9 (not shown). This addition to the design of the digital channel transmitter does not lead to any new technical characteristics per se.

The receiver of the digital channel 12 consists of the same components as in the prototype [2 scheme p. 55 (output node)], i.e. from FIG. eight:
shift register (в1, в2), 42, which is increased to ten cells (the outputs of which are eight-bit tires 14, and the input is wire 11); managed divider 43; the first and second decoders (b1, b2 = 10; b1, b2 = 01), instead of which we introduce a single decoder 44, which consists of one chip, for example, any read-only memory - ROM, with twelve inputs (ten of which are connected to the register outputs shift, 42, the eleventh with a controlled divider 43, and the twelfth is the second input in the receiver of the digital channel 12), and three outputs (the first and second outputs are connected to the phasing device 45, and the first, second, third outputs are respectively the first, second, third outputs 12 m); cyclic phasing device 45, the output of which is also the fourth output of the receiver of the digital channel 12; the first input at 12 is a clock input for the shift register 42, and the controlled divider 43. The circuit is similar to the prototype, and the addition of the design of the receiver of the digital channel 12 does not lead to any new technical characteristics per se.

 We install two such voice message compression modules with data packets at different stations, connected to each other with an IKM-30 s / n (or another digital s / n) and connect to the OOD and to the digital s / n, as in FIG. 2-3. We call stations ATS A and ATS B, modules respectively module A, module B, and data terminal equipment - OOD A, OOD B.

 Modules can be installed on all digital channels created by this digital s / n.

 Consider the operation of this module and its components, while we assume that the active signal levels are equal to one, and inactive levels to zero.

 The universal linear transceiver 2 of FIG. 1 receives start-stop signals from line 1 and, upon completion of reception, outputs 8 information bits to bus 5, and to the ninth output of this bus, a reception end signal, which we use as a signal to write information bits from bus 5 to the transmitter of digital channel 3. To the inputs 2, on the bus 14 information bits are received in parallel form and are recorded by the signal from the second input to 2, and output to line 13 in a start-stop form to the OOD. Reception and transmission of signals is controlled by a clock sequence supplied to the first input in 2, which sets the speed of work.

 At the output of counter 20, the active signal is unity. This output is the output of the end of the count, and the counter itself works in the usual way (chip 555IE7).

 The operation of the first and second shapers 8, 15 (Fig. 1) is performed in accordance with the time diagrams 34, where the vertical axes are indicated by the inputs - outputs of these shapers. The channel interval from PCM-30 is fed to the wires 22, 17, in which data will be transmitted (Fig. 3), and the strobe is fed to the wires 23, 16. 2 (Fig. 3) [3]. In this case, the sequence for the operation of the universal linear transceiver 2, which is obtained by dividing with the help of any counter (for example 555IE7) strobe, is removed from the second output of the first shaper 8. 2 by the desired value (for example, if the data is received through the first wire 1 of the OOD at a speed of 19.2 kBit / s, then the division ratio for the universal linear transceiver chip type 581BA1A is equal to k = (2048 / 19.2) / 16 = 6-7 where: 2048 is the strobe frequency. 2; 19.2 is the transmission speed of the OOD; 16 is the coefficient for 581BA1A).

 Subscriber Detector 26 of FIG. 1 is connected by wire 27 to the PCM-30 transceiver, FIG. 3 (this is necessary in order to remove the signal of only one voice subscriber, i.e., of the two voice subscribers conducting the conversation, only one is needed, which we do by connecting the wire 27 after the differential system of Fig. 3), from which we remove the conversation signal of the subscriber, we amplify it with an amplifier 32 and feed it to a comparator 33, for conversion to the TTL levels of logic. Using the amplifier 32 and the comparator 33, we configure the subscriber's detector so that interference from the voice subscriber line is not affected, i.e. so that it works only from the conversation of the subscriber and does not work from interference. This setting is done by adjusting the gain of the amplifier 32 and the response threshold of the comparator 33, which is known and not difficult to do. Thus, the active signal at the output of the comparator 33 appears in the absence of the subscriber and disappears when it appears.

 The delay circuit 9 of FIG. 1, if there is an active signal at its input, it is set at the inputs S of the triggers 34, 35 of FIG. 6 and units are set at the outputs of the triggers. When the active signal from inputs S is removed, a trigger 34, 35 records zero from the D input of trigger 34, with a delay set from the master oscillator 36. First, zero is written to trigger 34, then to trigger 35, at the first and second output of delay circuits 9 sequentially zeros appear.

 The digital channel transmitter 3 of FIG. 1 works similarly to the prototype, on bus 5 receiving an eight-bit information combination recorded on the ninth input of bus 5, and outputting it to the output (wire 4) by a clock signal from the second input, while transmitting to storage drives (37, 38, Fig. 7) either units or zeros supplied at the first input to 3 are sequentially loaded from the I1, 6 circuit, and at the third input to 3, information is output from the transmitting drives prohibited and either zero or one zeros are output to wire 4 (for the And circuit - one zeros), regardless of what was written but to transferring drives (from structure 3).

The digital channel receiver 12 of FIG. 1 works similarly to the prototype, sequentially receiving information from the CCS on wire 11, under the action of a clock sequence supplied at its first input. It displays information in eight-bit form on bus 14, recording it in 2 as a signal from its first output. A ten-bit shift register 42 is connected inside the receiver 12 with all its outputs to the decoder 44, (Fig. 8), so the decoder 44 does not decode the two control stuffing bits, but the entire ten-bit cycle, while the outputs from the first to the third receiver 12 are the decoder outputs 44, and the outputs of the first and second decoder 44 for circuit 45, for phasing. The functions of these outputs are described by equations depending on the state of its twelve inputs:
-output1 (1) = 1 (x) * 2 (x) * 3 (x) * 4 (x) * 5 (x) * 6 (x) * 7 (x) * 8 (x) * 9 (1) * 10 (0) * 11 (1) * 12 (1), i.e. decryption of the signal at the twelve inputs of a decoder of the form: xxxxxxxxxx1011;
-output2 (1) = (1 (0) * 2 (0) * 3 (0) * 4 (0) * 5 (0) * 6 (0) * 7 (0) * 8 (0) * 9 (0 ) * 10 (1) * 11 (1) * 12 (x)) + 1 (1) * 2 (1) * 3 (1) * 4 (1) * 5 (1) * 7 (1) * 8 ( 1) * 9 (0) * 10 (1) * 11 (1) * 12 (x), i.e., decryption of signals of the form: 00000000011x, and 11111111011x;
-output 3 (1) = 1 (1) * 2 (1) * 3 (1) * 4 (1) * 5 (1) * 6 (1) * 7 (1) * 8 (1) * 9 (0) * 10 (1) * 11 (1) * 12 (1), i.e. decryption of the signal type: 111111110111; Where:
1-12 - decoder inputs;
* - logical multiplication;
+ - logical addition;
(x) - any value;
in parentheses are the values of inputs / outputs, for example:
1 (1) - the value of the first input is equal to a logical unit. In this case, the twelfth input of the decoder is the second input of the receiver 12 and, as can be seen from the equations for this input, the operation enable signal is supplied to the first and third outputs of the decoder 44, Fig. 8 and the receiver 12. The decryption enable signal from the controlled divider 43 of FIG. 8 (the work is similar to the prototype). In addition, the fourth output 12 (from the output of the cyclic phasing device 45, Fig. 8) is fed a signal of no phasing of the receiver 12.

The operation of the entire module occurs according to the description below, and to illustrate the operation, a signal diagram is shown in the digital communication channel of FIG. 9, where:
TI - clock interval CKS;
KI - channel interval (corresponds to one CKS);
AB - the period of activity of the voice subscriber;
PD - data transmission period;
X - control stuffing control bits of the first type (10);
Y - control stuffing bits of the combination of the second type (01);
K1 - an empty combination of the first type (00000000);
K2 - an empty combination of the second type (11111111);
D - data;
above the time axis, the TI values are indicated, where: x is any value;
- diagram D - continuation of diagram C, diagram C - continuation of diagram B, diagram B - continuation of diagram A.

 In the absence of speech information supplied to the digital s / n 30 through the differential system to the transceiver [3], there is no active signal on the eighth wire 27 and therefore there is an active signal at the output of the subscriber's detector 26, which is fed to circuit I3, 24 and also sets both the outputs of the delay circuit 9 to the active single state, arriving at I2, 10 and the third input at 3. At the same time, the signals of the selected channel of FIG. 3 and pass to its output in the form of a telephone ban signal supplied to digital s / n 30, Fig. 3. Digital s / n 30 enters information into the central digital communications center from modules A and B in the direction to each other, from telephone exchanges A and B.

 At the same time, information from the OOD is not received through wire 1, since there is no signal of readiness of the module for transmission on the wire 25 towards the OOD, and since the OOD is already connected, they are transmitted through wire 7 to the side of their modules A and B, to ATS A and B, give their signal of readiness for transmission, which goes to I1, 6. Reception information on wire 13 also does not go to the OOD, since the first output of receiver 12 is prohibited by the signal from its second input equal to zero (it is set by resetting the counter for 20 s cyclic phasing device 45 of Fig. 8), which also holds t rigger 19 is at zero, it goes to the PCM-30 s / p in the form of a decoder inhibit signal, goes to the second input I1, 5, to the fourth input of the adder 18, allowing it to work, and therefore information from the digital channel receiver to the universal linear transceiver 2 12 is not recorded by the signal from this first output of the receiver 12 (a decoder from its composition).

 Since the information on wire 1 does not arrive, the transmitters of digital channel 3, modules A and B work on the stop similarly to the prototype and enter into the digital channel sequences of ten bits equipped with two bits for controlling staffing of the combination and eight empty bits, for controlling staffing of the combination and eight empty bits that are entered sequentially at 37, 38, FIG. 7 (transmitting drives from the transmitter of the digital channel 31). From the output of circuit I1, 6, at the output of which the value is zero (since there is no active signal at its second input), zeros are written in 3 sequentially.

 The empty bits thus have a value of zero, and the combinations are: 000000000100000000010000000001 ...

 The receivers of the digital channel 12, modules A and B, in this way from the transmitters of the digital channel 3 of modules A and B, from opposite automatic telephone exchanges A and B, via wire 11 from the CCS, receive this combination and perform phasing. This phasing process occurs similarly to the prototype, only phasing does not occur according to two bits of stuffing stuffing control by a symbol, but over the entire ten-bit combination, using a ten-bit shift register, and a decoder 44 from receiver 12, Fig. 8.

 After phasing is over, the second output 12 receives a signal of decryption of a signal of the form 0000000001 and after 18 it goes to counter 20. Counting 20, for example, to sixteen (the counting coefficient should be optimally matched), sets the active signal 1 to its output. both modules A and B.

 The active signal at the output of the counter 20 is fed to wire 21 and gives the inhibit signal to the decoder s / p IKM-30, figure 3, in addition, it allows the decoder 44 (consisting of 12, at the second input at 12) to work on the first and third outputs, and also prepares trigger 19 for operation, prohibits further counting due to the receipt of a unit in circuit 18, and gives a second unit to circuit I1, 6, as a result of which one is set at the output of circuit I1, 6, and the signal from the output of digital channel 3 transmitter (wire 4) takes the form: 11111111011111111101111111111101 ... This signal arrives the communication channel from both modules A and B and is received by both modules A and B. Decoder 44, (as part of receiver 12), decrypts this signal and outputs it to the third output of receiver 12, and it goes to the second input of trigger 19, which is set to unit and through wire 25, through the I3, 24 circuit, gives the OOD signal to the side of the module readiness for transmission (since the first input of the I3, 24 circuit contains an active signal from the subscriber's detector 26, which indicates the absence of activity of the voice subscriber). This happens with both modules A and B.

 OOD start transmitting data that comes about 1 and 2 in parallel on bus 5, to transmitter 3, and is output to wire 4, to the communication channel in the form: xxxxxxxxxx 10xxxxxxxx10xxxxxxxx10 ...: where x is the data. Work 3 is similar to the prototype. The coordination of speeds is made by inserting a combination of 1111111101, Fig.9.

 These combinations with the data are received at the receiver 12 on the opposite exchange and set on the bus 14, and only information bits are set, which is provided by the phase of the operation of modules A and B (prototype). The decoder 44 (consisting of 12) decodes these combinations and gives a signal to its first output (and to its first output 12), which records the combination of data with bus 14, to a universal linear transceiver 2, which outputs them in a start-stop form to the OOD . OOD A and B exchange data.

 When the voice subscriber is active, for example, on the PBX A, on the wire 27 of this module A, an active signal appears, which leads to the removal of the active signal from output 26, which leads to the removal of the readiness of module A for transmission (wire 25, removes the unit by removing the unit from the second input of circuit I3) and OOD A stops transmitting data to wire 1, to module A. The transmitter of digital channel 3 transfers the remaining data received from OOD to the channel. After that, at the first output of circuit 9, a zero appears (appears with a delay for transmitting the remaining data, (delay circuit of Fig. 6). This zero leads to the prohibition of circuit And, Fig. 7 from the composition of the transmitters 3 (on the third input in 12 of Fig. 7 ) and to wire 4, zeros are sent to the communication channel in the direction of module B: 000000000000000000000000000000 ... Module B accepts these zeros and does not decrypt decoder 44, (from part 12), since this combination is forbidden for this decoder (see. above), therefore, there are no signals at its outputs and the receiver 12 exits the operation phase, with four the output from circuit 12 (with a phasing device 45, Fig. 8) receives a signal and the counter 20 is reset (at its first input), zero appears on its output, which leads to the reset of trigger 19 to zero, and OOD B stops transmitting data (since the unit is removed from the wire 25, to the OOD B side, by removing the unit from the first input I3), In addition, removing the unit from output 20 gives the decoder 44, (part 12) at the second input to receiver 12, prohibition of operation its first and third outputs (respectively, the first and third outputs 12 as well). Therefore, writing information to 2 is prohibited. By wire 21 towards the IKM-30 s / p, the inhibitor signal of the decoder of Fig. 3 is also removed, preparing for the establishment of a conversation between voice subscribers, and zeroes are transmitted from circuit I1, 6 to transmitter 3 and transmitted to the CCS as part of a signal of the form: 00000000010000000001. .., in the direction of module A. The unit is also removed from the fourth input of circuit 18, which allows the counter to be counted 20.

 Module A receives these signals and removes a unit from the first input of circuit I3, 24, using a trigger 19, the first input of which (from the second output 12) receives a signal, and writes zero from its fourth input to trigger 19. There is no data reception from module B. OOD A and B stop the data exchange.

 Following this, circuit 9, with continued activity of the voice subscriber (on PBX A), removes one from the second output of circuit 9, which leads to the removal of the telephone barring signal from output I2, 10 (wire 28), Fig. 3 receives information in the communication channel from the voice subscriber to the PBX A, to the voice subscriber to the PBX B. In the case of the activity of the voice subscriber to the PBX B, a similar process occurs (see above). Voice subscribers exchange information. These processes occur quickly and are not noticeable to voice subscribers.

 Thus, the data transmission channel between OOD A and B disappears, the digital communication channel contains information from voice subscribers that is random in nature and therefore, when it is received by receivers 12, they do not phase and an active signal does not appear at the output of counters 20, and therefore reception and data transfer is prohibited.

 At the end of the activity of the voice subscribers, the signal on the wire 27 disappears and an active signal appears on the output 26, which immediately sets the first and second outputs 9 to unity and the process of establishing a data transmission channel between OOD A and B occurs similarly to the above.

Claims (1)

 A voice message compression module with data packets comprising a first wire of a data terminal equipment, a line receiver, a digital channel transmitter and a first wire of a digital transmission system connected in series, the line receiver and a digital channel transmitter connected by a six-bit bus, as well as a second wire of a digital transmission system connected in series, a digital channel receiver, a linear transmitter, a second wire of data terminal equipment, the third wire of a digital transmission system with is single with the input of the receiver of the digital channel and the input of the linear transmitter, characterized in that a universal linear transceiver, first and second formers, a subscriber detector, a delay circuit, circuits I1, I2, I3, a counter, an adder are introduced as a linear receiver and a transmitter, trigger, third and fourth wires of data terminal equipment, fourth, fifth, sixth, seventh, eighth, ninth wires of a digital transmission system, wherein a first wire of data terminal equipment is connected in series A linear linear transceiver, digital channel transmitter and the first wire of a digital transmission system, where the universal linear transceiver and digital channel transmitter are connected by a nine-bit bus, in addition, the output of circuit I1 is connected to the first input of the digital channel transmitter, the first input of which is connected to the third wire of the data terminal equipment , to the second input of the digital channel transmitter is connected the first output of the first driver, the second output of which is connected with the first input of the universal linear transceiver, and the third input of the digital channel transmitter is connected to the first output of the delay circuit, the second output of which is connected to the first input of the I2 circuit, and the second wire of the digital transmission system, the digital channel receiver, the universal linear transceiver, the second wire of the data terminal equipment are connected in series, the digital channel receiver is connected to the universal linear transceiver by an eight-bit bus, while the first input of the digital channel receiver is connected to the output of the second form a transmitter, the first input of which is connected to the third wire of the digital transmission system, and the second input to the fourth wire of the digital transmission system, in addition, the first output of the digital channel receiver is connected to the first input of the adder and to the second input of the universal linear transceiver, the second output of the digital channel receiver is connected with the second input of the adder and with the first input of the trigger, the third output of the receiver of the digital channel is connected to the third input of the adder and the second input of the trigger, and the fourth output of the receiver of the digital channel the la is connected to the first input of the counter, the output of which is connected to the fourth input of the adder, the second input of circuit I1, the third input of the trigger, the second input of the receiver of the digital channel and the fifth wire of the digital transmission system, the sixth wire of which is connected to the first input of the first driver and to the second input I2 circuit, and the seventh wire of the digital transmission system is connected to the second input of the first driver, while the fourth trigger input is connected to zero potential, and its output is connected to the first input of the I3 circuit, the output of which is connected to the fourth wire of the data terminal equipment, the second input of the I3 circuit connected to the output of the subscriber detector and the input of the delay circuit, in addition, the input of the subscriber detector connected to the eighth wire of the digital transmission system, the ninth wire of which is connected to the output of the I2 circuit, and the adder output connected to the second input of the counter.

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