RU2101826C1 - Single-phase ground-fault warning device for ac mains - Google Patents

Abstract

FIELD: protection of ac mains with insulated or compensated neutral, with neutral grounded through high-value resistor, or with fully compensated single-phase ground-fault current fundamental. SUBSTANCE: device is provided with series-connected clock generator and microprocessor unit, analog-to-digital converter, main and read-only storage units, address register, controller of storage units, and digital data unit all connected to microprocessor unit through system unibus interconnecting address register output and inputs of storage units, and switch which is connected through respective switches to threshold element and signal limiter, as well as control unit with relevant connections. Device records great amount of information about processes in supply mains on occurrence of single-phase ground faults. EFFECT: improved speed of response and validity of detection of fault (selective action) in transient and steady-state ground faults, improved reliability of device. 3 wdg , 1 tbl

Description

 The invention relates to electrical engineering, in particular to the protection of electrical networks, and is intended for operation in electrical networks with isolated, compensated neutral, neutral, grounded through a high-resistance resistor, and in networks with full compensation of the fundamental harmonic of the current of a single-phase earth fault (OZZ).

 A device for automatically detecting damage to cable lines in networks of 6-10 kV type ZZAG-2, which contains a search and control unit, an executive body, including an amplifier, a comparison element and an output relay, an automatic gain control unit, as well as a matching transformer and filter industrial frequency. This device is not intended for signaling (protection against) OZZ.

 Closest to the proposed one is another device for protecting the OZZ of an alternating current electric network, including a threshold organ, a signal limiter and a key connected in series, as well as an amplifier and an actuator.

 The disadvantage of this device is the reduced speed, insufficient to obtain the necessary amount of information when monitoring several connections during fast processes (for example, transient), as well as in a limited scope only in networks with isolated neutral and neutral, grounded through a high-resistance resistor.

 The basis of the invention is the creation of such a device for signaling OZZ in an alternating current electric network, which, with increased reliability, would provide the necessary speed of information transmission and conversion, as well as increased selectivity of action.

 This goal is achieved by the fact that in the alarm device OZZ in an alternating current electric network, containing a threshold organ connected to a zero-sequence voltage transformer (TNNP) of the network, the first connected to the first zero-sequence current transformer (TTNP) of the controlled connection is a signal limiter and a key connected in series with the nth signal limiter and key connected to the nth TTNP of the corresponding controlled connection, as well as a mutator, an amplifier, and a digital indicator, each of the n outputs of the switch being connected to the control input of the corresponding key; according to the invention, a rectangular (clock) pulse generator and a microprocessor (MP) are connected in series, as well as an (n + 1) th key connected between inputs of the threshold organ and amplifier, analog-to-digital converter (ADC), control unit (CU), random access memory (RAM), read-only flash memory (ROM), address register (RA), memory controller their devices (KZU), digital display unit (CBI), bus and system lines, and the control input of the (n + 1) -th key is connected to the (n + 1) -th output of the switch, the second outputs of all keys are combined and connected to the input an amplifier, the output of which is connected to the first input of the ADC, the first output of the RA through the bus line is connected to the first inputs of the ROM, RAM and switch, the second input of which is connected to the output of the threshold organ, the system line is connected to the first outputs of the ADC and ROM, with the first inputs of the RA, KZU, CBI, with outputs / inputs of MP and RAM, ne the output of the MP “Data Reading” is connected to the first input of the control unit and the second inputs of the ROM and RAM, the second output of the MP “Data Recording” with the second inputs of the control unit, ROM and the third input of the RAM, the third output of the MP “Exchange” with the third input of the control unit, the fourth input KZU and the second input of the RA, the fourth output of the MP "Byte-by-write" with the fifth input of the RAM, the fifth output of the MP "Installing external devices" with the second input of the CBI, the second output of the RA connected to the fourth input of the control unit, and the third output of the RA to the sixth input of the KZU, the first the output of the latter is connected to the third RAM input, the second output to the third ROM input, WTO the input of the MP "Response" is connected to the outputs: the first control unit and the third short-circuit memory, the second output of the control unit is connected to the second input of the ADC "Read permission", the third output of the control unit with the third input of the ADC "Launch ADC", the fourth output of the control unit with the third input of the pulsed circuit board, and the fifth input of the control unit with the second output of the ADC "Ready", the output of the central circuit is connected to the input of a digital indicator.

 A distinctive feature of the invention is the introduction of digital microprocessor units, storage devices, address registers, etc. which made it possible to record a large amount of information about processes in electronic form at high speed. networks in case of acute spinal cord disease and significantly increase the selectivity of determining the damaged connection.

 The threshold organ responds to alternating voltage and can be made in the form of a series-connected rectifier, comparator and RS-trigger.

 Signal limiters are designed to protect the inputs of the device from overvoltage and can be made in the form of a chain resistor two-sided zener diode, and the output signal is removed from the zener diode.

 The MP is the main control and computing unit in the alarm device; as the MP, the N1806BM2 chip with a start-up circuit can be used.

 As a voltage switch, ADC, RA, and CBI, microcircuits can be used, respectively 590 КНЗ, К1108ПВ1А, КР533ИР22 (23) and 514ПР1.

 KZU is a signal sampling circuit assembled on a K588VG2 microcircuit [3, p. 223-225] RAM and ROM can be implemented on the chips KR537RU8A, KS573RF2.

 CBI is a code converter having an input for resetting information connected to the corresponding output of the MP.

 In FIG. 1 shows a functional diagram of the device; in FIG. 2 is a functional diagram of a memory controller (RAM); in FIG. 3 is a functional diagram of a control unit (CU).

 To the transformer 1 voltage zero sequence (TNNP) network connected threshold organ 2 (Fig. 1). The first signal transformer 3 of the zero sequence (TTNP) of the controlled connection is connected in series to the first signal limiter 4, key 5, amplifier 6 and analog-to-digital converter (ADC) 7.

 To the nth TTNP of the 8th controlled connection, respectively connected in series are the nth limiter 9 of the signal, the key 10, the second output of which is connected to the same input of the amplifier 6. Resistors R having low resistance are connected to the secondary windings of the TTNP. The input of the threshold organ 2 through the key 11 is also connected to the input of the amplifier 6. The circuit has a switch 12, the first, nth and (n + 1) -th outputs of which are connected to the control inputs of the keys, respectively, 5, 10 and 11.

 The output of the threshold organ 2 is connected to the (n + 2) -th input of the switch 12.

 The circuit has a series-connected generator 13 of rectangular (clock) pulses and a microprocessor (MP) 14, as well as a digital display unit 15 (CBI), the output of which is via a bus (multi-wire) highway connected to the input of a digital indicator 16. The circuit also has an address register (RA) 17, random access memory (RAM) 18, permanent (reprogrammable) memory (ROM) 19, memory controller 20 (RAM), control unit 21 (CU) and system (bus) trunk (SM) 22 for transmission addresses and data. In this case, the output of RA 17 through its bus line 23 is connected to the first inputs of the voltage switch 12 and memory devices 19 and 18.

 The corresponding inputs / outputs MP14 through SM 22 are connected to the first outputs of the ADC 7, ROM 19, the first inputs of RA 17, KZU 20, CBI 15, inputs / outputs of RAM 18. The first output of RA 17 through the bus line 23 is connected to the first inputs of ROM 19, RAM 18 and voltage switch KN 12. The second input of the latter is connected to the output of the threshold organ 2, and the (n + 1) -th output to the control input of the key 11.

 The first output of MP14 "Data Reading" (DCHT) is connected to the first input of the control unit 21 and the second inputs of the RAM 20, RAM 18. The second output of the MP 14 "data recording" (DZP) is connected to the second input of the control unit 21, ROM 19 and the third input of KZU 20 The third output of the MP 14 "Exchange" (OBM) is connected to the third input of the BU 21, the fourth input of the KZU 20 and the second input of the RA 17. The fourth output of the MP 14 "Byte-by-write" (PZP) is connected to the fifth input of the KZU 20.

 The fifth output of MP 14 “Installing external devices” (IAC) is connected to the second input of the central computer 15. The second output of RA 17 (for example, the 5th digital word digit) is connected to the fourth input of the control unit 21, and the third output (for example, the 12th digital word category) to the sixth input of the RAM 20. The first output of the latter is connected to the third input of the RAM 18, the second output with the third input of the ROM 19.

 The second input of MP 14 "Answer" is connected to the outputs of the first BU 21 and the third short-circuit amplifier 20. The second output of BU 21 is connected to the second input of the ADC "Read permission", the third output with the third input of the ADC "Launch ADC", the fourth output with the third input of the pulsed circuit board 15 , and the fifth input of BU 21 with the second output of the ADC "Ready". The output of the CBI 15 is connected to the input of a digital indicator 16.

 Functional diagram of the RAM 20 (Fig. 2) contains a chip (MS) 24 memory controller and four logical elements And 25-28, with four address output of the MS 24 connected to the first input, the conclusions of the DCT, DZP, OBM and PZP are connected respectively to the inputs 2-5. The first inputs of the elements And 25, 26 and 28 are connected to the sixth input. The first output of the MS 24 is connected to the second input of the And 25 element, and its second output with the second inputs of the And 26 and 27 elements. The output of the And 28 element is connected to the second input of the And 27 element The 1st, 2nd and third outputs of the short circuit switch 20 are connected respectively with the outputs of the third MS 24, the outputs of the elements And 25 and 26 and the output of the element And 27.

и ПЗП в зависимости от их сочетания (см. таблицу) переключают выходные сигналы МС 24.If the code at the AD input (bits 0, 13, 14, 15 from the system bus) matches the units at input A, the input signals

and PZP, depending on their combination (see table) switch the output signals of the MS 24.

 In table X, it means any value (0 or 1) of a logical signal. Output 1 gives the response (OTV) MP 14 after the execution of the command. Thanks to the logical elements And 25-28 provides the writing and reading of RAM data 18 (elements And 25 and 26) output 2 of the RAM 20. In this case, the logical "0" at the output of the logical element And 25 determines the low byte, and the output of the logical element 26 high byte data. At the output 1 of the KZU 20, an OTF MP 14 signal is issued. A signal (low level) at the output of the ZKZU 20 provides read data from the ROM 19.

 Functional diagram BU 21 (Fig. 3) contains a 2 x 2 AND 29 chip with a control input, D trigger 30 and 2 logic elements OR 31, 32, with the first inputs connected to the first inputs of the first AND element of the chip 29 and the OR element 31, output which is connected to the R-input of the D-flip-flop 30. The first input of the 2nd element And microcircuit 29 is connected to the second input of the control unit, the second inputs of both elements And microcircuit 29 are connected to the third input. The control input (two bits) of the microcircuit 29 is connected to the fourth input of the control unit . The C-input of the D-flip-flop 30 is connected to the fifth input of the control unit. The first output of the microcircuits S 29 is connected to the second output of the control unit, the second with the fourth output of the control unit and to the first input of the element 32, the output of which is connected to the first output of the control unit. The third output of the microcircuit 29 is connected to the third output of the control unit, and the output of the D-trigger to the second input of the OR element 32.

 Chips (KR15ZZ IDCH) are a dual decoder / demultiplexer. Schemes And it are permissive inputs, and AO and A1 control. AO receives a signal of the 5th grade of RA 17, and to A1 a signal of coincidence of the signals of 9th, 13th, 14th, 15th bits of the RA 17. The state of the signals of AO and A1 is indicated at the outputs of the microcircuit 29 (Fig. 3). From the first output of the control unit 21 receives a response signal (OTV) MP 14 about the execution of the command. From the second output the signal “ADC start” is received, from the third “ADC read permission”.

 The signal from the fourth output ensures the recording of the code in the buffer registers of the CBI 15, so that the corresponding digits on the indicator 16 will display the number of the monitored connection until a new signal arrives from output 4 of the control unit 21.

 The operation of the device.

In normal network mode, the voltage U _o at the input of the threshold organ 2 is small and at the output its logical signal is zero, switch 2 is blocked. Keys 11, 5 and 10 are open. There is no information on indicator 16.

для каждого входного сигнала, где Δt время преобразования АЦП 7 и записи в ОЗУ 18 принято равным 0,01 мс.When OZZ in the network, the neutral voltage U _o exceeds the setting 0.3U _{f of} threshold organ 2, the logical unit appears at the output of the latter and allows the switch 12 to work. The MP operates in accordance with the program recorded in the ROM 19. First, it affects KN through RA 17 12, ensuring the closure of the key 11. Then, through the control unit 21, it sends to the control inputs of the ADC 7 the signals "Permission to read" and "Start". The ADC 7 generates a signal "Ready" on the BU 21, which gives a signal to the input of the MP 14 "Response". The latter issues commands through the RA 17, the RAM 20 and directly to the RAM 18 and the information from the ADC 7 output to the specified address through the CM 22 is transmitted and recorded in the RAM 18. Further, the MP 14 through the RA 17 provides the opening of the key 11 and the closure of the key 5, the described process repeated with a change in the addresses of the RAM cells 18, where information is recorded from the ADC 7, etc. MP 14 provides a record in RAM cells 18 of information about the levels of input signals, starting with key 11, then 5, 10 and then cyclically for one period T of industrial frequency (20 ms). For example, with m 10 output signals in 20 ms, the number of points

for each input signal, where Δt is the ADC conversion time 7 and write to RAM 18 is taken equal to 0.01 ms.

 Further, MP 14, in accordance with the program recorded in the ROM 19, begins to process the information stored in the RAM 18.

For example, the differences of neighboring numbers (points) of each of the joins are determined, all the received differences are assigned positive signs. The obtained values are summed for each of the current inputs (5-10), these amounts are compared. The damaged connection is the largest and the number of this connection lights up on indicator 16. The first input (key 11) is needed when processing the transient components of the voltage U _o and the currents of the connections I _oi to determine the damaged connection.

 The device has high speed and selectivity, information retrieval time of 20 ms and its processing of 100 ms.

 A device for signaling a single-phase earth fault in an alternating current electric network according to the invention can be successfully used in 6-35 kV electric networks of industrial enterprises in cities and agriculture. These networks can have any applicable neutral mode, and also contain systems for compensating the fundamental harmonic of the OZZ current.

 The use of the device allows you to automatically detect a damaged connection (with OZZ) at a substation or power station and eliminates the need for short-term disconnection of connections for this purpose.

 Tests of the proposed device in a 6 kV network showed its effective operation and the possibility of application in email. networks with a voltage of 6-35 kV with any neutral mode, including networks with compensation of the fundamental harmonic of the OZZ current.

 Using the device provides both economic and social positive effects.

Claims (1)

 A device for signaling a single-phase earth fault in an alternating current electric network, containing a threshold organ connected to a zero-sequence voltage transformer (TNNP), a signal limiter and a key connected to the first TTNP of a controlled connection in series, and a key connected in series with the nth connected to n -mu TTNP of the corresponding controlled connection, a signal limiter and a key, as well as a voltage switch, amplifier and digital indicator, and each of the n outputs of the voltage switch is connected to the control input of the corresponding key, characterized in that it is connected to a series-connected generator of rectangular (clock) pulses and a microprocessor (MP), as well as the (n + 1) -th key connected between the inputs of the threshold organ and an amplifier, an analog-to-digital converter (ADC), a control unit (CU), including a 2x2I microcircuit (MS 2x2I) with a control input, a D-trigger, OR or NOT logic elements, random access memory (RAM) and permanent programmable memory a memory device (EPROM), an address register (RA), a memory controller (RAM), including a signal sampling chip (MVS), three logical elements AND, and a logical element NOT, a digital display unit (CBI), a bus and system bus, the control the input of the (n + 1) -th key is connected to the (n + 1) -th output of the voltage switch, the second outputs of all the keys are combined and connected to the input of the amplifier, the output of which is connected to the first input of the ADC, the first input of the RA through the bus line is connected to the first the inputs of the ROM, RAM and switch voltage the second input of which is connected to the output of the threshold organ, the system trunk is connected to the first outputs of the ADC and EPROM, the first inputs of the RA, CBI, four address outputs of the MVS KZU, with the outputs / inputs of the MP and RAM, the first output of the MP "Data Reading" (DCHT ) is connected to the first input of the first element And the MS 2x2I and the input of the element NOT BU, the second input of RAM, the output of the MBM MVS KZU, the second output of the MP "Data Record" (DZP) with the second input of the ROM, the first input of the second element And the MS 2x2I BU and the output DCT MVS KZU, the third output of the MP "Exchange" (OBM) with the second inputs of both elements NTV and MS 2x2I BU, with the output of the DZP MVS KZU and the second input of the RA, the fourth output of the MP "Byte-by-write" (PZP) with the output of the PZP MVS KZU, the fifth output of the MP "Install external devices" with the second input of the CBI, the second output of the RA is connected to the control the input (two bits) of the MC 2x2I control unit, and the third output of the RA to the second inputs of the first and second logic elements AND and the input of the logic element NOT short circuit, the outputs of the first and second logic elements AND short circuit are connected to the third input of RAM, the output of the third logical element AND short circuit is connected with the third input of the ROM, the second input of the MP "Response" connected to the output of the logic element OR control unit and the third output of the MVS KZU, the first output of the MC 2x2I control unit is connected to the second input of the ADC "launch ADC", the third output of the MC 2x2I control unit with the third input of the ADC "read permission", the second output of the MC 2x2I control unit with the third input CBI, and the C-output of the D-flip-flop BU with the second output of the ADC “Ready”, the output of the CBI is connected to the input of the digital indicator, the first output of the MVS KZU is connected to the first input of the first logical element AND the short-circuit memory, and the second output of the MVS with the first inputs of the second and third logic gates AND short circuit, output logic gates the one which is NOT connected to the second input of the third logic element AND short circuit breaker, the output of the logical element NOT control unit is connected to the R-input of the D-trigger, the second output of the MC 2x2I control unit is connected to the first input of the logic element OR control unit, the second input of which is connected to the output of the D-trigger BOO.

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