RU2090959C1 - Self-phasing antenna array - Google Patents

Abstract

FIELD: antenna equipment, communication systems including mobile ones used under complex interference conditions. SUBSTANCE: self-phasing antenna array has reception channel including row of antenna elements, former of summary signal, phase inverters and power dividers placed between outputs of antenna elements and inputs of former. Control channel of antenna array incorporates discrete phase inverter and multiinput commutator connected to separate outputs of power dividers. Outputs of discrete phase inverter and commutator are connected through adder to network composed of amplitude detector, analog-to-digital converter, computation and control unit and former of controlling code connected in series. Outputs of former of controlling code are connected to controlling inputs of discrete phase inverter, commutator and controlled phase inverters. EFFECT: improved operational stability. 1 dwg

Description

 The invention relates to antenna technology and can be used in communication systems, including to ensure stable communication in a complex jamming environment with mobile corresponding points.

 Self-phasing is such an antenna array in which each antenna element has independent phasing, determined by the information contained in the signal received by this antenna element / 1 /. In this case, the entire antenna array is phased so that the maximum power of the received useful signal is obtained at its output. Potentially, such a lattice is capable of tuning to the signal source in a short period of time, compensating for the time delays of the signal caused by changes in the conditions of its propagation or the position of elements.

 Known / 1 / is a self-phasing receiving antenna array containing n connected in series elements, n controlled phase shifters and n phase detectors, to the reference inputs of which a reference signal generating unit is connected, as well as a sum driver, the output of which is the output of the array. For each phase detector, the signal output is connected to the corresponding input of the sum shaper, and the control output is connected to the control input of the controlled phase shifter connected in series to it.

 The disadvantages of the antenna array are due to the complexity of the distribution of reference signals with a coherent phase between spaced receiving elements. The phase coherence of the reference signals, depending on its degree, can lead to significant phasing errors in the elements of the antenna array. In addition, the block forming the reference signal included in the grating requires adaptation to the frequency of the received radiation, which complicates the process of self-phasing.

 Also known / 2 / is a self-phasing antenna array containing n receivers in series, n mixers, to the other inputs of which are connected phase shifters, a sum and difference signal generating unit and intermediate frequency amplifiers of the sum and difference channels, as well as three multipliers with bandpass filters, information extraction unit, auto-loop according to the angular position of the incoming signal, auto-loop of the total signal by delay, auto-loop ummarnogo signal and the reference quadrature oscillator oscillations. In this case, the information extraction unit is made in the form of a series-connected synchronous detector, a matched filter, and a decoder. The auto-loop for the angular position of the incoming signal contains a first phase detector and a driver for the control code, the outputs of which are connected to the control inputs of the phase shifters. The auto-tuning loop of the total delay signal includes a second phase detector, a clock and a functional generator. The auto-frequency loop of the total signal contains a demodulator, a third phase detector and a controlled oscillator connected to the inputs of the phase shifters. The output of the quadrature reference oscillator is connected to the control inputs of the third phase detector and synchronous detector.

 The main disadvantage of the lattice is due to the complexity of its functional circuit, which leads to a high probability of loss of performance in the event of failure of at least one of the control loops. The presence of several generators in the grid makes it difficult to synchronize the operation of the entire device as a whole. Along with this, a priori knowledge (exact or approximate) of the frequency of the incoming electromagnetic radiation is necessary, which determines the operation mode of the quadrature reference oscillator, which complicates the process of self-phasing.

 As a prototype, a self-phasing antenna array / 3 / is selected that contains a receiving channel, including a number of antenna elements, a signal shaper, the output of which is the output of the array, and series-connected controlled phase shifters and power dividers connected between the respective outputs of the antenna elements and the inputs of the signal shaper, as well as a control channel made in the form of series-connected phase and amplitude detection unit, analog-to-digital conversion of Tell, a specialized processor, a control processor and a phase shift controller, the outputs of which are connected to the control inputs of the phase shifters, wherein the second outputs of the power dividers are connected to the inputs of unit amplitude and phase detection.

 In this device, the control channel operates as follows. The signals from the outputs of the antenna elements receive certain phase shifts, passing through the phase shifters, and then through the power dividers are fed to the input of the amplitude and phase detection unit. Then, the analog-to-digital converter converts the detected signals to digital form, after which they enter the input of a specialized processor. A dedicated processor generates a noise digital signal, adding a certain shift to the phase of each input signal. After that, he calculates the correcting values of the phase settings based on the phases and amplitudes of both the input and noise signals so that the ratio of the signal to the sum of the desired received wave and internal noise is maximum. The calculated values of the phase settings are transmitted to the control processor, which generates control codes for the phase shift controller, which ensures the installation of the necessary phase shifts in the phase shifters.

 The main disadvantage of the prototype, which is also inherent in analogues, is due to the fact that in it the phasing of elements is carried out on the basis of phase measurements of the received signals carried out in the control channel. The complexity of the hardware of these measurements with the necessary accuracy entails a decrease in the power of the received useful signal due to the out-of-phase summation of the signals from individual elements and, thus, a decrease in the noise immunity of the antenna array.

 The objective of the invention is to create a self-phasing antenna array with increased noise immunity and a simplified design.

 In accordance with the task, the claimed self-phasing antenna array, as well as the prototype array, contains a control channel and a receiving channel, which includes a number of antenna elements, a signal shaper, the output of which is the output of the array, and included between the output of each antenna element and each individual input shaper of the total signal in series connected controlled phase shifter and power divider. The control channel includes a series-connected amplitude detector and an analog-to-digital converter.

 Unlike the prototype, the lattice additionally contains a discrete phase shifter, a multi-input switch, an adder, and a series-connected calculation and control unit and a control code generator. In this case, a discrete phase shifter is connected between the individual output of one of the power dividers and the first input of the adder, a multi-input switch is connected between the individual outputs of the remaining power dividers and the second input of the adder, the output of which is connected to the input of the amplitude detector, the output of the analog-to-digital converter is connected to the input of the calculation unit and the control and individual outputs of the control code generator are connected to the control inputs of the discrete phase shifter, multi-input switch, and controlled azovraschateley.

 Since in the control channel of the inventive self-phasing antenna array there is no multifunctional means for generating an intentional noise digital signal, this simplifies the design of the array.

 It is significant that in the control channel of the inventive array, the process of calculating the phase shifts required for the controlled phase shifters is implemented based on the measured amplitudes of the received signals. Since amplitude measurements are simpler and more accurate in comparison with phase measurements, this ultimately leads to a more accurate phasing of the antenna elements and, therefore, increases the noise immunity of the antenna array by increasing the power of the received useful signal.

 The drawing shows a structural electrical diagram of a self-phasing antenna array.

 The grating contains a receiving channel, including a series of N antenna elements 1, to the output of each of which are connected in series connected controlled phase shifter 2 and power divider 3. The outputs of the power dividers 3 are connected to the individual inputs of the shaper 4 of the total signal, the output of which is the output of the antenna array.

 The lattice control channel includes a discrete phase shifter (DF) 5, a switch 6 and a series-connected adder 7, an amplitude detector 8, an analog-to-digital converter (ADC) 9, a calculation and control unit (BVI) 10, and a control code generator 11. The input of DF 5 is connected to a separate output of one of the power dividers 3, the individual outputs of the remaining power dividers 3 are connected to separate inputs of the switch 6, the outputs of the DF 5 and switch 6 to the inputs of the adder 7, and the individual outputs of the shaper 11 of the control code to the control inputs of the controlled phase shifters 2 , DF 5 and switch 6.

 The functions of a BVI can be performed, for example, by a personal computer such as IBM PC. Shaper 11 of the control code can be performed based on a set of current keys. In particular, the authors used analog integrated circuits of the K170AP2 / 4 / series as current keys.

 As an ADC 9, any of domestic or foreign ADCs that are hardware compatible with an IBM PC type computer can be used. In particular, the authors used a serial-produced ADC type ADC 12 / 2-80.

 Each of the controlled phase shifters 2 can be performed, for example, in the form of a set of several delay lines / 5 /, the number of which can be specified based on the requirements for the accuracy of the installation of phase shifts realized by these phase shifters. So, in the model of the four-element grating made and tested by the authors, this number was 9.

 The switch 6 can be performed on a printed circuit board in strip design / 6 /.

 DF 5 should provide, depending on the state in which it is located, receiving through it a signal of three values of phase shifts. Structurally, it is most simple to perform DF 5 with phase shifts of 0, π / 2, π. The procedure for calculating and constructing such discrete phase shifters is described, for example, in / 7 /.

 Shaper 4 of the total signal was completely made on the basis of the design solution described in / 7 /.

 The adder 7 was completely made on the basis of the design solution described in / 7 /.

 The operation of the self-phasing antenna array includes the sequential execution of three modes: receiving input information, calculating the current values of the required phase shifts for the controlled phase shifters 2, and generating a state control code for these phase shifters.

Prior to the start of receiving input information on the first controlled phase shifter, a constant phase shift Φ _{1 is} established using a former 11 using a shaper 11.

(n 2, N) поступает на вход сумматора 7. Здесь А_n амплитуда сигнала, Φ_n его фаза. Одновременно комплексный сигнал

с выхода ДФ 5, находящегося в исходном состоянии, поступает на другой вход сумматора 7. В результате сложения сигналов сумматором 7 на его выходе создается сигнал с амплитудой:

Этот сигнал детектируется амплитудным детектором 8 и затем поступает на вход АЦП 9. АЦП 9 преобразует этот сигнал в цифровую форму, после чего значение сигнала считывается БВУ 10 и записывается в его оперативном запоминающем устройстве (ОЗУ).In the mode of receiving input information on the commands coming from the BVI 10, the shaper 11 sequentially generates three codes e ⁽¹⁾ , e ⁽²⁾ , e ^{(3) for} controlling the DF 5 and switch 6. Each code is fed simultaneously to the control inputs of the DF 5 and switch 6. Upon receipt of the code e ⁽¹⁾ , the switch 6 is connected to the output of the nth power divider 3. In this case, the signal with complex amplitude

(n 2, N) is fed to the input of the adder 7. Here, And _{n is the} amplitude of the signal, Φ _n its phase. At the same time complex signal

from the output of the DF 5, which is in the initial state, it goes to another input of the adder 7. As a result of the addition of signals by the adder 7, a signal with an amplitude is created at its output:

This signal is detected by the amplitude detector 8 and then fed to the input of the ADC 9. The ADC 9 converts this signal to digital form, after which the signal value is read by the BWC 10 and recorded in its random access memory (RAM).

. В то же время сохраняется подключение коммутатора 6 к выходу n-го делителя 3 мощности. В результате на выходе сумматора 7 формируется сигнал:

который детектируется амплитудным детектором 8 и затем преобразуется АЦП 9 в цифровую форму и записывается в ОЗУ БВУ 10.Upon receipt of the code e ^(2), DF 5 goes into a state that ensures that the signal E ₁ receives an additional phase shift ΔΦ, i.e. adder 7 now receives a signal

. At the same time, the connection of the switch 6 to the output of the nth power divider 3 is maintained. As a result, at the output of the adder 7, a signal is generated:

which is detected by the amplitude detector 8 and then converted by the ADC 9 into digital form and recorded in the RAM of the BVU 10.

записывается в ОЗУ БВУ 10.Upon receipt of the code e ^(3), DF 5 enters a state that ensures that signal E ₁ receives an additional phase shift of 2ΔΦ. The connection of switch 6 remains unchanged. As a result, the digital value of the signal:

is written in the RAM of the BVU 10.

Требуемые значения фазовых сдвигов представляют собой взятую с обратным знаком разность Φ_n- Φ₁.After a complete cycle of receiving input information from all antenna elements in the RAM of the second-tier bank 10, three arrays of numbers will accumulate U _1n } U _2n } U _3n }
In the mode of calculating the current values of the required phase shifts for the controlled phase shifters 2, the BVU 10 sequentially selects from RAM three numbers U _1n , U _2n , U _3n (n 2, N) and calculates the values Φ _n - Φ ₁ ∈ (-π, π] according to the formula:

The required values of the phase shifts are the difference Φ _n - Φ ₁ taken with the opposite sign.

In the mode of generating the control code by commands from the BVI 10, the shaper 11 generates a control code, when applied to the control inputs of the phase shifters 2, the latter go into a state that ensures phase shifters introduce phase shifts ΔΦ = - (Φ _n -Φ ₁ ), n 2, N. At the same time, N common-mode signals are supplied to the inputs of the sum shaper 4 of the total signal, which ensures that the maximum power of the received useful signal and, therefore, the maximum signal-to-noise ratio are obtained at the output of the antenna array. Changing the conditions for the propagation of radiation from the source and / or its spatial position will cause a phase outage of the signals at the inputs of the shaper 4 of the total signal and the generation in the control channel of the values of the required phase shifts for the phase shifters 2. This ensures that the maximum signal / noise ratio at the output of the antenna array is provided.

Compared with the prototype of the inventive self-phasing antenna array has:
1) better noise immunity;
2) simpler construction.

 The operability of the self-phasing antenna array and its advantages compared with the prototype array were confirmed by tests of a four-element array prototype manufactured at the Siberian Institute of Physics and Technology.

Sources of information
1. Hansen R.S. Microwave Scanning Antenna Systems. Per. from English / Ed. G.T. Markov and A.F. Chaplin. T. 3. M. Sov. radio, 1971, p. 383-452.

 2. Copyright certificate of the USSR N 780769, cl. H 01 Q 21/06, publ. in BI, 1986, N 28.

 3. Japanese application N 63-208306, cl. H 01 Q 3/26, publ. 08/29/1988 (prototype).

 4. Gorshkov B.I. Elements of electronic devices. Directory. M. Radio and Communications, 1988.

 5. Antonov A. V. Gerasimov Yu.M. Gridin A.A. Prokhorov S.A. High-speed discrete controlled RF attenuators and phase shifters for adaptive antenna array. On Sat Marine Radio Communication, 1985, p. 88-96.

 6. Karpov V.M. Malyshev V.A. Perevoshchikov I.V. Broadband microwave devices on elements with lumped parameters. M. Radio and Communications, 1984.

 7. Brook Yu.M. Gordienko T.A. Ermakov V.Yu. Mikhailov V.S. Sodin L.G. Broadband elements of phased array antennas (preprint N 131). Kharkov: IRE AN USSR, 1979.

Claims (1)

 A self-phasing antenna array containing N antenna elements, a signal shaper, the output of which is the output of the array, connected between the output of the i-th antenna element and the i-th input of the signal shaper, a controllable phase shifter and a power divider, as well as an amplitude detector connected in series and an analog-to-digital converter, characterized in that it additionally includes a discrete phase shifter, a multi-input switch, an adder and sequentially connected to the calculation and control unit and the driver of the control code, while the input of the discrete phase shifter is connected to the second output of one of the power dividers, the second outputs of the remaining power dividers are connected to the inputs of the multi-input switch, the output of the digital phase shifter is connected to the first input of the adder, and the output of the multi-input switch to the second the adder input, the adder output is connected to the input of the amplitude detector, the output of the analog-to-digital converter is connected to the input of the calculation and control unit lines, and the outputs of the control code generator are connected to the control inputs of the discrete phase shifter, multi-input switch, and controlled phase shifters.