RU2090927C1 - Method for identifying objects by their outline - Google Patents

Abstract

FIELD: automatic control and computer engineering; computer vision systems of robotic weapon complexes. SUBSTANCE: method involves rejection of separated outline from storage until object image identical to reference image in outline appears in photocells of image processing matrix as result of search of desired object or system reconnaissance target incorporating this device. EFFECT: enlarged functional capabilities. 2 cl, 5 dwg

Description

 The invention relates to automation and computer technology and can be used for automatic recognition of images of objects in vision systems of robotic weapons systems.

 A device for highlighting the image contour (A.S. N 1141429, class G 06K 9/00, 1983), containing a matrix of image processing cells, each of which consists of a memory element, a photodetector element, the first element And, the first input of which is connected with the output of the photodetector element, and the output is connected to the input of the memory element, the NAND element, the inputs of which are connected to the corresponding photodetector elements of adjacent cells, and the output is connected to the second input of the first element I.

 This device has a low accuracy.

 Closest to the invention is a device (AS No. 1257674, class G 06K 9/00, 1986) containing a matrix of image processing cells, each of which consists of a memory element, a photodetector element, three elements AND, an element NOT, an element AND AND AND AND NOT.

 The aim of the invention is to expand the conditions of use of the device by recognizing the allocated image contour.

из которых соединены с выходами третьих элементов И ячеек обработки изображения, расположенных вдоль одной, l-ой, строки матрицы ячеек обработки изображения, а входы соединены общей шиной, генератор синхроимпульсов, делитель частоты, первый счетчик, первый декодер/демультиплексор, информационный вход которого подключен к выходу генератора синхроимпульсов, выходы, кроме последнего, подключены к управляющим входам коммутаторов, а адресный вход соединен с выходом первого счетчика, вход которого подключен к выходу делителя частоты, вход которого подключен к выходу генератора синхроимпульсов, второй счетчик, управляющий вход которого подключен к выходу делителя частоты, третий счетчик, второй и третий декодеры/демультиплексоры, адресные входы которых соединены с выходом третьего счетчика, вход которого соединен с выходом общей шины блока коммутаторов, причем информационный вход второго декодера/демультиплексора соединен с выходом первого счетчика, а информационный вход третьего декодера/демультиплексора соединен с выходом второго счетчика, вход которого подключен к выходу генератора синхроимпульсов, блок регистров адреса, состоящий из n регистров с управляющими входами, подключенными к общей шине, соединенной с последним выходом первого декодера/демультиплексора, блок распознавания контура, который содержит 2(2n-1) вычислителей, 2(2n-1) квадраторов, 2n-1 сумматоров, 2(n-1) делителей, 2(n-1) вторых вычислителей, 2(n-1) регистров эталона, 2(n-1) пороговых элементов, n-1 элементов И-НЕ, входы каждого i-го, где

, из которых подключены к выходам 2i-го и (2i-1)-го пороговых элементов, выходы которых подключены к выходам вторых вычитателей, а входы каждого j-го, где

, второго вычитателя подключены к выходам j-тых делителя и регистра эталона, управляющий вход которого соединен с выходом делителя, причем первые входы каждых (2i-1)-го и 2i-го делителей подключены к выходу 2(i-1)-го квадратора, а вторые входы подключены к выходам соответственно 2i-го и (2i+1)-го квадраторов, причем вход каждого квадратора подключен к выходу k-го, где

сумматора, причем входы каждого k-го из сумматоров соединены с выходами соответственно k-го и (k+2n-1)-го первых вычитателей, а входы каждого (2i-1)-го, соответственно 2(i+n+1)-го, первого вычитателя соединены с выходами i-го и (i+1)-го, соответственно (i+n)-го и (i+n+1)-го регистров, а входы каждого 2i-го, соответственно (2i+2n-1)-го, первого вычитателя соединены с выходами i-го и (i+2)-го, соответственно (i+n)-го и (i+n+2)-го регистров, причем вторые входы 2(n-1)-го и (2n-1)-го, соответственно (4n-3)-го и 2(2n-1)-го первых вычитателей, первые входы которых соединены с выходами (n-1)-го и n-го, соответственно (2n-1)-го и 2n-го регистров подключены к выходу первого, соответственно (n+1)-го регистра, а входы каждого i-го и n-го, соответственно (i+n)-го и 2n-го регистров подключены к выходам второго, соответственно третьего декодера/демультиплексора.This goal is achieved in that the device further comprises a block of switches consisting of N switches, information inputs of each l-th, where

of which are connected to the outputs of the third elements AND image processing cells located along one lth row of the matrix of image processing cells, and the inputs are connected by a common bus, clock generator, frequency divider, first counter, first decoder / demultiplexer, the information input of which is connected to the output of the clock generator, the outputs, except the last, are connected to the control inputs of the switches, and the address input is connected to the output of the first counter, the input of which is connected to the output of the frequency divider, the input to the second counter, the control input of which is connected to the output of the frequency divider, the third counter, the second and third decoders / demultiplexers, the address inputs of which are connected to the output of the third counter, the input of which is connected to the output of the common bus of the switch unit, and the information the input of the second decoder / demultiplexer is connected to the output of the first counter, and the information input of the third decoder / demultiplexer is connected to the output of the second counter, the input of which is connected to a clock generator, an address register block consisting of n registers with control inputs connected to a common bus connected to the last output of the first decoder / demultiplexer, a loop recognition unit that contains 2 (2n-1) computers, 2 (2n-1) quadrators, 2n-1 adders, 2 (n-1) dividers, 2 (n-1) second calculators, 2 (n-1) reference registers, 2 (n-1) threshold elements, n-1 AND-NOT elements, inputs of each i-th, where

of which are connected to the outputs of the 2nd and 2nd (1) threshold elements, the outputs of which are connected to the outputs of the second subtractors, and the inputs of each jth, where

, the second subtractor is connected to the outputs of the j-th divider and the reference register, the control input of which is connected to the output of the divider, and the first inputs of each (2i-1) and 2i-th dividers are connected to the output of the 2 (i-1) -th quadrator , and the second inputs are connected to the outputs of the 2nd and 2nd (2i + 1) -th quadrators, and the input of each quadrator is connected to the output of the kth, where

adder, and the inputs of each k-th of adders are connected to the outputs of the k-th and (k + 2n-1) -th first subtracters, and the inputs of each (2i-1) -th, respectively 2 (i + n + 1) of the first, first subtractor are connected to the outputs of the i-th and (i + 1) -th, respectively (i + n) -th and (i + n + 1) -th registers, and the inputs of each 2i-th, respectively (2i + 2n-1) -th, the first subtractor is connected to the outputs of the i-th and (i + 2) -th, respectively (i + n) -th and (i + n + 2) -th registers, and the second inputs are 2 ( n-1) -th and (2n-1) -th, respectively (4n-3) -th and 2 (2n-1) -th first subtracters, the first inputs of which are connected to the outputs of the (n-1) -th and n from accordingly, the (2n-1) -th and 2n-th registers are connected to the output of the first, respectively (n + 1) -th register, and the inputs of each i-th and n-th registers, respectively (i + n) -th and 2n- th registers are connected to the outputs of the second, respectively third decoder / demultiplexer.

 In FIG. 1 shows a block diagram of a device; figure 2 diagram of the cell image processing; figure 3 circuit block recognition circuit; figure 4 connection diagram of registers, subtractors and dividers; 5 is an example of an image contour.

The following notation is accepted:
n the number of registers for storing the address of the photocells, the location of which coincides with the location of the inflection points of the contour of the image of the object in the plane of the matrix of photocells, while the address means the number equal to the number of the corresponding row (column) of the matrix;
N is the number of photocells along the row (column) of the matrix of photocells (image processing cells), while it is believed that the matrix is square.

 The device consists of a matrix of 10 cells 10-1 image processing, each of which contains (see figure 2) a photodetector element 10-2, the first 10-3, the second 10-4, the third 10-5 elements And, the element AND 10-6, memory element 10-7, AND-OR element 10-8, and the element NOT 10-9, generator 20 clock pulses (GPS), the first 30, second 40 and third 50 counters, frequency divider 60, block 70 switches containing N switches 70-1, 70-2, 70 N, the first 80, the second 90 and the third 100 decoders / demultiplexers, the first 110 and second 120 blocks of address registers, which are actually constructively units another block of 2n registers, however, for the convenience of describing the operation of the device, conventionally divided into two blocks containing (see Fig. 3.4) each of n registers 110-1 110-n and 120-1 120-n, respectively, and block 130 recognition circuit containing 2 (2n-1) first subtractors 130-1, 2 (2n-1) quadrants 130-2, 2n-1 adders 130-3, 2 (n-1) dividers 130-4, 2 (n- 1) second subtractors 130-5, 2 (n-1) registers 130-6 reference, 2 (n-1) threshold elements 130-7, n-1 elements AND-NOT 130-8 (see Fig.3,4).

 The operation of the device begins with the “Install” signal being sent to bus 101. As a result, potentials corresponding to “0”, the contents of the first 30, second 40, and third 50 counters ( see figure 1) is "nullified", and in the registers 110-1 110-n and 120-1 120-n (see figure 3.4) through their control inputs connected to the bus 101, the "Record" mode is amplified .

 At the next moment, the image of the object is projected onto the matrix of photodetector elements 10-2 (inputs 102-113 in Fig. 2), which is structurally formed by the matrix of image processing cells (Fig. 2).

According to A.S. N 1257674, cl. G 06K, publ. 1986, if the output signal 105 appears in the output bus 105 (see FIG. 2) of the image processing cell 10-1, this indicates the coincidence of the geometric position of the photocell 10-2 of this cell and the immediate vicinity of the inflection point of the contour projected onto the photodetector array 10- 2 images of the object (points F ₁ -F ₁₈ in Fig. 5). The outputs 103, 104 can be used to solve image reproduction problems.

The output signals of the ICG 20 are supplied with a frequency f ₁ to the input of the frequency divider 60 and to the input of the second counter 40, as well as to the information input of the first decoder / demultiplexer 80, the address input of which is connected to the output of the first counter 30. The input of the first counter is connected to the output of the divider 60 frequency converting the signals following with a frequency f ₁ into signals arriving at a frequency f ₂ = f ₁ / N. Each time a signal is received with a frequency f _2, the input of the first counter 30 receives a signal from the output to the address input of the first decoder / demultiplexer 80 to connect to the next output of the last one. At the same time, the output signal of the frequency divider 60 is fed to the control input of the second counter 40, as a result of which it is "zeroed". At the same time, the output signals of the first 30 and second 40 counters are fed to the information inputs of the second 90 and third 100 decoders / demultiplexers, respectively. Each of the N outputs of the first decoder / demultiplexer 80 is connected to the control input of one of the switches 70-1 70-N of the block 70 of the switches, each information input of each of which is connected to the output 105 of one of the N cells 10-1 of the image processing located along one line (column) matrix of 10 image processing cells. In this case, gated switching by the GSN 20 signals of the input of the switch connected to the “working” output of the first decoder / demultiplexer 80 is achieved. Thus, taking into account that the output signal of the first counter 30 corresponds to the number of whole packets of N GSI 20 pulses, sequential “pick-up” of signals from the output 105 of each of the cells 10-1 of the image processing and the transmission of these signals from the outputs 71 of the switches 70-1 70-N via a common bus to the input of the third counter 50. The output signal of the third counter corresponds to the number tvu of the signals "1" that have passed to its input.

 The output signal of the third counter 50 is supplied via the output bus to the address inputs of the second 90 and third 100 decoders / demultiplexers, thereby controlling the transmission of the input signal from the information input to the corresponding "address" information output.

 The output signal from each output bus of the second 90 and third 100 decoders / demultiplexers is fed to the input of one, corresponding to one, register of the first 110 and second 120 blocks of registers, respectively.

регистров 110-1 110-n и

регистров 120-1 120-n параллельно поступают на 2n входов 131 блока 130 распознавании контура.Thus, sequential "recording" of the input signals of the first 110 and second 120 decoders / demultiplexers in the registers 110-1 110-n and 120-1 and 120-n, respectively. Moreover, the output signals of the first 110 and second 120 decoders / demultiplexers follow simultaneously. After the "viewing" of the contents of all the cells 10-10 image processing from the (N + 1) -th output of the first decoder / demultiplexer 80 to the control inputs of the registers 110-1 110-n, 120-1 120-n connected by a common bus, a signal that sets the read mode in all these registers. After that, the output signals

registers 110-1 110-n and

registers 120-1 120-n in parallel are fed to 2n inputs 131 of the block 130 recognition circuit.

блока 130 распознавания контура по 2n входным шинам 131 поступают на входы 2(2n-1) первых вычитателей 130-1. При этом каждая i-я, соответственно (n+i)-я, кроме первой и n-ой, соответственно 2n-ой и (n+1)-ой, входная 131 шина подключена к входам (2i-1)-го, (2i-3)-го и (2i-4)-го, соответственно 2(i+n-1)-го, 2(i+n-2)-го и (2i+2n-5)-го, первых 130-1 первых вычитателей. При этом первая, соответственно (n+1)-я, входная 131 шина подключена к входам первого, 2(n-1)-го и (2n-1)-го, соответственно 2n-го, (4n-3)-го и 2(2n-1)-го вычитателей, а n-я, соответственно 2n-я, входная 131 шина подключена к входам 2(n-1)-го и (2n-1)-го, соответственно (4n-3)-го и 2(2n-1)-го вычислителей (см. фиг.4). Т.е. входы каждого (2i-1)-го, соответственно 2(i+n-1)-го, первого 130-1 вычитателя подключены к i-ой и (i+1)-ой, соответственно (i+n)-ой и (i+1+n)-ой, входной 131 шине, а вход каждого 2i-го, соответственно (2i+2n-1)-го, первого 131-1 вычитателя подключен к i-ой и (i+2)-ой, соответственно (i+n)-ой и (i+n+2)-ой входной 131 шине, причем вторые входы 2(n-1)-го и (2n-1)-го, соответственно (4n-3)-го и 2(2n-1)-го первых 131-1 вычитателей, первые входы которых соединены с (n-1)-ой и n-ой, соответственно (2n-1)-ой и 2n-ой, входными 131 шинами, подключены к первой, соответственно (n+1)-ой, входной 131 шине (см.фиг.3,4).Input signals

block 130 circuit recognition for 2n input buses 131 are fed to the inputs 2 (2n-1) of the first subtractors 130-1. Moreover, each i-th, respectively (n + i) -th, except for the first and n-th, respectively, 2n-th and (n + 1) -th, input 131 bus is connected to the inputs of (2i-1) -th, Of the (2i-3) th and (2i-4) th, respectively of the 2 (i + n-1) th, 2 (i + n-2) th and (2i + 2n-5) th, first 130-1 first subtractors. In this case, the first, respectively (n + 1) th, input 131 bus is connected to the inputs of the first, 2 (n-1) th and (2n-1) th, respectively 2n th, (4n-3) th and 2 (2n-1) -th subtractors, and the n-th, respectively 2n-th, input 131 bus is connected to the inputs of the 2 (n-1) -th and (2n-1) -th, respectively (4n-3) -th and 2 (2n-1) -th calculators (see figure 4). Those. the inputs of each (2i-1) -th, respectively 2 (i + n-1) -th, first 130-1 subtractors are connected to the i-th and (i + 1) -th, respectively (i + n) -th and (i + 1 + n) -th, input 131 bus, and the input of each 2nd, respectively (2i + 2n-1) -th, first 131-1 subtractor is connected to the i-th and (i + 2) -th , respectively (i + n) -th and (i + n + 2) -th input 131 bus, and the second inputs of the 2 (n-1) -th and (2n-1) -th, respectively (4n-3) - of the first and second (2n-1) -th first 131-1 subtracters, the first inputs of which are connected to the (n-1) -th and n-th, respectively (2n-1) -th and 2n-th, input 131 buses, connected to the first, respectively (n + 1) th, input 131 bus (see Fig. 3.4).

), а вторых n вычитателей ΔY_ijY_i-Y_j (i≠j; i,

). Выходные сигналы

по выходным шинам 132 поступают одновременно на входы квадраторов 130-2 (каждый квадратор подключен к одной шине 132) (см. фиг. 3). В качестве квадраторов могут быть использованы умножители с соединенными с одной шиной 132 входами. При этом в выходной шине 133 каждого квадратора реализуется арифметическая операция

. Входные сигналы каждого k-го и (k+n)-го

квадраторов одновременно поступают на входы одного, k-го, сумматора 130-3. Таким образом, в выходной шине каждого сумматора реализуется арифметическая операция R_ij= (ΔX_ij)²+(ΔY_ij)². После этого выходные сигналы

одновременно поступают по выходным шинам 134 на входы делителей 130-4. Причем каждая (2k-1)-я шина 134 соединена с первым входом 2k-го и (2k+1)-го делителей, вторые входы которых соединены соответственно с 2k-ой и (2k+1)-ой шиной 134 (см. фиг. 3,4).Thus, in the output buses of the first n subtractors 130-1, the arithmetic operation ΔX _ij X _i -X _j (i ≠ j; i,

), and the second n subtractors ΔY _ij Y _i -Y _j (i ≠ j; i,

) Output signals

on the output buses 132, they arrive simultaneously at the inputs of the squares 130-2 (each quad is connected to one bus 132) (see Fig. 3). Multipliers with inputs connected to one bus 132 can be used as quadrants. In this case, an arithmetic operation is implemented in the output bus 133 of each quadrator

. Input signals of each k-th and (k + n) -th

quadrators simultaneously arrive at the inputs of one, k-th, adder 130-3. Thus, the arithmetic operation R _ij = (ΔX _ij ) ² + (ΔY _ij ) ² is implemented in the output bus of each adder. After that, the output signals

simultaneously arrive at the output buses 134 to the inputs of the dividers 130-4. Moreover, each (2k-1) -th bus 134 is connected to the first input of the 2k and (2k + 1) -th dividers, the second inputs of which are connected respectively to the 2k-th and (2k + 1) -th bus 134 (see Fig. 3,4).

где j=i+2.Thus, the arithmetic operation is implemented in the output buses 134 of the dividers 130-4

where j = i + 2.

делителей 130-4 по выходным шинам 135 поступают на первые входы вторых вычитателей 130-5. Одновременно по шинам, ответвленным от каждой шины 135, на управляющие входы регистров 130-6 эталона поступают сигналы, установливающие режим "чтение" в регистрах. При этом с выходов регистров 130-6 на вторые входы вторых вычитателей 130-5 поступают сигналы, соответствующие эталонным значениям сигналов

, т.е.

.Output signals

dividers 130-4 on the output buses 135 are supplied to the first inputs of the second subtractors 130-5. At the same time, along the buses branched from each bus 135, signals are set to the control inputs of the registers 130-6 of the standard, which establish the "read" mode in the registers. In this case, from the outputs of the registers 130-6 to the second inputs of the second subtractors 130-5 receive signals corresponding to the reference values of the signals

, i.e.

.

Thus, when signals D _ij , D are simultaneously input $\genfrac{}{}{0ex}{}{\text{floor}}{\text{ij}}$ every second subtractor 130-5 it performs the arithmetic operation ΔD _ij = D _ij -D $\genfrac{}{}{0ex}{}{\text{floor}}{\text{ij}}$ .

где Z_e выходной сигнал каждого l-го порогового элемента 130-7,

.The output signals 2 (n-1) of the second subtractors 130-5 through the output buses 136 are fed to the inputs 2 (n-1) of the threshold elements 130-7. As a result, the output of each threshold element 130-7 implements a logical operation

where Z _{e the} output signal of each l-th threshold element 130-7,

.

d thresholds _{, the} threshold signal value selected at the training stage of the circuit recognition unit 130.

 According to this operation, the condition of the "proximity" of the coordinates of the reference and real vectors of the structural features of the image contour in the form of the ratio of the squares of the relative distances between two adjacent i-th and (i + 1) -th inflection points of the contour to the distance from one of the neighboring to the nearest (i +2) th inflection point.

пороговых элементов 130-7 поступают по выходным шинам 137 на входы n-1 элементов И-НЕ 130-8 так, что на входы каждого m-го

элемента И-НЕ 130-8 поступают одновременно выходные сигналы от (2m-1)-го и 2m-го вычитателей 130-7.Output signals

threshold elements 130-7 arrive at the output buses 137 to the inputs of n-1 elements AND-NOT 130-8 so that the inputs of each m-th

element AND-NOT 130-8 simultaneously receive output signals from the (2m-1) -th and 2m-th subtractors 130-7.

.As a result, the logical operation is implemented at the output of AND-NOT 130-8 elements (in the output bus 138, see Fig. 4)

.

Так как множество векторов

охватывает весь контур изображения (все точки перегиба контура), то наличие хотя бы одного сигнала "1" в одном из элементов И-НЕ 130-8 соответствует неэквивалентности (в смысле распознавания) контуров эталонного и реального изображений объекта.According to this operation, the absence of simultaneous “proximity” of two coordinates, and therefore the two-dimensional vectors P themselves, is checked $\genfrac{}{}{0ex}{}{\text{floor}}{\text{ij}}$ and P _ij signs of recognition of the contours of the reference and real images of the object. Physically, this means that

Since many vectors

covers the entire contour of the image (all inflection points of the contour), then the presence of at least one signal "1" in one of the I-NOT 130-8 elements corresponds to the nonequivalence (in the sense of recognition) of the contours of the reference and real images of the object.

 Thus, the appearance of the signal "1" in the output bus 138 of the circuit recognition unit 130 indicates the absence of recognition, and, consequently, the correctness of the "fixation" of the contour of this image.

 Therefore, the output signal “1” transmitted to the output bus 138 connected to the device “Install” bus 101 is used as a “reset” (“install”) signal, i.e. "zeroing", memory elements of cells 10-1 image processing, etc.

 Thus, the structural and functional design of the proposed device for selecting the contour of the image of the object allows you to expand its functionality, and therefore the scope by providing recognition.

 The use of such a device is advisable, for example, in optoelectronic guidance and tracking systems for reconnaissance and destruction. The device will “discard” the selected circuit from memory until, as a result of the search for a given target object by the reconnaissance system that includes this device, an object image similar in outline to the reference one does not get on the photocells of the matrix of image processing cells of the device. In addition, the contents of the registers of blocks 110 and 120 ("addresses" of the inflection points of the contour) can be used to calculate the aiming (pointing) points.

позволяет добиться относительно высокой помехоустойчивости и значительно меньшего объема оперативной и эталонной памяти, чем, например, при корреляционно-экстримальном распознавании. Кроме того, вычисление признаков вида P_ij не требует сложных арифметическо-логических операций и поэтому конструктивно просто реализуется.Using view recognition features

allows to achieve a relatively high noise immunity and significantly less RAM and reference memory than, for example, in correlation-extreme recognition. In addition, the calculation of signs of the form P _ij does not require complex arithmetic-logical operations and therefore is structurally easy to implement.

The amount of RAM, excluding the capacity of the memory elements of the image processing cells, is determined mainly by the total capacity of the blocks of address registers, i.e., the total number of registers included in them. Since for most of the contours of the analyzed images, the number n of inflection points of the contours is within 9.18, the amount of RAM is approximately 18-36 bytes. The recognition time of the image contour of an object does not exceed 10 ^-4 -10 ^-3 s.

 The analysis shows that for the recognition signs used in the device, it is enough that in the minimum overall size of the image of the object fit from 8 to 16 photocells of the matrix 10.

 Given this, optical-electronic systems (for example, thermal imaging) using this device can have an array of image processing cells ranging in size from 16x16 to 32x32 cells, i.e. N = 16-32. This meets the capabilities of modern technology.

 The regularity of the device structure simplifies the task of its implementation in the form of a special LSI (VLSI).

Claims (2)

 1. A device for recognizing objects by their circuits, containing optical signal to electric converters, the information inputs of which are the information inputs of the device, and the outputs are connected to the information inputs of the corresponding image processing nodes, the installation inputs of which are the installation input of the device, the first and second outputs are respectively the first and second information outputs of the device, characterized in that, in order to increase the accuracy and reliability of the device, it contains the switchboard, the information inputs of which are connected to the third outputs of the corresponding image processing nodes, the first switch, the outputs of which are connected to the control inputs of the respective switches of the group, the first counter, the installation input of which is connected to the installation input of the device, and the counting input with the outputs of the switches of the group, the second and the third switches, the control inputs of which are connected to the output of the first counter, and the outputs are the third and fourth information outputs of the device, respectively Namely, the second counter, the installation input of which is connected to the installation input of the device, and the output with the control input of the first and the information input of the second switch, the third counter, the installation input of which is connected to the installation input of the device, and the output to the information input of the third switch, frequency divider, output which is connected to the counting input of the second and control input of the third counters, a pulse generator, the output of which is connected to the input of the frequency divider, the information input of the first switch and the counting input of the third counter, the register block, the installation input of which is connected to the installation input of the device, the control input with the corresponding output of the first switch, and the information inputs are connected to the outputs of the second and third switches, and the coordinate comparison unit, the information inputs of which are connected to the outputs of the register block , and the output is connected to the installation input of the device.  2. The device according to p. 1, characterized in that the coordinate comparison unit contains a first group of subtracters, the information inputs of which are the information inputs of the block, and the outputs are connected to the information inputs of the corresponding quadrators, the outputs of the squares are connected to the information inputs of the corresponding adders, the outputs of which are connected to information inputs of the respective dividers, the outputs of the dividers are connected to the information inputs of the respective registers and the first information inputs of the respective x subtractors of the second group, the second information inputs which are connected to the outputs of the respective registers, the outputs of the subtractors of the second group are connected to data inputs of respective threshold elements, the outputs of which are connected to respective inputs of AND-NO elements, and the outputs of AND-NO elements are output unit.

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