CN110826705B

CN110826705B - Operation method, device and related product

Info

Publication number: CN110826705B
Application number: CN201810902139.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2018-08-09
Filing date: 2018-08-09
Publication date: 2022-08-19
Anticipated expiration: 2038-08-09
Also published as: CN110826705A

Abstract

The present disclosure relates to methods, apparatus, and related products for computing, the methods comprising: the first processing circuit determines a reconstruction circuit group according to a reconstruction rule, wherein the reconstruction rule comprises that at least two second processing circuits are utilized to form the reconstruction circuit group; the first processing circuit sends an operation instruction to the reconstruction circuit group so that a second processing circuit in the reconstruction circuit group obtains a processing result according to the operation instruction and obtains an intermediate result according to the processing result; and the first processing circuit receives the intermediate result sent back by the reconstruction circuit group and obtains the operation result of the operation instruction according to the intermediate result. The embodiment of the disclosure can enable the circuit structure to complete different operations more efficiently. The reconfiguration circuit group can improve the processing efficiency of the second processing circuit, reduce the calculation amount of the first processing circuit and improve the overall operation efficiency of the circuit structure.

Description

Operation method, device and related product

Technical Field

The present disclosure relates to the field of information processing technologies, and in particular, to an operation method, an operation device, and a related product.

Background

With the continuous development of information technology, the requirement for completing complex tasks by using a neural network computing device is increasing. The neural network arithmetic device can comprise different types of circuit structures, and different circuit structures are suitable for different arithmetic processing and have different processing efficiency. For example, the neural network operation device includes a circuit structure of a master-slave architecture. The plurality of slave processing circuits perform calculation simultaneously, and the master processing circuit obtains a final calculation result after all the slave circuits perform calculation, so that the overall calculation efficiency is low.

Disclosure of Invention

In view of the above, the present disclosure provides an arithmetic device and related products, so as to improve the processing efficiency of the arithmetic device and improve the accuracy of the arithmetic result.

According to an aspect of the present disclosure, there is provided a circuit reconfiguration method applied to a circuit configuration including a first processing circuit and a plurality of second processing circuits, the method including:

the first processing circuit determines a reconstruction circuit group according to a reconstruction rule, wherein the reconstruction rule comprises that at least two second processing circuits are utilized to form the reconstruction circuit group;

the first processing circuit sends an operation instruction to the reconstruction circuit group so that a second processing circuit in the reconstruction circuit group obtains a processing result according to the operation instruction and obtains an intermediate result according to the processing result;

and the first processing circuit receives the intermediate result sent back by the reconstruction circuit group and obtains the operation result of the operation instruction according to the intermediate result.

In a possible implementation manner, the sending, by the first processing circuit, an operation instruction to the reconfiguration circuit group so that the second processing circuit in the reconfiguration circuit group obtains a processing result according to the operation instruction and obtains an intermediate result according to the processing result includes:

the first processing circuit splits the received operation instruction according to the reconstruction rule to obtain a reconstruction operation instruction;

and the first processing circuit sends the reconstruction operation instruction to the reconstruction circuit group so as to enable a second processing circuit in the reconstruction circuit group to obtain a processing result according to the reconstruction operation instruction and obtain an intermediate result according to the processing result.

In one possible implementation, the method further includes:

the first processing circuit determines a reconstruction rule according to the received operation instruction.

In a possible implementation manner, the determining, by the first processing circuit, a reconfiguration rule according to a received operation instruction includes:

and the first processing circuit searches the reconstruction rule in a reconstruction rule set according to the reconstruction identifier in the operation instruction.

the first processing circuit sends an operation instruction to the reconstruction circuit group so that a second processing circuit in the reconstruction circuit group obtains a processing result according to the operation instruction, and at least one of the following operations is carried out on the processing result of the second processing circuit in the reconstruction circuit group to obtain the intermediate result: addition, accumulation, and multiplication.

In a possible implementation manner, the first processing circuit receives an intermediate result sent back by the reconfiguration circuit group, and obtains an operation result of the operation instruction according to the intermediate result, including:

the first processing circuit receives the intermediate result sent back by the reconstruction circuit group, and performs at least one of the following processing on the intermediate result to obtain an operation result of the operation instruction: addition operation, accumulation element operation, multiplication operation and activation operation.

a target processing circuit determines an associated circuit in a reconstruction circuit group according to a reconstruction rule, wherein the target processing circuit comprises any second processing circuit, the reconstruction rule comprises a reconstruction circuit group formed by at least two second processing circuits, and the associated circuit comprises a second processing circuit which has an operation relation with the target processing circuit in the reconstruction circuit group;

the target processing circuit acquires data to be operated according to the operation instruction sent by the first processing circuit and performs operation to obtain a first processing result;

the target processing circuit sends the first processing result to the association circuit, so that the association circuit performs operation according to a second processing result of the association circuit and the first processing result to obtain a third processing result, the reconstruction circuit group obtains an intermediate result according to the third processing result and sends the intermediate result to the first processing circuit, and the second processing result is obtained by the association circuit performing operation according to the operation instruction sent by the first processing circuit and obtained by acquiring data to be operated.

In one possible implementation, the method further includes:

and the target processing circuit sends the processing result to a storage device, so that the correlation circuit carries out operation according to the processing result after extracting the processing result from the storage device.

In one possible implementation, the method further includes:

and the target processing circuit acquires a reconstruction rule according to the operation instruction sent by the first processing circuit.

the target processing circuit determines a related circuit in a reconstruction circuit group according to a reconstruction rule, the target processing circuit comprises any one of the second processing circuits, the reconstruction rule comprises a reconstruction circuit group formed by at least two of the second processing circuits, and the related circuit comprises a second processing circuit which is in an operational relation with the target processing circuit in the reconstruction circuit group;

the target processing circuit receives a second processing result sent by the association circuit, carries out operation according to the second processing result and the first processing result to obtain a third processing result, enables the reconstruction circuit group to obtain an intermediate result according to the third processing result and then sends the intermediate result to the first processing circuit, and the second processing result is obtained by the association circuit through operation of obtaining data to be operated according to an operation instruction sent by the first processing circuit.

the target processing circuit acquires data to be operated according to the received operation instruction and operates the data to be operated to obtain a first processing result;

and the target processing circuit sends the first processing result to the association circuit so that the association circuit performs operation according to a second processing result of the association circuit and the first processing result to obtain a third processing result, and the reconstruction circuit group sends an intermediate result after obtaining the intermediate result according to the third processing result, wherein the second processing result is obtained by the association circuit performing operation according to the operation instruction to obtain data to be operated.

and the target processing circuit receives a second processing result sent by the association circuit, performs operation according to the second processing result and the first processing result to obtain a third processing result, and enables the reconstruction circuit group to obtain an intermediate result according to the third processing result and then send the intermediate result, wherein the second processing result is obtained by the association circuit obtaining data to be operated according to the operation instruction and performing operation.

According to an aspect of the present disclosure, there is provided a reconstruction circuit comprising a first processing circuit and a plurality of second processing circuits, wherein:

the first processing circuit is used for determining a reconstruction circuit group according to a reconstruction rule, and the reconstruction rule comprises a reconstruction circuit group formed by at least two second processing circuits;

the first processing circuit is used for sending an operation instruction to the reconstruction circuit group so as to enable a second processing circuit in the reconstruction circuit group to obtain a processing result according to the operation instruction and obtain an intermediate result according to the processing result;

the first processing circuit is used for receiving the intermediate result sent back by the reconstruction circuit group and obtaining the operation result of the operation instruction according to the intermediate result.

In a possible implementation manner, the first processing circuit is configured to send an operation instruction to the reconfiguration circuit group, so that a second processing circuit in the reconfiguration circuit group obtains a processing result according to the operation instruction and obtains an intermediate result according to the processing result, including:

the first processing circuit is used for splitting the received operation instruction according to the reconstruction rule to obtain a reconstruction operation instruction;

the first processing circuit is used for sending the reconfiguration operation instruction to the reconfiguration circuit group so that a second processing circuit in the reconfiguration circuit group obtains a processing result according to the reconfiguration operation instruction and obtains an intermediate result according to the processing result.

In a possible implementation, the first processing circuit is configured to determine a reconstruction rule according to a received operation instruction.

In a possible implementation manner, the first processing circuit is configured to determine a reconstruction rule according to a received operation instruction, and includes:

the first processing circuit is used for searching the reconstruction rule in a reconstruction rule set according to the reconstruction identifier in the operation instruction.

the first processing circuit is configured to send an operation instruction to the reconfiguration circuit group, so that the second processing circuit in the reconfiguration circuit group obtains a processing result according to the operation instruction, and performs at least one of the following operations on the processing result of the second processing circuit in the reconfiguration circuit group to obtain the intermediate result: addition, accumulation, and multiplication.

In a possible implementation manner, the first processing circuit is configured to receive an intermediate result sent back by the reconfiguration circuit group, and obtain an operation result of the operation instruction according to the intermediate result, and includes:

the first processing circuit is configured to receive the intermediate result sent back by the reconstruction circuit group, and perform at least one of the following processing on the intermediate result to obtain an operation result of the operation instruction: addition operation, accumulation element operation, multiplication operation and activation operation.

the target processing circuit is used for determining a related circuit in a reconstruction circuit group according to a reconstruction rule, the target processing circuit comprises any one of the second processing circuits, the reconstruction rule comprises a reconstruction circuit group formed by at least two of the second processing circuits, and the related circuit comprises a second processing circuit which is in an operational relation with the target processing circuit in the reconstruction circuit group;

the target processing circuit is used for acquiring data to be operated according to the operation instruction sent by the first processing circuit to carry out operation so as to obtain a first processing result;

the target processing circuit is used for sending the first processing result to the association circuit, so that the association circuit performs operation according to a second processing result of the association circuit and the first processing result to obtain a third processing result, the reconstruction circuit group obtains an intermediate result according to the third processing result and sends the intermediate result to the first processing circuit, and the second processing result is obtained by the association circuit performing operation on data to be operated according to an operation instruction sent by the first processing circuit.

In a possible implementation manner, the target processing circuit is configured to send the processing result to a storage device, so that the correlation circuit performs an operation according to the processing result after extracting the processing result from the storage device.

In a possible implementation, the target processing circuit is configured to obtain a reconfiguration rule according to an operation instruction sent by the first processing circuit.

the target processing circuit is used for receiving a second processing result sent by the association circuit, performing operation according to the second processing result and the first processing result to obtain a third processing result, enabling the reconstruction circuit group to obtain an intermediate result according to the third processing result and then sending the intermediate result to the first processing circuit, and the second processing result is obtained by the association circuit through operation of obtaining data to be operated according to an operation instruction sent by the first processing circuit.

the target processing circuit is used for acquiring data to be operated according to the received operation instruction and operating to obtain a first processing result;

the target processing circuit is used for sending the first processing result to the correlation circuit, so that the correlation circuit performs operation according to a second processing result of the correlation circuit and the first processing result to obtain a third processing result, and the reconstruction circuit group sends an intermediate result after obtaining the intermediate result according to the third processing result, wherein the second processing result is obtained by the correlation circuit performing operation according to the operation instruction to obtain data to be operated.

the target processing circuit is used for determining a correlation circuit in a reconstruction circuit group according to a reconstruction rule, the target processing circuit comprises any second processing circuit, the reconstruction rule comprises a reconstruction circuit group formed by at least two second processing circuits, and the correlation circuit comprises a second processing circuit which has an operation relation with the target processing circuit in the reconstruction circuit group;

the target processing circuit is used for receiving a second processing result sent by the association circuit, performing operation according to the second processing result and the first processing result to obtain a third processing result, and enabling the reconstruction circuit group to obtain an intermediate result according to the third processing result and then send the intermediate result, wherein the second processing result is obtained by the association circuit through operation according to the operation instruction and obtaining data to be operated.

According to an aspect of the present disclosure, there is provided a neural network operation device including one or more of the above reconstruction circuits, the neural network operation device being configured to perform a set neural network operation.

According to an aspect of the present disclosure, there is provided a combined operation device, the combined operation device comprising one or more of the above neural network operation devices, a universal interconnection interface and other processing devices;

and the neural network operation device interacts with the other processing devices to jointly complete the calculation operation specified by the user.

According to an aspect of the present disclosure, there is provided a neural network chip including:

the reconstruction circuit of any of the above; or

The neural network arithmetic device described above; or

The combined treatment device.

According to an aspect of the present disclosure, there is provided an electronic apparatus including:

the reconstruction circuit of any of the above; or

The neural network arithmetic device described above; or

The above-described combined treatment apparatus; or

The neural network chip is described above.

In the embodiment of the present disclosure, after the first processing circuit determines the reconfiguration circuit group according to the reconfiguration rule, the reconfiguration circuit group sends the operation instruction to the reconfiguration circuit group, and then the reconfiguration circuit group sends the obtained intermediate result back to the first processing circuit. And the first processing circuit obtains the operation result of the operation instruction according to the intermediate result of the reconstruction circuit group. Different reconstruction circuit groups can be formed according to different operation instructions or different operation purposes, so that different operations can be completed by the circuit structure more efficiently. The reconfiguration circuit group can improve the processing efficiency of the second processing circuit, reduce the calculation amount of the first processing circuit and improve the overall operation efficiency of the circuit structure.

In some embodiments, the electronic device comprises a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.

In some embodiments, the vehicle comprises an aircraft, a ship, and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance instrument, a B ultrasonic instrument and/or an electrocardiograph.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 shows a flow diagram of a circuit reconfiguration method according to an embodiment of the present disclosure;

FIG. 2 shows a flow diagram of a circuit reconfiguration method according to an embodiment of the present disclosure;

FIG. 3 illustrates a flow diagram of a circuit reconfiguration method according to an embodiment of the present disclosure;

FIG. 4 illustrates a flow diagram of a circuit reconfiguration method according to an embodiment of the present disclosure;

FIG. 5 shows a flow diagram of a circuit reconfiguration method according to an embodiment of the present disclosure;

FIG. 6 shows a flow diagram of a circuit reconfiguration method according to an embodiment of the present disclosure;

FIG. 7 shows a block diagram of a computing device in a circuit reconfiguration method according to an embodiment of the present disclosure;

FIG. 8 shows a block diagram of an arithmetic unit in a circuit reconfiguration method according to an embodiment of the present disclosure;

FIG. 9 shows a block diagram of a reconstruction circuit according to an embodiment of the present disclosure;

fig. 10 shows a block diagram of a combined processing device according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Fig. 1 shows a flowchart of a circuit reconfiguration method according to an embodiment of the present disclosure, which is applied to a circuit configuration including a first processing circuit and a plurality of second processing circuits, as shown in fig. 1, and includes:

and step S11, the first processing circuit determines a reconstruction circuit group according to a reconstruction rule, and the reconstruction rule comprises that at least two second processing circuits are utilized to form the reconstruction circuit group.

In one possible implementation, a controller unit and an arithmetic unit may be included in the neural network computing device. The controller unit may be configured to obtain data to be calculated, a machine learning model, and a calculation instruction, and may be configured to analyze the calculation instruction to obtain a plurality of operation instructions, and send the plurality of operation instructions and the data to be calculated to the operation unit. The arithmetic unit can carry out operation according to the received operation instruction and the data to be calculated to obtain an operation result. The circuit structure can be an arithmetic unit in the neural network computing device for completing operation according to the operation instruction.

In one possible implementation, the arithmetic unit may include a master processing circuit and a plurality of slave processing circuits. The controller unit may send the operation instruction to the master processing circuit, distribute the operation instruction to the slave processing circuit by the master processing circuit, and perform an operation according to the operation instruction by the slave processing circuit. The controller unit may send the operation instruction directly to the slave processing circuit, and the slave processing circuit may perform an operation based on the operation instruction.

In a possible implementation manner, the master processing circuit may allocate the input neuron data into a plurality of data blocks, and send at least one data block, a weight, and an operation instruction to the slave processing circuit, the slave processing circuit may obtain a processing result according to the received data block, the weight, and the operation instruction, and send the processing result back to the master processing circuit, and the master processing circuit may obtain a final operation result according to the processing result of each slave processing circuit. The master processing circuit may be a first processing circuit, and the slave processing circuit may be a second processing circuit, and the circuit reconfiguration method according to the embodiment of the present disclosure is applied.

In one possible implementation, the arithmetic unit may further include a branch processing circuit. The main processing circuit is connected with a plurality of branch processing circuits. Each branch processing circuit is connected to a plurality of slave processing circuits. The main processing circuit may allocate the input neuron data into a plurality of data blocks and send at least one of the data blocks, the weight values, and the operation instructions to the branch processing circuit. The branch processing circuit may further divide the received data block into a plurality of sub-data blocks. The branch processing circuit can send at least one sub data block, the weight and the operation instruction to the slave processing circuit connected with the branch processing circuit, and the slave processing circuit sends a processing result back to the branch processing circuit after obtaining the processing result according to the received sub data block, the weight and the operation instruction. Each branch circuit may obtain a respective branch processing result from the processing result of the slave processing circuit and send the branch processing result back to the master processing circuit. The main processing circuit can obtain a final operation result according to the branch processing result of each branch processing circuit. The main processing circuit may be a first processing circuit, and the branch processing circuit may be a second processing circuit, and the circuit reconfiguration method according to the embodiment of the present disclosure is applied. Meanwhile, the branch processing circuit may be a first processing circuit, and the slave processing circuit may be a second processing circuit, and the circuit reconfiguration method according to the embodiment of the present disclosure is applied.

In one possible implementation, the reconfiguration rule may include generating one or more reconfiguration circuit groups according to a part of the second processing circuits in the circuit structure, and the remaining part of the second processing circuits no longer constitute the reconfiguration circuit groups. The reconfiguration rule may also include generating one or more reconfiguration circuit groups from all of the second processing circuits in the circuit arrangement. For example, the circuit structure includes four second processing circuits, which are a second processing circuit a, a second processing circuit B, a second processing circuit C, and a second processing circuit D. According to the set reconfiguration rule, a reconfiguration circuit group 1 (including a second processing circuit a and a second processing circuit B) and a reconfiguration circuit group 2 (including a second processing circuit C and a second processing circuit D) can be generated; a reconfiguration circuit group 3 (including the second processing circuit a, the second processing circuit B, and the second processing circuit C) may be generated, the remaining second processing circuits D not constituting the reconfiguration circuit group; a reconfiguration circuit group 4 (including a second processing circuit a, a second processing circuit B, a second processing circuit C, and a second processing circuit D) may also be generated.

In a possible implementation manner, the second processing circuit constituting the reconfiguration circuit group may be specified in the reconfiguration rule, and the first processing circuit determines the reconfiguration circuit group according to the second processing circuit specified in the reconfiguration rule. For example, in the above example, the reconfiguration rule may specify that the reconfiguration circuit group is configured with the second processing circuit C and the second processing circuit D. In the reconfiguration rule, only the number of the reconfiguration circuit groups and the number of the second processing circuits in each reconfiguration circuit group may be determined, and the first processing circuit may select the second processing circuit to determine the reconfiguration circuit group according to the reconfiguration rule. For example, the reconfiguration rule may determine that one reconfiguration circuit group is configured by two second processing circuits, and that the reconfiguration circuit group is configured by the first processing circuit by the second processing circuit a and the second processing circuit B.

Step S12, the first processing circuit sends an operation instruction to the reconfiguration circuit group, so that the second processing circuit in the reconfiguration circuit group obtains a processing result according to the operation instruction, and obtains an intermediate result according to the processing result.

In a possible implementation manner, the first processing circuit may process the operation instruction, send the processed operation instruction to the corresponding reconfiguration circuit group, and perform corresponding operation by the reconfiguration circuit group. The first processing circuit may also send the operation instruction directly to the reconfiguration circuit group, and the reconfiguration circuit performs the operation according to a part of the instructions related to the first processing circuit in the operation instruction.

In one possible implementation, the reconfiguration circuit group includes at least two second processing circuits. Each second processing circuit can obtain the data to be operated related to the operation instruction according to the operation instruction sent by the first processing circuit, and then operate the data to be operated, so as to obtain a processing result. The reconfiguration circuit group may obtain an intermediate result based on the processing results of the second processing circuits in the group. For example, the set of reconstruction circuits may add or multiply the processing results of the second processing circuits in the set to obtain an intermediate result.

In one possible implementation, the calculation to obtain the intermediate result according to the processing result of each second processing circuit may be performed by a second processing circuit set in the reconfiguration circuit group, for example, in the reconfiguration circuit group formed by the second processing circuit C and the second processing circuit D, after the second processing circuit C and the second processing circuit D respectively obtain the processing results, the second processing circuit D sends the own processing result to the second processing circuit C, and the second processing circuit C obtains the intermediate result of the reconfiguration circuit group according to the two processing results.

In a possible implementation, the second processing circuit for performing the correlation operation to obtain the intermediate result may also be determined according to a set rule. For example, it may be configured that the second processing circuit which completes the calculation first sends the processing result to the second processing circuit which does not complete the calculation, and the second processing circuit which completes the calculation later obtains an intermediate result according to the processing result of each second processing circuit in the group.

In one possible implementation, in the arithmetic unit in the conventional neural network arithmetic device, the main processing circuit can perform multiplication, addition, accumulation and activation. The slave processing circuit can perform multiplication, addition, accumulation, and the like. According to related methods of embodiments of the present disclosure, the master processing circuit may be a first processing circuit and the slave processing circuit may be a second processing circuit. The slave processing circuit can obtain its own processing result according to the operation instruction, and can further perform operation on its own processing result and the processing results of other slave processing circuits in the group to obtain an intermediate result of the reconfiguration circuit group.

And step S13, the first processing circuit receives the intermediate result sent back by the reconstruction circuit group, and obtains the operation result of the operation instruction according to the intermediate result.

In a possible implementation manner, one or more reconstructed circuit groups may be formed by second processing circuits partially connected to the first processing circuit, and the first processing circuit may obtain the operation result of the operation instruction according to the received intermediate result sent by the reconstructed circuit group and the processing result of the second processing circuit that does not form the reconstructed circuit group.

In one possible implementation, one or more reconstructed circuit groups may be formed by the second processing circuits which are all connected to the first processing circuit, and the first processing circuit may obtain the operation result of the operation instruction according to the intermediate result of the single or multiple reconstructed circuit groups.

The first processing circuit receives the intermediate result sent back by the reconstruction circuit group, and obtains the operation result of the operation instruction according to the intermediate result, including:

the first processing circuit receives the intermediate result sent back by the reconstruction circuit group, and performs at least one of the following processing on the intermediate result to obtain the operation result of the operation instruction: addition operation, accumulation element operation, multiplication operation and activation operation.

In one possible implementation, in the arithmetic unit in the conventional neural network arithmetic device, the master processing circuit may be a first processing circuit, and the slave processing circuit may be a second processing circuit. The set of reconfiguration circuits may be formed using at least two slave processing circuits. The main processing circuit can complete accumulation operation, addition operation, activation operation and the like according to the intermediate result of the reconstruction circuit group to obtain the operation result of the operation instruction. The main processing circuit can be configured with only an adder or an activation unit to perform addition operation, accumulation operation and activation operation without configuring a multiplier and performing multiplication operation. Or all the slave processing circuits can form a reconstruction circuit group, and the master processing circuit only carries out activation operation according to the intermediate result of the reconstruction circuit group to obtain the operation result of the operation instruction. The main processing circuit only needs to configure the activation unit to perform activation operation.

In this embodiment, after the first processing circuit determines the reconstruction circuit group according to the reconstruction rule, the reconstruction circuit group sends the operation instruction to the reconstruction circuit group, and then sends an obtained intermediate result back to the first processing circuit. And the first processing circuit obtains the operation result of the operation instruction according to the intermediate result of the reconstruction circuit group. Different reconstruction circuit groups can be formed according to different operation instructions or different operation purposes, so that different operations can be completed by the circuit structure more efficiently. The reconfiguration circuit group can improve the processing efficiency of the second processing circuit, reduce the calculation amount of the first processing circuit and improve the overall operation efficiency of the circuit structure.

Fig. 2 shows a flowchart of a circuit reconfiguration method according to an embodiment of the present disclosure, as shown in fig. 2, the step S12 in the method includes:

in step S121, the first processing circuit splits the received operation instruction according to the reconfiguration rule to obtain a reconfiguration operation instruction.

And step S122, the first processing circuit sends the reconfiguration operation instruction to the reconfiguration circuit group, so that a second processing circuit in the reconfiguration circuit group obtains a processing result according to the reconfiguration operation instruction, and obtains an intermediate result according to the processing result.

In a possible implementation manner, the first processing circuit may split the received operation instruction according to the reconfiguration rule, and split the operation instruction into a reconfiguration operation instruction corresponding to the reconfiguration circuit group direction. The reconstruction operation instruction may include only an operation instruction related to the second processing circuit in the reconstruction circuit group. For example, the operation instruction may be an operation according to data blocks 1-100 to obtain an operation result. According to the reconfiguration rule, among the four second processing circuits, the reconfiguration circuit group 1 may be configured by the second processing circuit a and the second processing circuit B, and the reconfiguration circuit group 2 may be configured by the second processing circuit C and the second processing circuit D. The operation instruction may be split into two reconstructed operation instructions: a reconstruct operation instruction 1 and a reconstruct operation instruction 2. The reconstruction operation instruction 1 corresponds to the reconstruction circuit group 1 and is used for performing operation according to the data blocks 1 to 50 to obtain an intermediate result 1. The reconstruction operation instruction 2 corresponds to the reconstruction circuit group 2 and is used for performing operation according to the data blocks 51-100 to obtain an intermediate result 2.

In one possible implementation manner, the first processing circuit may send the reconfiguration operation instruction to the reconfiguration circuit group corresponding to the reconfiguration operation instruction, so that the reconfiguration circuit group obtains an intermediate result according to the reconfiguration operation instruction. For example, the first processing circuit may send the reconfiguration operation instruction 1 to the reconfiguration circuit group 1, so that the second processing circuit a and the second processing circuit B in the reconfiguration circuit group 1 perform operations respectively according to the reconfiguration operation instruction 1, and after obtaining respective processing results, the reconfiguration circuit group 1 may obtain an intermediate result 1 by using the two processing results. Meanwhile, the first processing circuit may send the reconfiguration operation instruction 2 to the reconfiguration circuit group 2, so that the second processing circuit C and the second processing circuit D in the reconfiguration circuit group 2 respectively perform operations according to the reconfiguration operation instruction 2, and after respective processing results are obtained, the reconfiguration circuit group 2 may obtain the intermediate result 2 by using the two processing results. And finally, the first processing circuit obtains an operation result according to the intermediate result 1 of the reconstruction circuit group 1 and the intermediate result 2 of the reconstruction circuit group 2.

In this embodiment, the first processing circuit may split the received operation instruction according to the reconfiguration rule, and after obtaining the reconfiguration operation instruction, send the reconfiguration operation instruction to the corresponding reconfiguration circuit group. The reconstruction operation instruction can improve the operation efficiency of the reconstruction circuit group.

In one possible implementation, the method further includes: the first processing circuit determines a reconstruction rule according to the received operation instruction.

In one possible implementation, a reconstruction rule set consisting of a plurality of predetermined reconstruction rules may be stored in a memory device of the circuit configuration. The reconfiguration rule setting instruction may be sent to the first processing circuit or the second processing circuit as required. The reconstruction rule setting instruction may be independent of the operation instruction. The reconfiguration rule set specifies a number that can carry a reconfiguration rule. The first processing circuit may determine a number of the reconstruction rule according to the reconstruction rule setting instruction, and extract a corresponding reconstruction rule in the reconstruction rule set according to the determined number. The first processing circuit may send the extracted reconstruction rule to the corresponding second processing circuit so that the second processing circuit constitutes a reconstruction circuit group. The second processing circuit may also extract a corresponding reconfiguration rule from the reconfiguration rule set according to the reconfiguration rule setting instruction, and then form a reconfiguration circuit group.

In a possible implementation manner, the first processing circuit may search the reconstruction rule in a reconstruction rule set according to a reconstruction identifier in the operation instruction. The information of the reconstruction rule may be carried in the operation instruction. The operation instruction may include a reconstruction identifier, and the reconstruction identifier may be used to carry rule number information of a reconstruction rule, and the like. The first processing circuit may search the stored reconstruction rule for the reconstruction rule corresponding to the reconstruction identifier according to the information in the reconstruction identifier, and determine the reconstruction circuit group according to the searched reconstruction rule.

In this embodiment, the operation instruction may carry a reconfiguration identifier, and the first processing circuit may determine, according to the reconfiguration identifier, a reconfiguration rule corresponding to the reconfiguration identifier in the reconfiguration rule set, and determine the reconfiguration circuit group according to the reconfiguration rule. The reconstruction identifier carried in the operation instruction can enable the first processing circuit to conveniently acquire the reconstruction rule matched with the operation instruction.

Fig. 3 shows a flowchart of a circuit reconfiguration method according to an embodiment of the present disclosure, the method being applied to a circuit configuration including a first processing circuit and a plurality of second processing circuits, as shown in fig. 3, the method including:

step S31, the target processing circuit determines the associated circuit in the reconstruction circuit group according to the reconstruction rule, the target processing circuit includes any one of the second processing circuits, the reconstruction rule includes that at least two of the second processing circuits form the reconstruction circuit group, and the associated circuit includes the second processing circuit which has the operation relation with the target processing circuit in the reconstruction circuit group.

In step S32, the target processing circuit obtains data to be operated according to the operation instruction sent by the first processing circuit, and performs an operation to obtain a first processing result.

Step S33, the target processing circuit sends the first processing result to the related circuit, so that the related circuit performs an operation according to its own second processing result and the first processing result to obtain a third processing result, and the reconfiguration circuit group obtains an intermediate result according to the third processing result and sends the intermediate result to the first processing circuit, where the second processing result is obtained by the related circuit performing an operation by acquiring data to be operated according to an operation instruction sent by the first processing circuit.

In one possible implementation manner, the reconfiguration circuit group determined according to the reconfiguration rule includes at least two second processing circuits. For the target processing circuit in the reconfiguration circuit group, an operation relationship exists between the target processing circuit and the associated circuit in the reconfiguration circuit group, which indicates that an operation is required between the processing result of the target processing circuit and the processing result of the associated circuit, and the result obtained by the operation may be an intermediate result of the reconfiguration circuit group, or may be an intermediate result obtained by further operation with the processing result of another second processing circuit in the reconfiguration circuit group. The operational relationship may be determined by a reconstruction rule. The target processing circuit in the reconfiguration circuit group may transmit its own processing result to the correlation circuit, and the correlation circuit may perform further operation. The reconfiguration circuit group may obtain an intermediate result from the processing result of the correlation circuit.

In one possible implementation, the second processing circuit may receive the operation instruction sent by the first processing circuit. That is, the master processing circuit may receive an operation instruction sent by the controller unit and forward the operation instruction to the slave processing circuit. The master processing circuit may also perform decomposition processing on the operation instruction sent by the controller unit, and then distribute the operation instruction to the corresponding slave processing circuits. The slave processing circuit can receive the operation instruction sent by the master processing circuit to perform operation.

In a possible implementation manner, the target processing circuit may send the first processing result to the association circuit, and the association circuit may obtain a third processing result after performing an operation on the first processing result and the second processing result of the association circuit. The correlation circuit can also send the third processing result to other second processing circuits in the reconstruction circuit group for further operation, so as to obtain an intermediate result of the reconstruction circuit group. For example, according to the reconfiguration rule, it is determined that the second processing circuit E, the second processing circuit F, and the second processing circuit G are included in the reconfiguration circuit group 3. The second processing circuit E sends the processing result to the second processing circuit F, the second processing circuit F performs accumulation operation on the processing result of the second processing circuit E and the processing result of the self processing circuit F to obtain an accumulated sum, the second processing circuit F sends the accumulated sum to the second processing circuit G, and the second processing circuit G performs accumulation operation on the received accumulated sum and the processing result of the self processing circuit G to obtain an intermediate result of the reconfiguration circuit group 3. It can be seen that the second processing circuit E needs to send the processing result to the second processing circuit F for further operation, and if the second processing circuit E is the target processing circuit, the second processing circuit F is a circuit associated with the second processing circuit E. The second processing circuit F needs to send the processing result to the second processing circuit G, and if the second processing circuit F is the target processing circuit, the second processing circuit G is a circuit associated with the second processing circuit F. The reconstruction circuit group obtains an intermediate result according to the processing result of the correlation circuit F.

In a possible implementation manner, the target processing circuit may send the first processing result to the association circuit, and the association circuit may perform an operation on the first processing result and the second processing result of the target processing circuit, so that an obtained third processing result is an intermediate result. The correlation circuit may send the intermediate result to the first processing circuit. For example, the reconfiguration circuit group 4 includes a second processing circuit X and a second processing circuit Y. The second processing circuit X sends its own first processing result to the second processing circuit Y, and the second processing circuit Y performs an operation according to its own second processing result and the received first processing result to obtain a third processing result, which is an intermediate result of the reconfiguration circuit group 4. The second processing circuit Y sends the third processing result to the first processing circuit.

In one possible implementation, the reconfiguration rules may specify the target processing circuit and associated circuits in the set of reconfiguration circuits. For example, the reconfiguration rule may directly specify that, in the reconfiguration circuit group 3, the second processing circuit E sends the processing result to the second processing circuit F, and the second processing circuit F sends the processing result to the second processing circuit G.

In a possible implementation manner, the reconfiguration rule may also determine an operation rule, and the reconfiguration circuit group may determine the target processing circuit and the associated circuit group in the reconfiguration circuit group according to the operation rule. The operation rule comprises that the second processing circuit which finishes the operation firstly sends the processing result to the second processing circuit which finishes the operation later. For example, in the reconfiguration circuit group 3, the second processing circuit F completes the operation first, and the second processing circuit F may transmit its own processing result to either one of the second processing circuit E and the second processing circuit G, which do not complete the operation, or to a designated second processing circuit E. The second processing circuit F is the target processing circuit and the second processing circuit E is the correlation circuit.

In this embodiment, in the reconfiguration circuit group, the target processing circuit sends the processing result to the associated circuit to enable the associated circuit to perform further operation, and the reconfiguration circuit group obtains an intermediate result according to the processing result of the associated circuit and sends the intermediate result to the first processing circuit. In the reconstruction circuit group, the target processing circuit and the associated circuit are determined according to the reconstruction rule, so that the operation relation in the reconstruction circuit group is clear, and the operation result is accurate and reliable.

In a possible implementation manner, the target processing circuit sends the processing result to a storage device, so that the correlation circuit performs an operation according to the processing result after extracting the processing result from the storage device.

In one possible implementation, the target processing circuit may send the processing results to the storage device instead of directly to the associated circuit. The storage device may be any second processing circuit in the reconfiguration circuit group except the target processing circuit and the associated circuit, or may be an on-chip storage device or an off-chip storage device configured in a circuit configuration in which the reconfiguration circuit group is located. The present disclosure does not limit the implementation form and the position setting of the storage device.

In one possible implementation, the association circuit may extract the processing result of the target processing circuit in the storage device and perform further operations according to the received operation instruction (including the reconfiguration operation instruction).

In this embodiment, the target processing circuit may transmit the processing result to the storage device, and the association circuit may perform the operation after extracting the processing result of the target processing circuit from the storage device. The target processing circuit sends the processing result to the storage device, so that the flexibility of the operation of the reconstruction circuit group can be improved, and the operation efficiency of the reconstruction circuit group can be improved.

In a possible implementation manner, the target processing circuit obtains the reconfiguration rule according to the operation instruction sent by the first processing circuit.

In one possible implementation, a preset reconstruction rule set composed of a plurality of reconstruction rules may be stored in a storage device in the circuit configuration. The first processing circuit may set a reconfiguration identifier in the operation instruction or the reconfiguration operation instruction, and the reconfiguration identifier may carry a number of the reconfiguration rule. The target processing circuit may extract the reconfiguration rule from the storage device where the reconfiguration rule set is located according to the received operation instruction sent by the first processing circuit, including according to the received reconfiguration operation instruction sent by the first processing circuit, and according to the operation instruction or the reconfiguration identifier in the reconfiguration operation instruction.

In this embodiment, the target processing circuit acquires the reconfiguration rule according to the operation instruction sent by the first processing circuit. The second processing circuit can flexibly acquire the reconstruction rule according to the operation instruction.

Fig. 4 shows a flow chart of a circuit reconfiguration method according to an embodiment of the present disclosure, the method being applied to a circuit configuration including a first processing circuit and a plurality of second processing circuits, as shown in fig. 4, the method including:

step S41, the target processing circuit determines a correlation circuit in a reconstruction circuit group according to a reconstruction rule, where the target processing circuit includes any one of the second processing circuits, the reconstruction rule includes using at least two of the second processing circuits to form a reconstruction circuit group, and the correlation circuit includes a second processing circuit in the reconstruction circuit group that has an operation relationship with the target processing circuit.

In step S42, the target processing circuit obtains data to be operated according to the operation instruction sent by the first processing circuit, and performs an operation to obtain a first processing result.

Step S43, the target processing circuit receives the second processing result sent by the association circuit, performs operation according to the second processing result and the first processing result to obtain a third processing result, and sends the intermediate result obtained by the reconstruction circuit group according to the third processing result to the first processing circuit, where the second processing result is obtained by the association circuit obtaining data to be operated according to the operation instruction sent by the first processing circuit.

In a possible implementation manner, the difference from the embodiment shown in fig. 3 is that the target processing circuit may receive the second processing result sent by the association circuit in the reconfiguration circuit group, and obtain a third processing result after performing an operation on the received second processing result and the first processing result of the target processing circuit. The target circuit can also send the third processing result to other second processing circuits in the reconstruction circuit group for further operation, and then an intermediate result of the reconstruction circuit group is obtained.

In a possible implementation manner, the target processing circuit receives the second processing result sent by the associated circuit in the reconfiguration circuit group, and obtains a third processing result, which is an intermediate result of the reconfiguration circuit group, after performing operation on the received second processing result and the first processing result of the target processing circuit.

In this embodiment, in the reconfiguration circuit group, the target processing circuit may receive the processing result sent by the associated circuit, and calculate the own processing result and the processing result sent by the associated circuit, so as to finally obtain an intermediate result of the reconfiguration circuit group. In the reconstruction circuit group, the target processing circuit and the associated circuit are determined according to the reconstruction rule, so that the operation relation in the reconstruction circuit group is clear, and the operation result is accurate and reliable.

Fig. 5 shows a flowchart of a circuit reconfiguration method according to an embodiment of the present disclosure, the method being applied to a circuit configuration including a first processing circuit and a plurality of second processing circuits, as shown in fig. 5, the method including:

step S51, the target processing circuit determines a correlation circuit in a reconstruction circuit group according to a reconstruction rule, where the target processing circuit includes any one of the second processing circuits, the reconstruction rule includes using at least two of the second processing circuits to form a reconstruction circuit group, and the correlation circuit includes a second processing circuit in the reconstruction circuit group that has an operation relationship with the target processing circuit.

In step S52, the target processing circuit obtains data to be operated according to the received operation instruction to perform operation, so as to obtain a first processing result.

Step S53, the target processing circuit sends the first processing result to the correlation circuit, so that the correlation circuit performs an operation according to its own second processing result and the first processing result to obtain a third processing result, and the reconstruction circuit group sends an intermediate result after obtaining the intermediate result according to the third processing result, where the second processing result is obtained by the correlation circuit performing an operation according to the operation instruction to obtain data to be operated.

In one possible implementation, the difference from the embodiment shown in fig. 3 is that the second processing circuit may receive an operation instruction sent by another device, for example, the second processing circuit may receive an operation instruction sent by the controller unit. Each second processing circuit in the reconfiguration circuit group determined according to the reconfiguration rule can complete the operation according to the received operation instruction to obtain a processing result of the second processing circuit, and the reconfiguration circuit group finally obtains an intermediate result of the reconfiguration circuit group according to the processing result of each second processing circuit. The intermediate results of the set of reconstruction circuits may be sent to the first processing circuit, stored in an associated storage device, or sent to another external device. The present disclosure is not limited thereto.

In a possible implementation manner, the target processing circuit in the reconfiguration circuit group may send the first processing result of the target processing circuit to the association circuit, and after the association circuit obtains the second processing result according to the received operation instruction, the association circuit may perform an operation on the first processing result and the second processing result to obtain a third processing result. The reconfiguration circuit group may obtain an intermediate result from the third processing result of the associated circuit group.

Fig. 6 shows a flowchart of a circuit reconfiguration method according to an embodiment of the present disclosure, the method being applied to a circuit configuration including a first processing circuit and a plurality of second processing circuits, as shown in fig. 6, the method including:

step S61, the target processing circuit determines a correlation circuit in a reconstruction circuit group according to a reconstruction rule, where the target processing circuit includes any one of the second processing circuits, the reconstruction rule includes using at least two of the second processing circuits to form a reconstruction circuit group, and the correlation circuit includes a second processing circuit in the reconstruction circuit group that has an operation relationship with the target processing circuit.

In step S62, the target processing circuit obtains data to be operated according to the received operation instruction, and performs an operation to obtain a first processing result.

Step S63, the target processing circuit receives the second processing result sent by the association circuit, performs operation according to the second processing result and the first processing result to obtain a third processing result, and enables the reconfiguration circuit group to obtain an intermediate result according to the third processing result and then send the intermediate result, where the second processing result is obtained by the association circuit performing operation on the data to be operated according to the operation instruction.

In a possible implementation manner, the target processing circuit in the reconfiguration circuit group may receive the second processing result sent by the associated circuit, the target processing circuit may perform an operation according to the first processing result of the target processing circuit and the second processing result of the associated circuit to obtain a third processing result, and the reconfiguration circuit group may obtain an intermediate result according to the third processing result of the target circuit.

In this embodiment, in the reconfiguration circuit group, the target processing circuit may receive the processing result sent by the associated circuit, the target processing circuit may perform an operation according to the processing result of the target processing circuit and the processing result of the associated circuit to obtain a third processing result, and the reconfiguration circuit group may obtain an intermediate result according to the third processing result of the target processing circuit. In the reconstruction circuit group, the target processing circuit and the associated circuit are determined according to the reconstruction rule, so that the operation relation in the reconstruction circuit group is clear, and the operation result is accurate and reliable.

Example 1

Fig. 7 is a block diagram of a computing device in a circuit reconfiguration method according to an embodiment of the present disclosure, where the computing device shown in fig. 7 is applied to perform machine learning calculation, and the computing device includes: an arithmetic unit and a controller unit; the arithmetic unit includes: a master processing circuit and a plurality of slave processing circuits;

the controller unit is used for acquiring data, a machine learning model and a calculation instruction, analyzing the calculation instruction to obtain a plurality of operation instructions, and sending the operation instructions and the data to the main processing circuit;

the master processing circuit is used for executing preamble processing on the data and transmitting data and operation instructions with the plurality of slave processing circuits;

the plurality of slave processing circuits are used for executing intermediate operation in parallel according to the data and the operation instruction transmitted from the master processing circuit to obtain a plurality of intermediate results and transmitting the plurality of intermediate results to the master processing circuit;

and the main processing circuit is used for executing subsequent processing on the plurality of intermediate results to obtain a calculation result of the calculation instruction.

In one possible implementation, the connection of the master processing circuit and the slave processing circuit may be a tree connection, where the master processing circuit is located at the root of the tree structure.

In one possible implementation, the slave processing circuits may also be distributed in a matrix, for example, a plurality of slave processing circuits may be distributed in an M × N matrix. Wherein M is the row number of the matrix, and N is the column number of the matrix.

In one possible implementation manner, the master processing circuit determines a reconfiguration circuit group according to a reconfiguration rule, where the reconfiguration rule includes that at least two slave processing circuits form a reconfiguration circuit group;

the main processing circuit sends an operation instruction to the reconstruction circuit group so that a slave processing circuit in the reconstruction circuit group obtains a processing result according to the operation instruction and obtains an intermediate result according to the processing result;

and the main processing circuit receives the intermediate result sent back by the reconstruction circuit group and obtains the operation result of the operation instruction according to the intermediate result.

In a possible implementation manner, a target processing circuit determines a related circuit in a reconstruction circuit group according to a reconstruction rule, the target processing circuit includes any slave processing circuit, and the related circuit includes a slave processing circuit in the reconstruction circuit group, which has an operation relation with the target processing circuit;

the target processing circuit acquires data to be operated according to the operation instruction sent by the main processing circuit and performs operation to obtain a first processing result;

and the target processing circuit sends the first processing result to the associated circuit so that the associated circuit performs operation according to a second processing result of the associated circuit and the first processing result to obtain a third processing result, the reconstruction circuit group obtains an intermediate result according to the third processing result of the associated circuit and sends the intermediate result to the main processing circuit, and the second processing result is obtained by the associated circuit performing operation according to the operation instruction sent by the main processing circuit to obtain data to be operated.

Example 2

The computation of convolutional layers in a neural network can be performed using a computing device such as that shown in fig. 7. In the computing device shown in fig. 7, the arithmetic unit is a master-slave architecture and includes a master processing circuit and K slave processing circuits. For a convolutional layer, the number of weights may be M. Each of the M weights may be distributed to a slave processing circuit and stored in an on-chip cache and/or register of the slave processing circuit. If M is less than or equal to K, a weight may be assigned to each slave processing circuit. If M > K, one or more weights may be assigned to each slave processing circuit.

In each slave processing circuit, for example the ith slave processing circuit, the received weight values Ai distributed by the master processing circuit may be stored in its registers and/or on-chip cache. The ith slave processing circuit can extract the weight Ai from the register and/or the on-chip buffer, and the processing result is obtained after the operation is carried out on the weight Ai and the input neuron data.

The master processing circuit may determine the set of reconstruction circuits according to a reconstruction rule including forming the set of reconstruction circuits with at least two of the slave processing circuits.

The processing results of each slave processing circuit within the set of reconstruction circuits may be accumulated and transmitted back to the master processing circuit. Partial sums obtained by the operation executed by each slave processing circuit in the reconstruction circuit group can be stored in a register and/or an on-chip cache of the slave processing circuit, and are transmitted back to the master processing circuit after the accumulation is finished; the partial sums obtained by the operation executed by each slave processing circuit in the reconfiguration circuit group can be stored in a register and/or an on-chip cache of the slave processing circuit for accumulation when a first setting condition is met, and can be transmitted to the main processing circuit for accumulation when a second setting condition is met.

Example 3

Fig. 8 shows a block diagram of an arithmetic unit in a circuit reconfiguration method according to an embodiment of the present disclosure, the arithmetic unit being applied to a computing apparatus that performs machine learning calculation, the computing apparatus including: an arithmetic unit and a controller unit. The computing device may be referred to as the computing device shown in fig. 7. As shown in fig. 8:

the arithmetic unit includes: a master processing circuit, a plurality of branch processing circuits and a plurality of slave processing circuits;

the main processing circuit is used for distributing an input neuron datum into a plurality of data blocks and sending at least one data block in the data blocks, a weight value and at least one operation instruction in a plurality of operation instructions to the branch processing circuit;

the branch processing circuit is configured to allocate the data block sent by the main processing circuit into a plurality of sub data blocks, and send at least one sub data block of the plurality of sub data blocks, a weight, and at least one operation instruction of the plurality of operation instructions to the slave processing circuit;

the plurality of slave processing circuits are used for executing operation on the received sub data blocks and the weight according to the operation instruction to obtain a processing result and transmitting the processing result to the branch processing circuit;

and the main processing circuit is used for carrying out subsequent processing on the processing result sent by the branch processing circuit to obtain a result of the calculation instruction, and sending the result of the calculation instruction to the controller unit.

In one possible implementation, the main processing circuit determines a first reconfiguration circuit group according to a reconfiguration rule, where the reconfiguration rule includes forming the first reconfiguration circuit group by using at least two of the branch processing circuits;

the main processing circuit sends an operation instruction to the first reconstruction circuit group so that a branch processing circuit in the first reconstruction circuit group obtains a processing result according to the operation instruction and obtains a first intermediate result according to the processing result;

and the main processing circuit receives a first intermediate result sent back by the first reconstruction circuit group and obtains an operation result of the operation instruction according to the first intermediate result.

In one possible implementation, the branch processing circuit determines a second reconfiguration circuit group according to a reconfiguration rule that includes composing the second reconfiguration circuit group with at least two of the slave processing circuits;

the branch processing circuit sends an operation instruction to the second reconstruction circuit group so that a slave processing circuit in the second reconstruction circuit group obtains a processing result according to the operation instruction and obtains a second intermediate result according to the processing result;

and the branch processing circuit receives a second intermediate result sent back by the second reconstruction circuit group and obtains a first intermediate result according to the second intermediate result.

Fig. 9 shows a block diagram of a reconstruction circuit according to an embodiment of the present disclosure, which comprises, as shown in fig. 9, a first processing circuit 10 and a plurality of second processing circuits 20, wherein:

the first processing circuit 10 is configured to determine a reconfiguration circuit group according to a reconfiguration rule, where the reconfiguration rule includes that at least two of the second processing circuits 20 form a reconfiguration circuit group;

the first processing circuit 10 is configured to send an operation instruction to the reconfiguration circuit group, so that the second processing circuit 20 in the reconfiguration circuit group obtains a processing result according to the operation instruction, and obtains an intermediate result according to the processing result;

the first processing circuit 10 is configured to receive the intermediate result sent back by the reconstruction circuit group, and obtain an operation result of the operation instruction according to the intermediate result.

In a possible implementation manner, the first processing circuit 10 is configured to send an operation instruction to the reconfiguration circuit group, so that the second processing circuit 20 in the reconfiguration circuit group obtains a processing result according to the operation instruction and obtains an intermediate result according to the processing result, and includes:

the first processing circuit 10 is configured to split the received operation instruction according to a reconfiguration rule to obtain a reconfiguration operation instruction;

the first processing circuit 10 is configured to send the reconfiguration operation instruction to the reconfiguration circuit group, so that the second processing circuit 20 in the reconfiguration circuit group obtains a processing result according to the reconfiguration operation instruction, and obtains an intermediate result according to the processing result.

In a possible implementation, the first processing circuit 10 is configured to determine a reconstruction rule according to a received operation instruction.

In a possible implementation manner, the first processing circuit 10 is configured to determine a reconstruction rule according to a received operation instruction, and includes:

the first processing circuit 10 is configured to search for the reconstruction rule in a set of reconstruction rules according to the reconstruction identifier in the operation instruction.

the first processing circuit 10 is configured to send an operation instruction to the reconfiguration circuit group, so that the second processing circuit 20 in the reconfiguration circuit group obtains a processing result according to the operation instruction, and performs at least one of the following operations on the processing result of the second processing circuit 20 in the reconfiguration circuit group to obtain the intermediate result: addition, accumulation, and multiplication.

In a possible implementation manner, the first processing circuit 10 is configured to receive an intermediate result sent back by the reconfiguration circuit group, and obtain an operation result of the operation instruction according to the intermediate result, and includes:

the first processing circuit 10 is configured to receive the intermediate result sent back by the reconstruction circuit group, and perform at least one of the following processing on the intermediate result to obtain an operation result of the operation instruction: addition operation, accumulation element operation, multiplication operation and activation operation.

In one possible implementation, the reconstruction circuit comprises a first processing circuit 10 and a plurality of second processing circuits 20, wherein:

the target processing circuit is used for determining a related circuit in a reconstruction circuit group according to a reconstruction rule, the target processing circuit comprises any one of the second processing circuits 20, the reconstruction rule comprises a reconstruction circuit group formed by at least two of the second processing circuits 20, and the related circuit comprises the second processing circuit 20 which is in an operational relationship with the target processing circuit in the reconstruction circuit group;

the target processing circuit is configured to obtain data to be operated according to the operation instruction sent by the first processing circuit 10 to perform operation, so as to obtain a first processing result;

the target processing circuit is configured to send the first processing result to the association circuit, so that the association circuit performs an operation according to a second processing result of the association circuit and the first processing result to obtain a third processing result, and the reconfiguration circuit group obtains an intermediate result according to the third processing result and sends the intermediate result to the first processing circuit 10, where the second processing result is obtained by the association circuit performing an operation by acquiring data to be operated according to an operation instruction sent by the first processing circuit 10.

In a possible implementation, the target processing circuit is configured to obtain a reconstruction rule according to an operation instruction sent by the first processing circuit 10.

the target processing circuit is used for determining an associated circuit in a reconstruction circuit group according to a reconstruction rule, the target processing circuit comprises any one second processing circuit 20, the reconstruction rule comprises a reconstruction circuit group formed by at least two second processing circuits 20, and the associated circuit comprises the second processing circuit 20 which has an operational relationship with the target processing circuit in the reconstruction circuit group;

the target processing circuit is configured to receive a second processing result sent by the association circuit, perform operation according to the second processing result and the first processing result to obtain a third processing result, and send the intermediate result obtained by the reconfiguration circuit group according to the third processing result to the first processing circuit 10, where the second processing result is obtained by the association circuit performing operation by obtaining data to be operated according to an operation instruction sent by the first processing circuit 10.

Fig. 10 is a block diagram of a combined processing device according to an embodiment of the present disclosure, as shown in fig. 10, which includes the neural network operation device, the universal interconnection interface, and other processing devices described above.

The neural network arithmetic device interacts with other processing devices to jointly complete the operation designated by the user. Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the neural network arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the neural network arithmetic device; other processing devices can cooperate with the neural network arithmetic device to complete the arithmetic task. And the universal interconnection interface is used for transmitting data and control instructions between the neural network arithmetic device and other processing devices. The neural network arithmetic device acquires required input data from other processing devices and writes the input data into a storage device on the neural network arithmetic device chip; control instructions can be obtained from other processing devices and written into a control cache on a neural network arithmetic device chip; and the data in the storage module of the neural network arithmetic device can also be read and transmitted to other processing devices.

The combined processing device may further include a storage device, and the storage device is connected to the neural network operation device and the other processing device, respectively. The storage device is used for storing data in the neural network arithmetic device and the other processing devices, and is particularly suitable for data which are required to be calculated and cannot be stored in the internal storage of the neural network arithmetic device or the other processing devices.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the overall power consumption is reduced. In this case, the generic interconnect interface of the combined processing device is connected to some component of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

In a possible implementation manner, the present disclosure further provides a neural network chip, which includes the above neural network operation device or the combined processing device.

In a possible implementation manner, the present disclosure further provides a chip packaging structure, which includes the above chip.

In a possible implementation manner, the disclosure further provides a board card, which includes the chip packaging structure.

In a possible implementation manner, the present disclosure further provides an electronic device, which includes the board card.

Electronic devices include data processing apparatus, robots, computers, printers, scanners, tablets, smart terminals, mobile phones, tachographs, navigators, sensors, cameras, servers, cloud servers, cameras, video cameras, projectors, watches, headsets, mobile storage, wearable devices, vehicles, household appliances, and/or medical devices.

The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance instrument, a B ultrasonic instrument and/or an electrocardiograph.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules are not necessarily required for the disclosure.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.

The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, and various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps of the methods of the above embodiments may be implemented by a program, which is stored in a computer-readable memory, the memory including: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The above embodiments of the present disclosure are described in detail, and specific examples are applied herein to explain the principles and implementations of the present disclosure, and the description of the above embodiments is only used to help understand the method and its core idea of the present disclosure; meanwhile, for a person skilled in the art, based on the idea of the present disclosure, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present disclosure should not be construed as a limitation to the present disclosure.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method of operation, the method being applied to a circuit arrangement comprising a first processing circuit and a plurality of second processing circuits, the method comprising:

the first processing circuit receives the intermediate result sent back by the reconstruction circuit group and obtains the operation result of the operation instruction according to the intermediate result;

the first processing circuit determines a reconfiguration circuit group according to a reconfiguration rule, and the reconfiguration circuit group comprises:

the first processing circuit receives the operation instruction, and the operation instruction carries a reconstruction identifier;

and the first processing circuit searches the reconstruction rule from a preset reconstruction rule set according to the reconstruction identifier.

2. The method according to claim 1, wherein the first processing circuit sends an operation instruction to the set of reconstruction circuits, so that a second processing circuit in the set of reconstruction circuits obtains a processing result according to the operation instruction and obtains an intermediate result according to the processing result, and the method comprises:

and the first processing circuit sends the reconstruction operation instruction to the reconstruction circuit group so that a second processing circuit in the reconstruction circuit group obtains a processing result according to the reconstruction operation instruction and obtains an intermediate result according to the processing result.

3. The method according to claim 1, wherein the first processing circuit sends an operation instruction to the reconfiguration circuit group, so that a second processing circuit in the reconfiguration circuit group obtains a processing result according to the operation instruction and obtains an intermediate result according to the processing result, and the method comprises:

4. The method according to any one of claims 1 to 3, wherein the first processing circuit receives the intermediate result sent back by the reconstruction circuit group and obtains the operation result of the operation instruction according to the intermediate result, and comprises:

5. A method of operation, the method being applied to a circuit arrangement comprising a first processing circuit and a plurality of second processing circuits, the method comprising:

the target processing circuit acquires data to be operated according to the operation instruction sent by the first processing circuit to operate, and a first processing result is obtained;

6. The method of claim 5, further comprising:

7. The method of claim 5 or 6, further comprising:

8. An arithmetic circuit, characterized in that the arithmetic circuit comprises a first processing circuit and a plurality of second processing circuits, wherein:

the first processing circuit is used for sending an operation instruction to the reconstruction circuit group so that a second processing circuit in the reconstruction circuit group obtains a processing result according to the operation instruction and obtains an intermediate result according to the processing result;

the first processing circuit is used for receiving the intermediate result sent back by the reconstruction circuit group and obtaining the operation result of the operation instruction according to the intermediate result;

9. The arithmetic circuit of claim 8, wherein the first processing circuit is configured to send an arithmetic instruction to the reconfiguration circuit group, so that a second processing circuit in the reconfiguration circuit group obtains a processing result according to the arithmetic instruction and obtains an intermediate result according to the processing result, and the arithmetic circuit comprises:

10. The arithmetic circuit of claim 8, wherein the first processing circuit is configured to send an arithmetic instruction to the set of reconfigurable circuits, so that a second processing circuit in the set of reconfigurable circuits obtains a processing result according to the arithmetic instruction and obtains an intermediate result according to the processing result, and the first processing circuit comprises:

11. The arithmetic circuit according to any one of claims 8 to 10, wherein the first processing circuit is configured to receive an intermediate result sent back by the reconstruction circuit group, and obtain an arithmetic result of the arithmetic instruction according to the intermediate result, and includes:

12. An arithmetic circuit, comprising a first processing circuit and a plurality of second processing circuits, wherein:

the target processing circuit is used for acquiring data to be operated according to the operation instruction sent by the first processing circuit to operate to obtain a first processing result;

13. The operational circuit of claim 12, wherein the target processing circuit is configured to send the processing result to a storage device, so that the correlation circuit performs an operation according to the processing result after extracting the processing result from the storage device.

14. The arithmetic circuitry of claim 12 or 13, wherein the target processing circuitry is configured to obtain the reconstruction rule in dependence on an arithmetic instruction sent by the first processing circuitry.

15. A neural network operation device, comprising one or more operation circuits according to any one of claims 8 to 14, wherein the neural network operation device is configured to perform a set neural network operation.

16. A combined computing device, comprising one or more of the neural network computing device of claim 15, a universal interconnect interface, and other processing devices;

17. A neural network chip, comprising: an arithmetic circuit as claimed in any one of claims 8 to 14; or

The neural network operation device of claim 15; or

A combinational operation device as described in claim 16.

18. An electronic device, characterized in that the electronic device comprises:

an arithmetic circuit as claimed in any one of claims 8 to 14; or

The neural network operation device of claim 15; or

A combinational operation device according to claim 16; or

The neural network chip of claim 17.