RU208046U1 - Pulse repetition rate measurement unit - Google Patents

Abstract

The utility model relates to measuring technology and can be used in devices for monitoring environmental parameters for encoding signals from frequency sensors. pulse repetition rate, containing a generator, a reference frequency counter, a measured frequency counter, the first D-flip-flop, an AND element, an input bus, a bus for the number of reference pulses, a bus for the number of input pulses, and the output of the first D-flip-flop is connected to the first input of the AND element, additionally contains a trigger bus and a programmable logic integrated circuit (FPGA), in which a reference frequency counter, a measured frequency counter, the first D-trigger, an AND element are designed, the second D-trigger, an S-trigger, an OR element are additionally designed in the FPGA, while the counter reference frequency and counter lost frequency, synchronous, multi-bit, have a clock input and count enable input, the reference frequency counter has an overflow output, the first and second D-flip-flops, synchronous, have a clock input and information input, S-trigger, synchronous, has a clock input, setting input to logical "1" and the setting input to logical "0", the AND, OR elements have two inputs each, while the trigger bus is connected to the first FPGA input, the generator output is connected to the second FPGA input, the input bus is connected to the third FPGA input, the bus number of reference pulses is connected bit by bit to a group of fourth FPGA inputs, the bus of the number of input pulses is connected bit by bit to a group of fifth FPGA inputs, the first input of the FPGA is connected inside the FPGA to the information input of the first D-trigger, the output of the first D-trigger is connected to the information input of the second D-trigger , the inverse output of the second D-flip-flop is connected to the second input of the AND element, the output of the AND element is connected to the input of the setting to logic "1" of the S-flip-flop, the output The S-flip-flop code is connected to the count enable input of the reference frequency counter and to the count enable input of the measured frequency counter, the bit outputs of the reference frequency counter are connected bit by bit to a group of fourth inputs of the FPGA inside the FPGA, the overflow output of the reference frequency counter is connected to the first input of the OR element, the second input The FPGA is connected inside the FPGA to the clock input of the first D-trigger and the second D-trigger, to the clock input of the S-trigger, to the clock input of the reference frequency counter, the third FPGA input is connected inside the FPGA to the clock input of the measured frequency counter, the bit outputs of which are connected bit by bit to by a group of fifths, by the FPGA input inside the FPGA, the output of the high-order digit of the measured frequency counter is connected to the second input of the OR element, the output of which is connected to the setting input to the logical "0" of the S-flip-flop. 1 ill.

Description

The utility model relates to measuring technology and can be used in devices for monitoring environmental parameters for coding signals from frequency sensors.

The closest to the claimed block (prototype) is a device for measuring the pulse repetition rate [1], which contains a generator, a counter of the reference frequency, the overflow output of which is connected to the first input of the OR-NOT element, the output of the D-flip-flop through the AND element is connected to the counting input counter of the measured frequency, the second input of the AND element is the input of the device, the delay element and the register, and the generator output through the delay element is connected to the C-input of the trigger, the output of which is connected to the control input of the register, the bit inputs of which are connected to the corresponding bit outputs of the reference frequency counter, the input which is connected to the generator output, the output of the highest bit of the counter of the measured frequency is connected to the second input of the OR-NOT element, the inverse output of which is connected to the D-input of the trigger, the information outputs of the device are the bit outputs of the counter of the measured frequency and the register outputs.

The disadvantage of the prototype is the low reliability of the frequency measurement due to the lack of synchronization of the output data and the end of the measurement. Output data - the number of reference pulses, set at the information outputs of the device from the register in which the code of the number of reference pulses from the bit outputs of the reference frequency counter is latched (written). The end of the measurement occurs when the log is installed. "0" at the output of the D-flip-flop after half of the counter capacity of the measured frequency has been set. Synchronization of the D-trigger setting in the log. "0" and writing the code of the reference frequency counter to the register in the prototype is absent. Writing the code of the counter of the reference frequency to the register occurs at the log level. "0" at the control input of the register. Log level. "0" is set to the control input of the register from the output of the D-flip-flop. The reference frequency counter and D-flip-flop are clocked by the generator pulses. The reference frequency counter code arrives at the register with a delay relative to the clock pulses due to the delay in the reference frequency counter microcircuit and the data transmission delay in the communication lines. Log level. "0" at the control input of the register also arrives with a delay relative to the clock pulses due to the delay in the D-flip-flop microcircuit and the propagation delay in the communication line. The delays of the code of the reference frequency counter and the signal at the control input of the register are not equal to each other, as a result of which there is no synchronization of the output data and the end of the measurement. If the delay in transferring the code from the reference frequency counter to the register turns out to be greater than the delay of the register control signal, the register will latch the code preceding the end of the measurement, that is, unreliable. In the prototype for this case, a delay element is provided in the form of an RC-circuit between the generator and the D-flip-flop. But choosing the right amount of delay can be practically difficult, since the delays in microcircuits vary from sample to sample and depend on temperature and other factors. Possible unreliability of data on the number of reference pulses reduces the reliability of measurements in the prototype.

The technical result of the utility model is to increase the reliability of frequency measurement, due to the introduction of synchronization of the output data and the end of the measurement.

The technical result is achieved by the fact that the unit for measuring the pulse repetition rate, containing the generator, the counter of the reference frequency, the counter of the measured frequency, the first D-flip-flop, the I element, the input bus, the bus for the number of reference pulses, the bus for the number of input pulses, and the output of the first D-flip-flop connected to the first input of the AND element, additionally contains a start bus and a programmable logic integrated circuit (FPGA), in which the counter of the reference frequency, the counter of the measured frequency, the first D-flip-flop, the AND element are designed, in the FPGA, the second D-flip-flop is additionally designed, S- trigger, OR element, while the counter of the reference frequency and the counter of the measured frequency, synchronous, multi-bit, have a clock input and an input for counting permission, the counter of the reference frequency has an overflow output, the first and second D-flip-flops, synchronous, have a clock input and an information input, S-flip-flop, synchronous, has a clock input, set input to logic "1" and input set to logic "0" ", Elements AND, OR have two inputs each, while the start bus is connected to the first input of the FPGA, the generator output is connected to the second input of the FPGA, the input bus is connected to the third input of the FPGA, the bus of the number of reference pulses is bitwise connected to the group of fourth inputs of the FPGA, the bus the number of input pulses is bitwise connected to the group of the fifth FPGA inputs, the first FPGA input is connected inside the FPGA to the information input of the first D-flip-flop, the output of the first D-flip-flop is connected to the information input of the second D-flip-flop, the inverse output of the second D-flip-flop is connected to the second input of the element And, the output of the AND element is connected to the input of the setting in the logical "1" of the S-flip-flop, the output of the S-flip-flop is connected to the input of the counter of the reference frequency counter and to the input of the counter of the counter of the measured frequency, the bit outputs of the counter of the reference frequency are bitwise connected to the group of fourth inputs FPGA inside FPGA, the overflow output of the reference frequency counter is connected to the first input of the OR element, the second The 1st FPGA input is connected inside the FPGA with the clock input of the first D-flip-flop and with the clock input of the second D-flip-flop, with the clock input of the S-flip-flop, with the clock input of the reference frequency counter, the third input of the FPGA is connected inside the FPGA with the clock input of the measured frequency counter, bit the outputs of which are bitwise connected to the group of fifths by the FPGA input inside the FPGA, the output of the high-order bit of the measured frequency counter is connected to the second input of the OR element, the output of which is connected to the set input to the logical "0" of the S-flip-flop.

The drawing shows a block diagram.

Accepted designations in the drawing:

designations without position numbers:

starting bus;

input bus;

bus of the number of reference pulses;

bus of the number of input pulses;

1 - generator;

2 - programmable logic integrated circuit FPGA, the FPGA uses the first input, the second input, the third input, a group of fourth inputs, a group of fifth inputs;

FPGA 2 contains:

3 - the first D-flip-flop, synchronous, has a clock input "C", information input "D";

4 - the second D-flip-flop, synchronous, has a clock input "C", information input "D";

5 - element And, has two entrances;

6 - S-flip-flop, synchronous, has a clock input "C", input "S" set to logic "1", input "R" set to logic "0". Setting the S-flip-flop to logic "1" occurs on a clock pulse provided there is a logic level "1" at the input of the setup to logic "1", setting to logic "0" occurs on a clock pulse, provided that a level of logic "1" is present at the input of the setup to logical "0";

7 - counter of the reference frequency, multi-bit, synchronous, has a clock input "C", an input "En" for counting enable, an output "Cout" of overflow. Performs binary counting of clock pulses, provided that a logic level "1" is present at the counting enable input;

8 - counter of the measured frequency, multi-digit, synchronous, has a clock input "C", input "En" for counting enable. Performs binary counting of input pulses, provided that a logic level "1" is present at the count enable input;

9 - OR element, has two inputs.

The unit for measuring the pulse repetition rate contains (see drawing) generator 1, counter 7 of the reference frequency, counter 8 of the measured frequency, the first D-flip-flop 3, element AND 5, an input bus, a bus for the number of reference pulses, a bus for the number of input pulses, a start bus, programmable logic integrated circuit (FPGA) 2, in which counter 7, counter 8, D-flip-flop 3, AND element 5, second D-flip-flop 4, S-flip-flop 6, OR element 9 are designed, the trigger bus is connected to the first input of the FPGA 2 , the output of the generator 1 is connected to the second input of the FPGA 2, the input bus is connected to the third input of the FPGA 2, the bus of the number of reference pulses is connected bit by bit to the group of the fourth inputs of the FPGA 2, the bus of the number of input pulses is connected bit by bit to the group of the fifth inputs of the FPGA 2, the first input of the FPGA is 2 connected inside FPGA 2 with the information input of the D-flip-flop 3, the output of the D-flip-flop 3 is connected to the information input of the D-flip-flop 4 and with the first input of the AND element 5, the inverse output of the D-flip-flop 4 is connected to the second input of the AND element 5 , the output of the element And 5 is connected to the input of the installation in the log. "1" of the S-flip-flop 6, the output of the S-flip-flop 6 is connected to the input of the counter 7 and to the input of the counter 8, the bit outputs of the counter 7 are bitwise connected to the group of the fourth inputs of the FPGA 2 inside the FPGA 2, the overflow output of the counter 7 is connected to the first input of the OR element 9, the second input of the FPGA 2 is connected inside the FPGA 2 with the clock input of the D-flip-flop 3 and with the clock input of the D-flip-flop 4, with the clock input of the S-flip-flop 6, with the clock input of the counter 7, the third input of the FPGA 2 is connected internally FPGA 2 with the clock input of the counter 8, the bit outputs of which are bitwise connected to the group of the fifth inputs of the FPGA 2 inside the FPGA 2, the output of the most significant bit of the counter 8 is connected to the second input of the OR element 9, the output of which is connected to the input of the installation in the log. "0" S-flip-flop 6.

Generator 1 is used to generate highly stable reference pulses (clock pulses), which are fed to the second input (clock) of FPGA 2. Generator 1 can be performed, for example, on a B525CEM3 100.000MHZ chip from BFC (Brookdale Frequency Controls), which generates rectangular pulses in logic levels with a frequency of 100 MHz with a relative stability of 5 × 10 ^-6 .

The input bus is used to receive input pulses of the measured frequency of electrical voltage in logic levels.

The trigger bus is used to receive a trigger pulse of electrical voltage at logic levels, which triggers the start of the measurement.

The bus of the number of reference pulses is an output information bus on which the binary code of the number of reference pulses from the counter 7 is set.

The bus of the number of input pulses is an output information bus on which the binary code of the number of counted input pulses from counter 8 is set.

The measured frequency is equal to the reference frequency multiplied by the number of input pulses and divided by the number of reference pulses.

In FPGA 2, the first D-flip-flop 3, the second D-flip-flop 4, I element 5, S-flip-flop 6, counter 7 of the reference frequency, counter 8 of the measured frequency, element OR 9 are designed using software. , for example, the programmable logic integrated circuit EP3C16F484C6 of the Cyclone III family by ALTERA, which has the following resources: 15.5 thousand logic elements, 20 dedicated clock synchronization lines, four clock inputs, the total number of inputs is 484. The maximum switching frequency of triggers and counters in the FPGA is 2 - 330 MHz. The program for configuring the FPGA 2 is stored, for example, in an EPCS16SI8 flash memory chip from ALTERA, which contains 16 Kb of memory (the Flash memory chip is not shown in the drawing).

The first D-flip-flop 3, element I 5, the second D-flip-flop 4 serve to bind the start pulse to the clock pulses of the generator 1. At the output of element I 5, a pulse is formed with a duration equal to the period of the clock pulses, the front of which coincides with the front of the clock pulse with a small delay , following the first after the leading edge of the trigger pulse. The pulse at the output of the element And 5 allows you to set the trigger pulse S-flip-flop 6 in the log. "1" is synchronous with clock pulses.

The pulse at the output of the S-flip-flop 6 controls the counter 7 and counter 8 synchronously with the clock pulses.

After reaching half of the capacity in the counter 8 (in order to ensure the specified frequency measurement accuracy), the high bit of the counter 8 initiates the synchronous termination of the counting of the reference frequency periods in the counter 7.

Generator 1 is mounted on a common PCB using bulk mounting, FPGA 2 is mounted on a common PCB using surface mounting. The input bus, the start bus, the bus for the number of reference pulses, the bus for the number of input pulses, and the connection of the generator 1 to the FPGA 2 are made on a common printed circuit board by a printed circuit. The general printed circuit board is not shown in the drawing.

The drawing does not show the power supply of generator 1 and FPGA 2.

The unit for measuring the pulse repetition rate operates as follows. The description is based on the drawing.

It is assumed that power is supplied to generator 1 and FPGA 2. It is also assumed that the configuration program is loaded into FPGA 2 from the Flash memory chip.

In the initial state, D-flip-flop 3, D-flip-flop 4, S-flip-flop 6, counter 7, counter 8 are zeroed (zeroing circuits are not shown in the drawing). At the output of the D-flip-flop 3, S-flip-flop 6, at the output of the overflow of the counter 7, at the output of the high-order bit of the counter 8, the log level is set. "0", at the inverse output of the D-flip-flop 4, the log level is set. "one". Log level. "0" from the output of the D-flip-flop 3 through the element And 5 is fed to the input of the installation in the log. "1" S-flip-flop 6 and prohibits the installation of S-flip-flop 6 in the log. "1" for clock pulses. Log level. "0" from the output of the S-flip-flop 6 goes to the enable input of the counter 7, to the enable input of the counter 8 and prohibits the counting of pulses.

The pulses of generator 1 are fed to the second input (clock) of FPGA 2. Inside FPGA 2, clock pulses are propagated along dedicated clock lines with the same minimum delay. Clock pulses are fed to the clock input of D-flip-flop 3, D-flip-flop 4, S-flip-flop 6, counter 7. Clock pulses synchronize the operation of triggers and a counter inside FPGA 2, excluding failures at a high clock frequency, when impulse propagation delays inside FPGA 2 are affected ...

Input pulses of the measured frequency go to the third input of FPGA 2. Inside FPGA 2, they go to the clock input of counter 8.

Before the start pulse arrives at the start bus, the clock and input pulses do not change the initial state of counters 7 and 8, since the log level is set at the input for enabling the counting of counter 7 and counter 8. "0" from the output of the S-flip-flop 6. Level log. "0" at the output of the S-flip-flop 6 is held until log. "0" is present at the input of the installation in the log. "1" S-trigger 6. At the entrance to the installation in the log. "1" S-trigger 6 log. "0" is set from the output of the D-flip-flop 3 through the AND element 5.

At an arbitrary moment in time, a start pulse is sent to the start bus. "1", which initiates the start of measuring the frequency of the input pulses. The start pulse through the first input of FPGA 2 is fed inside FPGA 2 to the information input D-flip-flop 3. The first clock pulse that came first to the clock input of D-flip-flop 3 after the front of the start pulse, that is, after the transition log. "0" on the log. "1" on the start bus, writes a log. "1" in D-flip-flop 3. At the output of D-flip-flop 3 there is a transition log. "0" on the log. "1" with a small delay relative to the front of the first clock pulse. Log level. "1" from the output of the D-flip-flop 3 is fed to the information input of the D-flip-flop 4 and to the first input of the AND element 5. The second clock pulse after the front of the start pulse writes a log. "1" in the D-flip-flop 4. At the inverse output of the D-flip-flop 4 there is a transition log. "1" on the log. "0" with a small delay relative to the leading edge of the second clock pulse. Log level. "0" from the inverse output of the D-flip-flop 4 is fed to the second input of the AND element 5. The AND element 5 compares the logic levels at the first and second inputs by logic AND. Matching log levels. "1" occurs in the time interval between the edges of the first and second clock pulses. At the output of the element And 5, a log pulse is formed. "1" of duration equal to the period of the clock pulses, slightly delayed relative to the edges of the first and second clock pulses. The pulse from the output of the element And 5 is fed to the input of the installation in the log. "1" (S-input) S-flip-flop 6, allowing the installation of S-flip-flop 6 in the log. "one". The second clock pulse after the front of the start pulse sets the S-flip-flop 6 to log. "1", since the front of the second clock pulse is within the pulse duration at the S-input of the S-flip-flop 6 due to a small pulse delay in the AND element 5. Level log. "1" from the output of the S-flip-flop 6 with a small delay relative to the front of the second clock pulse is fed to the enable input of the counter 7 and to the input of the enable counter of the counter 8. Level log. "1" at the counting enable input enables counting clock pulses in counter 7 and counting input pulses in counter 8. Counter 7 on each clock pulse adds one at the bit outputs, starting from the third clock pulse due to the delay setting log. "1" at the output of the S-flip-flop 6. The measurement time begins with the second clock pulse, since after the front of the second clock pulse, counters 7 and 8 open. Counter 8 counts the input pulses. The noted small delays are due to the trigger response delays in FPGA 2 and are less than 1 ns.

When the counter 8 reaches half the capacity, the log level appears at the output of the most significant bit of counter 8. "1", which through the OR element 9 enters the input of the installation in the log. "0" (R-input) S-flip-flop 6. The clock pulse that came first to the clock input of the S-flip-flop 6 after setting the log. "1" at the R-input of the S-flip-flop 6, sets the S-flip-flop 6 to log. "0" with a little delay. The clock pulse that sets the S-flip-flop 6 to log. "0", adds one at the bit outputs of the counter 7. Level log. "0" from the output of the S-flip-flop 6 goes to the enable input of the counter 7 and to the enable input of the counter 8. The counting of impulses in the counter 7 and in the counter 8 stops. The measurement ends. Counter 7 stores the code for the number of reference pulses, counter 8 stores the code for the number of input pulses counted. The end of the measurement and the counting of the number of reference pulses occur synchronously at the same clock pulse. The number of reference pulses is reliably related to the end of the measurement and is valid.

The measurement time is equal to the duration of the log hold. "1" at the output of the S-flip-flop 6. Level log. "1" at the output of the S-flip-flop 6 is set on the front of the clock pulse after the front of the start pulse and is reset to log. "0" on the front of the clock pulse after the counter 8 reaches half the capacity. The code at the bit outputs of the counter 7 is equal to an integer number of periods of the reference frequency.

In the case of a high frequency of input pulses, the count of which to half the capacity of the counter 8 occurs during one period of the reference frequency, the code of the number of reference pulses in the counter 7 will be equal to one. In this case, on the front of the second clock pulse, counter 7 will open, and on the front of the third clock pulse, it will close. On the front of the third clock pulse, counter 7 will add one at the bit outputs.

In the case of a low frequency of input pulses, counter 7 overflow occurs before half of the capacity is set by counter 8. In this case, a log is set on all bit outputs of counter 7. "1", and at the output of the overflow counter 7 appears a log pulse. "1", which passes through the OR element 9 to the R-input of the S-flip-flop 6. Level log. "1" at the R-input allows the next clock pulse to set the S-flip-flop 6 to log. "0". The next clock pulse sets the log. "0" at the output of the S-flip-flop 6 and at all bit outputs of the counter 7. Log level. "0" from the output of the S-flip-flop 6 goes to the enable input of the counter 7 and prohibits the counting of pulses in the counter 7. The counter 7 stops in the log state. "0" on all bit outputs. Log level. "0" at all bit outputs of the counter 7 indicates the impossibility of achieving the specified accuracy of measuring the input frequency even during the maximum measurement time.

The code of the number of reference pulses at the bit outputs of the counter 7 through the group of the fourth inputs of the FPGA 2 is bitwise fed to the bus of the number of reference pulses. The code of the number of input pulses at the bit outputs of the counter 8 through the group of the fifth inputs of the FPGA 2 is bitwise fed to the bus of the number of input pulses. The measured repetition rate of the input pulses in the block is equal to the frequency of generator 1 multiplied by the number of input pulses (counter code 8) and divided by the number of reference pulses (counter code 7).

The data on the bus of the number of reference pulses and the end of the measurement are synchronized, since the end of the count of the number of reference pulses in the counter 7 and the reset of the S-flip-flop 6 to the log. "0" occurs synchronously with the clock pulse. The code in the counter 7 of the reference frequency is valid with high reliability. The reliability of the pulse repetition rate measurement is increased.

Thus, the claimed technical result is achieved, namely: increasing the reliability of frequency measurement, due to the introduction of synchronization of the output data and the end of the measurement.

Sources of information

1. Patent RU 2054681 C1, IPC G01R 21/10, 20.02.1996.

Claims (1)

A pulse repetition rate measuring unit containing a generator, a reference frequency counter, a measured frequency counter, the first D-flip-flop, an AND element, an input bus, a bus for the number of reference pulses, a bus for the number of input pulses, and the output of the first D-flip-flop is connected to the first input of the AND element , characterized in that it additionally contains a start bus and a programmable logic integrated circuit (FPGA), in which the reference frequency counter, the measured frequency counter, the first D-flip-flop, the AND element are designed, in the FPGA, the second D-flip-flop, S-flip-flop are additionally designed, OR element, while the counter of the reference frequency and the counter of the measured frequency, synchronous, multi-bit, have a clock input and an input for counting permission, the counter of the reference frequency has an overflow output, the first and second D-flip-flops, synchronous, have a clock input and an information input, S- trigger, synchronous, has a clock input, an input to set to logical "1" and an input to set to logical "0", elements AND, OR them There are two inputs each, while the start bus is connected to the first input of the FPGA, the generator output is connected to the second input of the FPGA, the input bus is connected to the third input of the FPGA, the bus of the number of reference pulses is connected bit by bit to the group of fourth inputs of the FPGA, the bus of the number of input pulses is connected bit by bit to a group of fifth FPGA inputs, the first FPGA input is connected inside the FPGA to the information input of the first D-flip-flop, the output of the first D-flip-flop is connected to the information input of the second D-flip-flop, the inverse output of the second D-flip-flop is connected to the second input of the AND element, the output of the AND element is connected with the input of setting to the logical "1" of the S-flip-flop, the output of the S-flip-flop is connected to the input of the counter of the reference frequency counter and to the input of the resolution of the counter of the measured frequency, the bit outputs of the counter of the reference frequency are bitwise connected to the group of the fourth input of the FPGA inside the FPGA, the overflow output the counter of the reference frequency is connected to the first input of the OR element, the second input of the FPGA is connected inside the FPGA with the clock input of the first D-flip-flop and with the clock input of the second D-flip-flop, with the clock input of the S-flip-flop, with the clock input of the reference frequency counter, the third input of the FPGA is connected inside the FPGA with the clock input of the measured frequency counter, the bit outputs of which are connected bitwise with a group of fifths by the FPGA input inside the FPGA, the output of the most significant bit of the counter of the measured frequency is connected to the second input of the OR element, the output of which is connected to the input of the setting to the logical "0" of the S-flip-flop.

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