RU2075755C1 - Electronic active energy meter - Google Patents

Abstract

FIELD: electrical measurement technology; measurement of ac active energy consumption. SUBSTANCE: meter has two integrating voltage-to-frequency converters, a standard frequency generator, an equivalence unit, and a reversible counter. Feedback pulse width in the first converter is determined by the generator period and in the second converter by the period of first converter output pulses. First and second converter inputs are connected to the outputs of a voltage transducer and a current transducer, respectively. Integrating circuit in each of the converters has a voltage difference-to-current converter and an integrating capacitor connected to its output. Transistor gates controlled by comparators maintain constant sign of voltage at first and second converter outputs. Comparator outputs are also connected to inputs of the equivalence unit. Output of the unit is connected to the up-down input of the counter. Highest order digit output of the counter serves a frequency output of the meter. EFFECT: improved design. 3 dwg

Description

 The invention relates to electrical engineering, in particular to devices for measuring the consumption of active electric energy of alternating current of industrial frequency.

 Known meters of active energy and active power [1, 2] containing voltage to frequency converters, reversible counters, frequency dividers, input measuring voltage and current converters.

 Closest to the proposed is a converter of active energy into a digital code [2] containing an input unit, two voltage to frequency converters, a reversible counter, a binary multiplier.

 The disadvantage of this device is its complexity, in addition, its disadvantages include the low accuracy and lack of frequency output, which is preferred for measuring devices of telemechanized information and computing systems. The difficulty is due to the introduction of a binary multiplier containing two counters, two registers, a frequency divider, delay elements, a controlled frequency divider, a reference frequency generator, and pulse-potential valves.

 The listed elements also reduce accuracy, since they cause a number of time delays and corresponding measurement errors, which increase with increasing levels and the number of harmonics in the current and voltage curves of the network.

 The aim of the invention is to simplify the device, increasing its accuracy and providing a frequency output. Simplification is achieved by eliminating a separate multiplier block. The multiplication function is implemented by the interaction of the first and second voltage to frequency converters without introducing additional elements complicating the device.

 The first essential feature is the formation of negative feedback pulses in the second servo voltage to frequency converter using the first voltage to frequency converter in such a way that the durations of these pulses are equal to the period of the output pulses of the first converter.

 The main source of error of the tracking voltage-to-frequency converter on a specific amplifier (op-amp) is the zero-drift of the op-amp, which in the integration mode is approximately 10 times greater than in the proportional (scale) mode. The construction of a voltage-to-current difference converter using an op-amp and connecting an integrating capacitor to its output makes it possible to provide an op-amp mode close to proportional, i.e. significantly reduce the zero drift of the opamp. In addition, the integrating capacitor is connected with a single output to a common point in the circuit, which reduces the effect of various noise.

 Thus, the second essential feature of the device is the use of a voltage difference to current converter in each voltage to frequency converter.

 The third essential feature is the use of key circuits on integrated circuits at the inputs of voltage converters to the frequency of alternating voltages and control of these key circuits using comparators. This allows you to ensure the minimum value of the rectification error and, in addition, simplify the control logic of the reversible counter, which operates in the summation mode when the signs of voltage and current of the controlled network are equal and in the subtraction mode for different signs of voltage and current.

 In FIG. 1 is a diagram of an electronic active energy meter; FIG. 2 and FIG. 3 shows voltage diagrams.

 The active energy meter consists of two voltage converters in frequency 1 (VLF1) and 2 (VLF2), an equivalence element 3 (ER3), a reversible counter-frequency divider 4 (PC), an electromechanical counter 5 (EMC), a voltage measuring transducer 6 (IPN ), a measuring current transducer 7 (IPT), a reference voltage source 12 (ION), and a reference frequency generator 13 (GOCH).

 Each of the two voltage-to-frequency converters (VLF1 and VLF2) contains transistor key circuits 15 (KL1), 16 (KL2), 17 (KL3), 18 (KL4), a sign comparator 9 (KO1) for VLF1 and 10 (KO2) for LF2, comparator of cycle 11 (KO3), voltage difference converter and current 25 (PNT), integrating capacitor 24 (C1) and trigger 14 (T1 for LF1 and T2 for LF2).

 The converter of the voltage difference to current 25 (PNT) contains an operational amplifier 8 (OS1 for VLF1) and five resistors: 19 (R1), 20 (R2), 21 (R3), 22 (R4), 23 (R5).

 The out-of-phase outputs of the voltage measuring transducer are connected to the first and second inputs of the first voltage-to-frequency converter, the output of which is connected to the clock input of the second voltage-to-frequency converter, the other two inputs of which are connected to the out-of-phase outputs of the current measuring transducer; the output of the second voltage to frequency converter is connected to the counting input of the reversible counter, the input of the counting direction of which is connected to the output of the equivalence element; the high-order output of the reversible counter serves as the frequency output of the electronic counter.

 The first input of the voltage-to-voltage difference converter is connected through the first and second keys to the first and second inputs of the voltage-to-frequency converter, the second input of the voltage-to-voltage difference converter is connected through the third key to the first output of the voltage reference source, and through the fourth key to a common point; the first input of the sign comparator is connected to the second input of the voltage to frequency converter, the second with a common point, the control inputs of the first and second keys are connected to the output of the sign comparator; an integrating capacitor is connected between the first output of the voltage difference to current converter and a common point; the second output of the voltage difference to current converter is connected to a non-inverting input of the cycle comparator, the inverse input of which is connected to the second output of the reference voltage source, and the output of the cycle comparator is connected to the information input of the trigger; the clock input of the trigger of the first voltage to frequency converter is connected to the output of the reference frequency generator, and the clock input of the trigger of the second voltage to frequency converter forms the clock input of this converter and is connected to the output of the first voltage to frequency converter; control inputs of the third and fourth keys are connected to the trigger output; two inputs of the equivalence element are connected to the outputs of the sign comparators of the first and second voltage to frequency converters, respectively.

 In the voltage-to-voltage difference converter, the first resistor is connected between the first input of the voltage-to-current difference converter and the inverse input of the operational amplifier, the second resistor is connected between the inverse input of the operational amplifier and its output, which forms the second output of the voltage-to-voltage converter, and the third resistor is connected between the second input the voltage difference to current converter and the non-inverse input of the operational amplifier, the fourth resistor is connected between the first and second outputs STUDIO voltage difference into a current, and a fifth resistor connected between the first output of the voltage difference to a current converter and the inverted input of the operational amplifier.

 The output of the counter 4 (PC) is connected to the input of the electromechanical counter 5 (EMC).

Кривые изменений напряжений на конденсаторе 24 (u_C) и на выходе усилителя 8 (U_oy) приведены на фиг. 3. Когда напряжение на выходе усилителя 8 (ОУ1) u_oy Достигает значения U_o2 срабатывает компаратор цикла 11 (КО3) и триггер 14 (Т1), который заставляет замкнуться ключ 17 (КЛ3). Ключ 18 (КЛ4) при этом размыкается. Начинается перезаряд конденсатора 24. От точки 1 до точки 2 (фиг. 3) идет процесс перезаряда при подключенном опорном напряжении U_o1, а от точки 2 до точки 3 при отключенном напряжении U_o1. Для срабатывания триггера 14 (для формирования на его выходе логической единицы) требуется, чтобы логическая единица поступила на его D-вход от компаратора цикла 11 и чтобы поступил импульс u_ти от генератора 13 на тактовый С-вход триггера 14. В связи с этим триггер 14 после достижения напряжением u_oy значения U_o2 может сработать с задержкой во времени в пределах от нуля до τ₀ мкс, где - τ₀ длительность периода генератора опорной частоты 13. Это сопровождается изменениями уровней напряжения на конденсаторе 24 в момент срабатывания триггера 14 (фиг. 3, точки 1 и 3). При этом возникает мгновенная погрешность преобразования, не сопровождающаяся однако накоплением погрешности, так как схема обеспечивает интегральный баланс энергии заряда и разряда конденсатора. Уравнение баланса на основе (2) можно записать в таком виде:
K₁(U_o1-u₁)τ_o= K₁•u₁(T₁-τ_o), (3)
где Т₁ период переключения триггера 14. Из (3) следует выражение для мгновенного значения частоты преобразователя 1 (ПНЧ1):

Методическая погрешность, обусловленная вышеуказанными задержками в срабатывании триггера 14, представляет собой погрешность дискретизации. Ее значение будет пренебрежимо мало, если при номинальном уровне сигнала на входе (u₁) частота f₁ будет удовлетворять условиям:

где f₁ частота контролируемой сети,
f_о частота генератора опорной частоты 13.The energy meter works as follows. Converter 1 (VLF1) converts the current value of the voltage module of the controlled network u ₁ to the frequency f ₁ . The voltage module u ₁ with a negative sign is formed using the keys 15 and 16, controlled by the comparator 9 (KO1). In FIG. 2 shows the voltage curves u, current i and instantaneous power p of the monitored network and modules with a negative sign of the output voltages of the voltage transducer u ₁ and the current transducer u ₂ . Operational amplifier 8 (OU1) operates according to the scheme of the converter of the input voltage difference (U _о1 u ₁ ) to current [3] The voltage across the capacitor 24 (C1) is formed as an integral of the current over time. This construction of the integrator allows to reduce the zero drift of the operational amplifier in comparison with the connection circuit of the capacitor between the output of the operational amplifier and its inverting input. The resistors of the circuit of FIG. 1 must satisfy the condition
R1 (R4 + R5) (R2) (R3). (one)
In this case, the current i _{C of the} charge or discharge of the capacitor 24 (C1) is determined by the expression

The voltage variation curves at the capacitor 24 (u _C ) and at the output of the amplifier 8 (U _oy ) are shown in FIG. 3. When the voltage at the output of amplifier 8 (ОУ1) u _oy Reaches the value U _o2, the comparator of cycle 11 (KO3) and trigger 14 (T1) are activated, which makes key 17 (KL3) close. Key 18 (KL4) thus opens. The recharging of the capacitor 24 begins. From point 1 to point 2 (Fig. 3), the process of recharging occurs when the reference voltage U _{o1 is} connected, and from point 2 to point 3 when the voltage U _{o1 is off} . To trigger 14 (for generating at its output a logic one) requires that a logical unit received at its D-input of comparator 11 and to a cycle pulse u _ti entered from the generator 13 to the clock C input of trigger 14. In this regard, the trigger 14, after the voltage u _oy reaches the value of U _{o2, it} can operate with a time delay ranging from zero to τ ₀ μs, where - τ _{0 is the} duration of the reference frequency generator 13. This is accompanied by changes in the voltage levels on the capacitor 24 at the moment of trigger 14 activation (Fig. . 3 then ki 1 and 3). In this case, an instantaneous conversion error occurs, which is not accompanied, however, by the accumulation of error, since the circuit provides an integrated balance of the charge energy and the discharge of the capacitor. The balance equation based on (2) can be written in the following form:
K ₁ (U _o1 -u ₁ ) τ _o = K ₁ • u ₁ (T ₁ -τ _o ), (3)
where T ₁ trigger switching period 14. From (3) follows the expression for the instantaneous value of the frequency of the Converter 1 (VLF1):

The methodological error due to the above delays in the operation of the trigger 14, is a sampling error. Its value will be negligible if, at the nominal signal level at the input (u ₁ ), the frequency f ₁ will satisfy the conditions:

where f _{1 the} frequency of the controlled network,
f _{about the} frequency of the reference frequency generator 13.

Таким образом при постоянстве значений U_o1 и τ_o частота пропорциональна произведению значений u₁ и u₂, т.е. модулю мгновенной мощности. Импульсы u_T2 (фиг. 1) направляются на счетный вход реверсивного счетчика 4 (РС). Работа счетчика на суммирование или вычитание происходит в соответствии со знаком мгновенной мощности Р (фиг. 2) и определяется логическим значением сигнала У на выходе направления счета счетчика 4. В определении знака мгновенной мощности участвуют компараторы знака 9 (ЕО1) и 10 (КО2) и элемент равнозначности 3 (ЭР3). Если знаки тока i и напряжения u совпадают, то совпадают логические уровни "X1" и "X2". При этом "Y" соответствует логической единице (фиг. 2), а счетчик работает на суммирование. В противном случае счетчик работает на вычитание. Счетчик 4 выполняет также функцию делителя частоты. Если выходное напряжение снимается с выхода старшего разряда двоичного счетчика с разрядностью n, то коэффициент деления К_д определяется выражением
К_д 2ⁿ. (8)
При номинальных уровнях тока и напряжения контролируемой сети и cosΦ = 1 возникает максимум мгновенной частоты (f_2max)_max, которому соответствует максимум средней частоты (f_2cp)_max. Если принять f_o 500 кГц, (f_1max)_max 50 кГц, (f_2max)_max 5 кГц, то, поскольку,
P = 0,5U_mI_mcosΦ-0,5U_mI_mcos(2ω_Ct-Φ), (9) получим (f_2cp)_max 2,5 кГц. При разрядности счетчика n 12 получим K_д 2¹² 4096 и (f_вых)_max (f_2cp)_max/K_д 0,61 Гц. Такое значение частоты приемлемо и с точки зрения точной оценки расхода энергии за получасовой максимум энергосистемы, и с точки зрения достаточной емкости счетчика 5 (ЭМС). Потеря одного импульса за получасовой максимум энергосистемы обусловит погрешность учета расхода энергии
δ = 100/0,61•1800 = 0,91% .
Электромеханический счетчик с семью десятичными разрядами при прохождении максимальной мощности заполнится за
T_сч 10⁷/3600•0,61 4554 часа.The trigger 14 is triggered on the leading edge of the pulses u _ty , which provides a connection time U _o1 to the input OS1, equal to the period τ _o clock pulses regardless of the voltage level u ₁ . The output frequency f _{1 of the} Converter 1 (VLF1) (Fig. 1, Fig. 3, voltage u _T1 ) serves as the clock frequency for the Converter 2 (VLF2), the measuring inputs of which are connected to the outputs of the measuring current transducer 7 (IPT). For transducer 2, a relation similar to (3) is true:
K2 (U _o1 u ₂ ) T ₁ K2 • u ₂ (T ₂ - T ₁ ). (6)
where T ₁ , T _{2 are the} durations of the pulse repetition periods, respectively, at the output of the LF1 and at the output of the LF2. Frequency at the output of the IF2:

Thus, with the constancy of the values of U _o1 and τ _{o, the} frequency is proportional to the product of the values of u ₁ and u ₂ , i.e. instant power module. The pulses u _T2 (Fig. 1) are sent to the counting input of the reverse counter 4 (PC). The operation of the counter for summation or subtraction occurs in accordance with the sign of the instantaneous power P (Fig. 2) and is determined by the logical value of the signal Y at the output of the counting direction of the counter 4. The sign comparators 9 (ЕО1) and 10 (КО2) and element of equivalence 3 (ER3). If the signs of the current i and voltage u coincide, then the logical levels "X1" and "X2" coincide. In this case, "Y" corresponds to a logical unit (Fig. 2), and the counter works on summation. Otherwise, the counter works for subtraction. Counter 4 also performs the function of a frequency divider. If the output voltage is removed from the output of the highest bit of the binary counter with a capacity of n, then the division coefficient K _d is determined by the expression
K _d 2 ⁿ . (eight)
At rated current and voltage levels of the controlled network and cosΦ = 1, a maximum of the instantaneous frequency (f _2max ) _{max occurs} , which corresponds to a maximum of the average frequency (f _2cp ) _max . If we take f _o 500 kHz, (f _1max ) _max 50 kHz, (f _2max ) _max 5 kHz, then, since
P = 0.5U _m I _m cosΦ-0.5U _m I _m cos (2ω _C t-Φ), (9) we obtain (f _2cp ) _max 2.5 kHz. When the bit length of the counter n 12 we get K _d 2 ¹² 4096 and (f _o ) _max (f _2cp ) _max / K _d 0.61 Hz. Such a frequency value is acceptable both from the point of view of accurate estimation of energy consumption for a half-hour maximum of the power system, and from the point of view of sufficient counter capacity 5 (EMC). The loss of one pulse per half-hour maximum of the power system will cause an error in accounting for energy consumption
δ = 100 / 0.61 • 1800 = 0.91%.
An electromechanical meter with seven decimal places when passing maximum power will be filled in
T _MF 10 ^7/3600 • 0,61 4554 hours.

According to GOST 6570 75, the counter's counter mechanism should not be overflowed faster than in 1500 hours. If the number of EMC discharges is insufficient, then it is necessary to increase the overall division coefficient K _d and make separate outputs from the counter-divider to the electronic accounting system and to the EMC.

Sources of information
1. Copyright certificate of the USSR N 1397846, cl. G 01 R 21/00, 1988, BI N 19.

 2. USSR author's certificate N 1411678, cl. G 01 R 21/00, 1988, BI N 27.

 3. Gutikov V.S. Integrated electronics in measuring devices. - L. Energoatomizdat, 1988, -304 p.

Claims (1)

 An electronic active energy meter comprising voltage and current transducers, two voltage-to-frequency converters, a reference frequency generator and a pulse counter, characterized in that an equivalence element is introduced into it, the antiphase outputs of the voltage measuring transducer being connected to the first and second inputs of the first voltage converter to a frequency whose output is connected to the clock input of the second voltage to frequency converter, the other two inputs of which are connected to to the phase outputs of the measuring current transducer, the output of the second voltage to frequency converter is connected to the counting input of the reversible counter, the input of the counting direction of which is connected to the output of the equivalence element, the high-order output of the reversing counter serves as the frequency output of the electronic counter, each voltage to frequency converter contains four keys, a comparator sign and a comparator of the cycle, a voltage difference to current converter integrating a capacitor and a trigger, the first input being the voltage difference generator into the current is connected through the first and second switches respectively to the first and second inputs of the voltage to frequency converter, the second input of the voltage difference to current converter is connected through the third switch to the first output of the voltage reference source, and through the fourth switch to a common point, the first input the sign comparator is connected to the second input of the voltage to frequency converter, the second with a common point, the control inputs of the first and second keys are connected to the output of the sign comparator, integrating the capacitor is connected between the first output of the voltage-to-voltage difference converter and the common point, the second output of the voltage-to-voltage converter is connected to the non-inverting input of the cycle comparator, the inverse of which is connected to the second output of the reference voltage source, and the output of the cycle comparator is connected to the information input of the trigger the trigger input of the first voltage converter to the frequency is connected to the output of the reference frequency generator, and the clock input of the trigger of the second voltage converter It forms the clock input of this converter to the frequency and is connected to the output of the first voltage to frequency converter, the control inputs of the third and fourth keys are connected to the trigger output, the two inputs of the equivalence element are connected to the outputs of the sign comparator of the first and second voltage to frequency converters, respectively, each difference converter voltage in current contains an operational amplifier and five resistors, and the first resistor is connected between the first input of the voltage difference Converter I into the current and the inverse input of the operational amplifier, the second resistor is connected between the inverse input of the operational amplifier and its output, forming the second output of the voltage difference to current converter, the third resistor is connected between the second input of the voltage difference to current converter and the non-inverse input of the operational amplifier, the fourth resistor is connected between the first and second outputs of the voltage difference to current converter, and the fifth resistor is connected between the first output of the voltage to voltage difference converter and non-inverse input of an operational amplifier.

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