RU2059287C1 - Device for monitoring program executing by control computer - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has counter 1, memory unit 2, comparison circuit 3, reset flip-flop 4, interrupt flip-flop 5, error flip-flop 6, AND gate 7, NOR gate 9, OR gate 8 and 10. EFFECT: increased speed of monitoring because it is performed directly after instruction reading; increased functional capabilities because device continues operations after interrupts in computer to be controlled, simplified hardware design. 2 dwg

Description

 The invention relates to computer technology and can be used to build reliable control computers (UVM), insensitive to program failures.

 The purpose of the invention is to increase the efficiency of control by exercising control directly when reading commands, expanding the functionality due to the ability to work in the presence of interruptions in a controlled UVM, as well as reducing hardware costs.

 Figure 1 shows the structural diagram of the device; figure 2 is an example program.

 The device (Fig. 1) contains a source 1, a memory unit 2, a comparison circuit 3, cleaning triggers 4, interrupts 5, errors 6, AND element 7, the first 8 OR element, the OR-NOT 9 element, the second 10 OR element, UVM lines : address / data bus 11, access line to program ROM 12, clear 13, access to interrupt vectors 14, read 15, device failure signal 16 output.

 Figure 2 presents an example of part of the UVM program, as well as the firmware of the main field (associated with the group of information outputs) of the second page of the memory unit 2.

The following notations are accepted: A _i addresses of the commands of conditional and unconditional transition; l (A _i ) the address to which the transition is possible when executing the commands of conditional and unconditional transition; B the length of the instruction pipeline; X an arbitrary address that is not part of the ROM program area.

 The device is designed to control the progress of the UVM program, built on the basis of modern processors having an instruction pipeline (for example, microprocessors 1810 BM86, INTEL 18086).

1• QSO=

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активный уровень которого ("1") появляется при QS1 0; QSO 1 идентифицирует переход к началу нового линейного участка программы и подается на соответствующий вход устройства.In these processors, an advanced sample of instructions is used and a queue of instructions is formed. When control is transferred to another place in the program (at the beginning of a new linear section of the program), the instruction pipeline is cleared and after that it begins to fill up with commands of the new linear section of the program. Conveyor cleaning signal (for microprocessor 1810 VM86, for example, it is signal y

1 • QSO =

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whose active level ("1") appears at QS1 0; QSO 1 identifies the transition to the beginning of a new linear section of the program and is fed to the corresponding input of the device.

 The active ("0") signal level on the access lines to the ROM of program 12 and to the interrupt vectors 14 is generated in the UVM (using the address selector included in it) when the UVM processor addresses the address zone, according to which the program executed by the UVM is stored, and to the area where the interrupt vectors are stored, remaining until the end of the access cycle at this address.

 A failure signal ("0") on line 16 may be provided to the IWM as an interrupt request signal.

 With a logical “0” signal at its recording permission input, counter 1 operates in parallel recording mode, and with “1” counts. Recording and counting is performed on the front 1/0 at the counter clock input.

 Information is recorded in triggers 4 and 6 along the front 0/1 at their sync inputs.

 If the codes of the comparison circuit 3 are equal and the logical signal “1” appears at its output, if the inequality is logical, the signal is “0”.

 Memory block 2 consists of two pages. With a logical "1", the first page is selected at the page selection input, and with a logical "0", the second page is selected.

The first page is identical to ROM of programs controlled by UVM. The second page is stitched so that the address at its entrance is assigned to the output address of the start of a new linear section of the program controlled by the UVM (figure 2), which can occur at this point in the program. The number of instructions following a conditional or unconditional jump instruction and read into the conveyor of the UVM processor commands at the time of its execution is non-deterministic (due to the non-deterministic time of interruptions that cause the pipeline to be cleared in the UVM), therefore, on the second page of memory block 2, for all addresses A _i ; A _i + B the notation l (A _i ) is written. At the addresses of the UVM program, in which, in the absence of interruptions, it is impossible to switch to other linear sections of the program, arbitrary information X is written that does not fall into the address area of the ROM of the UVM program.

 On the second page of memory block 2, one bit of data is associated with its separate output. It has a value equal to "0" if the transition address at a given point in the UVM program cannot be determined in advance ("1" if it can) otherwise).

 The requirement for the UVM program is that the interval between the commands of the conditional and unconditional transition exceed the length of the conveyor commands of the UVM processor. Violation of this requirement is extremely unlikely due to the short length of the conveyor (1-2 teams) and easily removable by inserting the OP command (no operation).

 The control of the operation of the UVM is carried out by comparing the real and predicted values of the command codes and addresses of the transition to a new linear section of the program. This ensures that the correct reading of the commands during the execution of the linear section of the program and the correct transitions to the new linear section of the program.

 The proposed device operates as follows.

 When the power is turned on and when switching to a new linear section of the program in the processor with the command pipeline, it is cleaned, accompanied by the appearance of an active level ("1") of the signal on the cleaning line 13, this leads to the reset of the cleaning trigger 4 and the transfer of counter 1 to recording mode.

 The UVM processor, referring to the ROM of the program for the 1st command of the linear section of the program, gives its address. The call is accompanied by the appearance of an active ("0") signal level on the access line to the program ROM 12, by which the address is recorded in counter 1 and the cleaning trigger is set 4. Counter 1 is switched to counting mode, the first page is selected in memory block 2. When reading subsequent commands by the signal to access the ROM of the programs ("0"), counter 1 is incremented. If there are no failures, the value of counter 1 coincides with the value of the counter of the CPU processor commands. The expected command is read from memory block 2. Reading the command in the computer is accompanied by active signal levels ("0") on the lines of accessing the ROM of program 12 and reading 15, which leads to the appearance of a logical "0" signal at the output of OR 8 and the sync input of error trigger 6. Comparison of the expected and actually read command occurs in the comparison circuit 3. When the edge 6 coincides at the sync input of the trigger of error 6 at the output of the comparison circuit 3 and the information input of the trigger of error 6 at the output of the comparison circuit 3 and the information input of trigger 6 is logical “1”, trigger 6 remains set In the idle state, a fault signal ("0") is not issued to line 16. With you, at the moment of front 0/1, on trigger sync input 6, at output of comparison circuit 3 and trigger 6 information input “0”, trigger 6 is reset, a fault signal is issued to the UVM.

 In response to it, the UVM interrupts its work, switching to a failure interrupt processing program, which is accompanied by reading the interrupt vector and the appearance of an active signal level on line 14, which resets the interrupt trigger 5 and sets the error trigger 6, removing the error signal ("0") on line 16.

 When switching to a new linear section, the transition address is controlled. The transition to a new linear section is accompanied by the appearance of an active level ("1") on the cleaning line 13, which leads to the reset of the cleaning trigger 4, the second page of the memory block 2 is selected. The address to which it is possible to jump to this point in the program is read. The comparison is based on the appearance of an active signal level on the line "Access ROM programs" 12, the appearance of which indicates the issuance of the address of the first command of a new linear section. In this case, the cleaning trigger 4 is set, at its output, at the output of the And 7 element, the sync input of the error trigger appears front 0/1, which likewise compares the expected and real transition addresses.

 In some cases, the transition address cannot be determined in advance. These include the transition to the interrupt processing program when the transition address depends on the interrupt vector being read, return from the interrupt when the transition address is determined by the point at which the main computer program was interrupted, indirect transition addressing when the transition address depends on the changing contents of a certain cell RAM UVM.

 At these moments, control of the UVM device is temporarily interrupted. It happens as follows.

 When switching to the interrupt processing program according to the active signal level on the line “Access to interrupt vectors” 14, the interrupt trigger 5 is reset, and due to the active signal level (“0”), the passive state of the signal on the fault line 16 is maintained at the input of the error trigger setting. By the active level ("0") of the signal on the line "Access to program ROM" 12, which appears when the first command of a new linear section is read, trigger 5 is reset, and the operation of the UVM is resumed.

 At the address of the last command of the interrupt processing program, as well as the commands where the transition address cannot be determined in advance, the lock bit has an active value ("0") in the second page of the memory block. When switching to a new linear section by the active level of the cleaning signal on line 13, the cleaning trigger 4 is reset, the second page of memory block 2 is selected. At the same time, with the active value of the lock bit ("0"), the output of the OR-NOT 9 element and the OR 10 element appears logical signal "1", which supports the passive state of the fault signal on line 16. According to the active level ("0") of the signal on the line "Access to program ROM" 12, which appears when the first command of a new linear section is read, trigger 4 is reset, operation control UVM renew Xia.

Claims (1)

 DEVICE FOR MONITORING THE PROGRAM OF THE MANAGING COMPUTER MACHINE, containing a memory block, a comparison circuit, interrupt, cleanup and error triggers, an AND element, an OR element, the first group of inputs of the comparison circuit being connected to the group of inputs of the device data address, characterized in that, for the purpose of increasing control efficiency, expanding functionality due to the ability to work in the presence of interruptions in a controlled computer and reducing hardware costs, it contains a counter, a second OR element and an OR element moreover, the group of inputs / addresses of the device is connected to the information group of inputs of the counter, the group of outputs of which is connected to the group of address inputs of the memory block, the output and group of information outputs of which are connected respectively to the first input of the OR element and the second group of inputs of the comparison circuit, the output of which is connected with the first input of the second OR element, the second input of which is connected to the output of the OR element, the output of the second OR element is connected to the information input of the error trigger, the output of which is you device failure, the sync input of the error trigger is connected to the output of the AND element, the inverse input of the installation of the error trigger is connected to the output of the interrupt trigger, the inverse reset input of which is the input of accessing the device interrupt vectors, the first input of the first OR element, the inverse input of the cleaning trigger setting, the inverse input the settings of the interrupt trigger and the counter clock input are connected to the access address of the device program ROM, the cleaning trigger clock is the device cleaning input, the output of the cleaning trigger ki is connected to the input of the choice of the counter mode, with the input of the page selection of the memory block, with the second input of the OR element and the first input of the AND element, the second input of which is connected to the output of the first OR element, the second input of which is the read input of the device, the information input of the cleaning trigger is connected to the bus of the zero potential of the device.

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