RU2058596C1 - Device for remote control of mechanisms - Google Patents

Abstract

FIELD: remote control devices. SUBSTANCE: device has transmitting and receiving parts, which serve as encoder and decoder. Encoder contains unit of gates, encoder, crystal oscillator, buffer register, selective unit, receiver, transmitter, multiplexer. decoder contains receiver, delay gate, flip-flops, counters, decoders, comparison gate. EFFECT: increased reliability, increased information capacity by using single communication channel, parity check of received information and information transmission to selected user taking into account busy signal in communication line. 5 cl, 5 dwg

Description

 The invention relates to telemechanics and can be used for remote control of various technological processes, hoisting-and-transport mechanisms (cranes), transport mechanisms, dampers, etc.

A device for remote telecontrol, which includes a portable control panel (with a transmitter and a control device) and a receiving device comprising a receiver, a differential filter unit, a proportional instruction decoding unit and discrete instruction decoding unit [1]
In such a device, for telecontrolling a given number of objects, the same number of frequency channels is required, moreover, it is complicated, requires fine tuning of filters, and, as a result, has low reliability.

A device for telecontrol and telecontrol is known, the principle of which is based on the fact that the first signal on the air of a signaling system of a line item is received by all other line items and locks the radio transmitters of these line items for the duration of the signal transmission of the signaling system, the first line item starting transmission [2 ]
A disadvantage of the known device is the constant occupancy of the communication channel by any one linear point, while the updating of telemechanical information is relatively rare. In addition, when working with one channel and having many users, a situation is possible when several line points simultaneously try to capture the channel. In this case, the transmitted information is distorted.

A device for remote control, in which the number of frequency channels is less than the number of controlled objects. This device contains control buttons on the transmitting side, an encoder, a register, an OR element, frequency generators, a counter, a shift register on the receiving side, a lock trigger, a pulse generator, a counter, an I element, a register and an instruction decoder [3]
In this device, to control a given number of objects, again, a large number of frequency channels is required equal to log ₂ (n + 1), where n is the number of control objects. In addition, with an increase in the number of controlled objects, along with an increase in the number of occupied channels, the device becomes more complicated (the number of frequency generators is equal to the number of communication channels used), and it is necessary to fine-tune the repetition periods of the generator pulses relative to each other.

 The task was to create a device for remote control of many objects using only one communication channel, as well as ensuring high reliability of remote control.

 According to the invention, in a device for remote control of mechanisms, comprising on the transmitting side a key block, an encoder, a buffer register, an OR element, a first binary counter, a crystal oscillator, on a receiving side a trigger, a crystal oscillator, a first binary counter, an And element, a first shift register, buffer register, command decoder, selector element, receiver, I element, multiplexer, transmitter, receiver, receiver element, delay element, trigger, multiplexer, comparison element introduced on the transmitting side Nia, a decoder, a binary counter.

 To increase the reliability of telecontrol, the transmitted information is supplemented by a parity check bit, for which a control discharge driver, an control trigger and an element I are introduced on the receiving side.

 To prevent distortion of information when trying to capture a channel by several users, a random number generator, a second binary counter, and a decoder are additionally introduced on the transmitting side.

 To increase the reliability and speed of completion of executable commands, an additional trigger for the end of transmission has been introduced on the transmitting side.

 To control one object, many users additionally introduced on the receiving side a switch, a second shift register, and a busy trigger.

 In FIG. 1 shows a functional diagram of a device; in FIG. 2 shows a fragment of a device supplemented by a control discharge former; in FIG. 3 is a fragment of a device supplemented on the transmitting side with elements of user distribution in time when trying to simultaneously capture the channel; in FIG. 4 fragment of a device supplemented on the transmitting side with a trigger for ending transmission; in FIG. 5 is a fragment of a device supplemented on the receiving side by elements for determining a user number.

 The device consists of two half-sets, the receiving side (decoder) located on the managed object, and the transmitting (encoder) located at the operator. The encoder contains a key block 1, an encoder 2, a buffer register 3, an OR element 4, a binary counter 5, a crystal oscillator 6, a selective element 7, a receiver 8, an And 9 element, a multiplexer 10, an And 11 element, a transmitter 12. The decoder contains a receiver 13 , delay element 14, trigger 15, trigger 16, binary counter 17, crystal oscillator 18, multiplexer 19, comparison element 20, decoder 21, element 22, shift register 23, buffer register 24, instruction decoder 25, binary counter 26.

 According to one embodiment of the device, to increase the reliability of telecontrol, the transmitted information is supplemented by a parity check bit, for which a control bit shaper 27 is introduced on the transmitting side, with constanta and buffer register 3 outputs respectively connected to its first and second inputs, and the output connected to the third input of the multiplexer 10, on the receiving side of the trigger 28, the first input of which is connected to the output of the receiver 13, the second input is connected to the first output of the decoder 21, and t the third input with the output of the trigger 16, and the element And 29, the first input of which is connected to the output of the trigger 16, the second input with the second output of the decoder 21, and the output with the second input of the buffer register 24 and the first input of the binary counter 26.

 According to another embodiment of the device for preventing information distortion when trying to capture a channel by several users, it further comprises a decoder 30, a second binary counter 31 and a random number generator 32 on the transmitting side, the output of which is connected to the third input of the second binary counter 31. The first input of the counter 31 is connected with the output of the crystal oscillator 6, the second input with the output of the OR element 4, the fourth input with the output of the element And 9, and the outputs are connected to the inputs of the decoder 30, the output of which is connected ene to a fifth input of counter 31 and the fifth input of the counter 5.

 According to a fourth embodiment of the device, in order to increase the reliability and speed of completion of executable instructions, it further comprises a transmission end trigger 33 on the transmitting side, the first input of which is connected to the output of the OR element 4, the second input with the fifth output of the selective element 7, and the output is connected to the first binary input counter 5.

 According to a fifth embodiment of the device for controlling one object by many users, it additionally comprises a busy trigger 34, a switch 35 and a second shift register 36 on the receiving side, the outputs of which are connected to the second inputs of the switch 35, the first inputs of which are connected to the output of the receiver 13, and the outputs are connected to the inputs of the multiplexer 19. The first and second inputs of the busy trigger 34 are connected to the first and second outputs of the decoder 25 commands, the third input is connected to the output of the second binary counter 26, and the output under is connected to the control input of the switch 35 and the first input of the second shift register 36, the second and third inputs of which are connected to the first output of the decoder 21 and the high-order output of the first shift register 23, respectively.

 The device operates as follows.

 The operator, by pressing a command button, sends a digital word with a bit capacity of C = M + N + P + K to the communication channel, where M is the address of the managed object (the most significant bit of the address is logical “1” for decoder synchronization); N user number; P is the command number and K is the control bit, and the communication channel is occupied for a time t = Δ t · C + Δ, where C is the bit depth of the sent word; Δt transmission time of one bit; Δ time of establishment of transients in the communication channel. After issuing the entire package, the encoder releases the channel for a time T, after which the command is regenerated. The decoder, having selected the signal of its carrier frequency, determines sequentially bit by bit the address M, and if this address and the address of the object coincide, then further operation of the device is allowed, otherwise the sending is rejected. After the address is received, the user number N, the P command, and the parity check bit K are received. After successfully checking the received information for parity, the user number N is stored in the register and the device takes care of this user until the command "transfer control" arrives, and all other users who have the same object address is rejected for this time. Upon receipt of subsequent sendings, the field N of the user number is compared with the state of the corresponding register, and if the comparison is unsuccessful, the command is rejected.

 Consider the operation of the encoder and decoder separately.

 The encoder works as follows.

 When the power is turned on, an initial reset signal is generated, which returns the device to its initial state, resetting buffer register 3. Element OR 4, having determined the zero state of all bits of register 3, resets counter 5, and at the first output of election element 7 there is a logical signal “1” , which allows recording information in the buffer register 3 from the encoder 2 (only at the zero position of the counter 5), at the other outputs the logical "0". If none of the buttons is started, then zeros are recorded in buffer register 3 (the initial state of encoder 2), the device is in a standby state and nothing is being broadcast.

 When you press a key, key block 1 (or several at once), the encoder 2 converts the Y inputs from the command keys 1 into a P-bit binary code, which is entered in register 3. At the same time, the OR 4 element is activated and enables (removes the reset signal) the operation of the counter 5, to the sync input of which pulses from the crystal oscillator 6 are continuously supplied. Since the And 9 element is closed by the second output of the electoral element 7, the operation of the counter 5 is also allowed at the third (control) input.

 The logic of the device is such that the P-bit binary code recorded in the buffer register 3, supplemented by a constant, must be converted into a serial binary code and bit by bit broadcast for reception by the actuator. Since a channel is used that is common to other users, then after issuing its code message for a time t, the device should disconnect from the channel for a time T in order to be captured by other users (time division). After time t + T, the command changes (if another button is pressed) or the old one is regenerated and the cycle repeats.

 After the first cycle, when counter 5 changes its state by one, element 7 prohibits writing information to register 3, which goes into storage mode until the end of the cycle, and allows the signal to pass from receiver 8 to counter 5 by the second output. Receiver 8 operating on the same frequency with the transmitter 12, continuously receives signals from the ether, and if it selects a signal with a given carrier frequency, then through the And 9 element prohibits the further counting of the counter 5. After the ether is released, the receiver 8 closes the And 9 element and enables the further counting of the counter 5.

 In the next step, counter 5 changes its state by one; element 7 closes the And 9 element until the end of the cycle (prohibits stopping the counter 5 until the end of the cycle) and sets the switching signal for the carrier frequency of transmitter 12 with its third output, while the modulator of the transmitter 12 receives a modulation enable signal with Element And 11 does not arrive. Since the counting conditions for the counter 5 are saved, it calculates several clock cycles to the value at which the element 7 supplies the enable signal to the And 11 element. From this moment on, the counter 5, controlling the multiplexer 10, connects the transmitter 12 to the modulator (and accordingly radiates to the air) bitwise information: object address (constant) and register bits 3.

 The constant is an M-bit binary, the high bit of which contains a logical "1". The first bit is the clock for the receiver, and the rest determine the number of the object. After issuing the last bit of the command, element 7 closes the AND element 11 and removes the carrier frequency enable signal at transmitter 12 until the end of the cycle. At the end of the cycle, the counter 5 is reset to the initial state by a signal from the fifth output of the element 7 (performs a reset of the counter 5). If at this point in time any key 1 is pressed (or several), then the cycle repeats, otherwise zeros are written to register 3 and the device goes into standby mode.

 The decoder works as follows.

 When the power is turned on, an initial reset signal is generated, which returns the device to its initial state, setting trigger 15 to zero and resetting register 24. Trigger 15 resets trigger 16, which, in turn, resets counter 17, and the device goes into standby mode.

 The information emitted by the transmitter 12 of the encoder is received by the receiver 13 of the decoder. The receiver 13 at the first output selects bits of information (input code), and at the second output, a carrier frequency signal. The device is in a standby state until the receiver 13 selects a carrier frequency signal to which it is tuned. This signal through the leading edge delay element 14 includes a trigger 15. Next, the device enters the standby state of the first pulse that arrives at the trigger 16 from the receiver 13. The trigger 16 is turned on at the leading edge of the first pulse and enables the counter 17 to be continuously fed to the clock input pulses from the quartz oscillator 18. In this case, the counter 17, controlling the multiplexer 19, connects to the element 20 of the comparison the first bit of the constant, which is equal to the logical "1". The input code from the receiver 13 is received at the second input of the comparison element 20. The decoder 21, controlled by the counter 17, generates a short strobe at the first output in each clock cycle in the middle section of the received bit. If the signals of the multiplexer 19 and the receiver 13 are unequal, the trigger 15 is reset by the strobe from the decoder 21 through the And element 22, and then the trigger 16 and the counter 17 are reset, and the device returns to its initial state (the “foreign message” is defined). With the equality of the compared information, the element 20 closes the element And 22 and reset the trigger 15 in this cycle does not occur.

 In subsequent clock cycles, the counter 17, controlling the multiplexer 19, connects to the element 20 and compares bit by bit the remaining bits of the M-bit constant. After counting M clocks (if the constant and received codes are equal), the device proceeds to receive a P-bit command, while counter 17, controlling the multiplexer 19, connects input code from receiver 13 to element 20, as a result of which And 22 Closed and reset trigger 15 does not occur. In register 23 of the shift from the receiver 13, information is recorded in each cycle by the strobe of the decoder 21 and after counting M + P cycles in the register 23 are the last P bits of the input code (the first M bits are not needed). In the last M + Pth cycle, the decoder 21, after issuing the gate with the second output, generates a single pulse, which resets the counter 26 and writes P bits (command) from register 23 to the buffer register 24. The outputs of the decoder 25 of the commands controlled by the register 24 are sent to the executive mechanism.

 The device is reset, resetting the trigger 15, in the next clock signal from the element And 22, since the inverse signal of the receiver 13 is received from the multiplexer 19 from the multiplexer 19, and it will determine the incomparison. At the end of the transmission, the buffer register 24 is reset by the signal of the counter 26, to the sync input of which pulses from the crystal oscillator 18 are continuously received. The time of appearance of this signal from the moment the command was entered into the buffer register 24 2 · (T + t), twice the regeneration period, provides stable operation of the device even in conditions of strong channel interference.

 To increase the reliability of remote control, the transmitted information is supplemented by a parity check bit, for which a control bit shaper 27 is introduced on the transmitting side, the constant and outputs of the buffer register 3 are connected to the first and second inputs of it, respectively. The output of the driver 27 is connected to the multiplexer 10, and the control bit is issued to the channel last after the M-bit constant and P-bit command. So, a C = M + R + K-bit code is emitted into the air, where K is the control bit.

 On the receiving side, to determine the parity of the received information, trigger 28 is entered (in the initial state it was reset by trigger 16), which counts, according to mod 2, the number of “units” coming from receiver 13, and after C clock cycles must be turned off, otherwise a parity failure will be detected. In the last M + P + 1) -th clock, the decoder 21, after issuing the gate with the second output, generates a single pulse, which arrives at the And 29 element. If the trigger 28 is not turned on, the counter 26 is reset and the shift register 23 is written from P high-order bits (must have P + 1 bits) in the buffer register 24, and on the P + 1 clock cycle the element And 22 is closed (the second P + 1 information inputs of the multiplexer 19 receives a signal from the receiver 13).

 When working with one channel and the presence of many users, it is possible that several users simultaneously try to capture the channel. To automatically distribute the requests of these users in time on the transmitting side, a decoder 30, a second binary counter 31, and a random number generator 32 are introduced.

 After pressing any command key 1, counter 5 changes its state by one, element 7 prohibits the recording of information in register 3 and by the second output allows the signal to pass from receiver 8 to counters 5 and 31 (in the initial state it was reset). If the receiver 8 selects a signal with a given carrier frequency, then through the And 9 element it prohibits the further counting of the counter 5, and also writes a random value from the random number generator 32 to the counter 31. The counting of the counter 5 is prohibited until two conditions are met: the ether is free, t. e. the receiver 8 ceases to emit signals, and the counter 31 should have a zero value. After the ether is released, the receiver 8 closes the And 9 element, which in turn prohibits the recording of information in the counter 31 from the random number generator 32. If a non-zero number is entered in the counter 31, then the decoder 30 (determines the zero state of the counter 31) prohibits the counter 5 and enables the counter 31, to the sync input of which pulses from the crystal oscillator 6 are continuously supplied. Counter 31 counts to zero, after of which the decoder 30 prohibits its further counting and removes the counting ban of the counter 5. If at this point in time the receiver 8 does not select a signal with a given carrier frequency, further operation of the device is possible (otherwise the process repeats, that is, it will aesena random value in the counter 31, the decoder 30 prohibits the counter counter 5, etc.).

 To increase the reliability and speed of completion of commands on the transmitting side, a transmission end trigger 33 is introduced, which is turned on by the signal from the OR element 4 and controls the reset of the counter 5. The trigger 33 is turned off by the signal from the fifth output of the element 7 only with a logical "0" at the output of the OR element 4. If at the end of the transmission cycle none of the control keys of unit 1 is pressed, then logical “0” is written into register 3, the OR 4 element removes the logical “1” signal from the input of trigger 33 and after the next operation cycle of the device (to the channel with ides stop command sent to all zeros), the trigger 33 is off the output signal from the fifth selective element 7 and the apparatus enters the standby mode.

 To control one object by many users, a busy trigger 34, a switch 35, and a second shift register 36 are introduced at the receiving side. In this case, the constant connected to the first information inputs of the multiplexer 10 on the transmitting side must have a bit M + N, where N is the binary code of the user number, and C = M + N + P-bit code is broadcast.

 On the receiving side, after counting M clocks (if the constant and receiving codes are equal), the device proceeds to receive the N-bit user number. Since the device is not occupied, the trigger 34, controlling the switch 35, connects the input code from the receiver 13 to the inputs of the multiplexer 19. The element And 22 is closed for this number of clock cycles and the trigger 15 does not reset.

 In the following clock cycles, the device proceeds to receive the P-bit command. In the shift register 36 from the upper bit of register 23, information is recorded in each clock by the strobe of the decoder 21 and after counting C = M + N + P clocks, N bits of the user number are in the register 36, and the instruction from the shift register 23 is written in the buffer register 24. The decoder 25 commands controlled by the register 24, the signal from its first output (generated for all commands except the commands "transfer control" and "stop" the zero state of the register 24) includes a trigger 34 busy, which, controlling the switch 35, connects to the inputs of the multiplexer 19 the outputs of the register 36 and prohibits further entry into it from the register 23.

 In the following receive cycles, the device determines not only its address, but also the user number, and for any non-comparison, the package is rejected. A user who has taken over the device and has completed all of his operations sends a “transfer control” command to the channel, which is received by the device. The command decoder 25, having determined this command, turns off the trigger 34 with a signal from the second output, which, acting on the switch 35, connects the output of the receiver 13 to the inputs of the multiplexer 19 and removes the write ban from register 36. Thus, the device goes to its original state and is ready to accept the command from any user with their address. Trigger 34 can also be turned off by a signal from counter 26 (if the user has not sent a single command for a certain time). The time of appearance of this signal T1 (for example, several minutes) from the moment the last command is entered in the buffer register 24.

 So, in general, the encoder sends a message to the channel with a bit capacity of C = M + N + P + K, which, when the address part is successfully compared with the parity of the received information, takes the managed object for the time necessary for the user to perform all operations.

Claims (5)

 1. A DEVICE FOR REMOTE CONTROL OF MECHANISMS, containing on the transmitting side a series of keys, an encoder, a buffer register, an OR element and a binary counter, a crystal oscillator, the output of which is connected to the second input of the binary counter, and a crystal oscillator, the output of which is via the first the binary counter is connected to a decoder, a shift register, a buffer register, an AND element, and triggers, characterized in that the And elements, a receiver, a transmitter, a selector are inserted into it on the transmitting side the th element and the multiplexer, the output of the receiver is connected to the first input of the first element And, the output of which is connected to the third input of the binary counter, the output of which is connected to the control input of the multiplexer, the information inputs of which are connected to the output of the buffer register, the output is connected to the first input of the second element And, the output of which is connected to the first input of the transmitter, the first to fifth outputs of the selective element are connected respectively to the input of the buffer register, to the second inputs of the first element And, the transmitter, W And the fourth input of the binary counter, the first input of the multiplexer is the input of the "Const" device, on the receiving side is a receiver, a command decoder, a multiplexer, a comparison element, a second binary counter, a delay element, the output of the receiver is connected to the information inputs of the multiplexer and the first inputs of the register shift, the comparison element and the first trigger and through the delay element with the first input of the second trigger, the output of which is connected to the second input of the first trigger, the output of which is connected to the second input first binary counter, the output of the first binary counter is connected to the control input of the multiplexer, the output of the multiplexer is connected to the second input of the comparison element, the output of which is connected to the first input of the element And, the first output of the decoder is connected to the second inputs of the shift register and the element And, the output of the element And is connected to the second input of the second trigger, the output of the crystal oscillator is connected to the first input of the second binary counter, the output of which is connected to the first input of the buffer register, to the second input of which chen shift register output, the output coupled to the instruction decoder, the output of which is the control output device, the second output of the decoder is connected to a second input of the second binary counter and a third input buffer register.  2. The device according to claim 1, characterized in that the control discharge generator is introduced on the transmitting side, the inputs of the first group of which are inputs of the “Const” device, the inputs of the second group are connected to the outputs of the buffer register, the output is connected to the second input of the multiplexer, on the receiving side the third trigger and the second element And, the first input of the third trigger is connected to the first output of the receiver, the second and third inputs, respectively, with the first output of the decoder and the output of the first trigger, the output is connected to the first input of the second element And connected between the second output of the decoder, a second input of the second binary counter and a third input of the buffer register, respectively, its second input and output.  3. The device according to claim 2, characterized in that a random number generator, a second binary counter and a decoder, a quartz generator output, an OR element output, a random number generator output, a first AND element and a second decoder output are connected respectively to the inputs of the second binary counter, the output of which through the second decoder is connected to the fifth input of the first binary counter.  4. The device according to claim 1, characterized in that a trigger is inserted into it on the transmitting side, connected between the output of the OR element and the first input of the first binary counter by its first input and output, the second trigger input is combined with the fourth input of the first binary counter.  5. The device according to claim 1, characterized in that a trigger for controlling occupancy, a switch and a second shift register are inserted into the device on the receiving side, the first and second inputs of the employment control trigger are connected to the second and third outputs of the command decoder, the third input is connected to the output the second binary counter, the output is connected to the control input of the switch and the first input of the second shift register, the inputs of the first group of the switch are connected to the output of the receiver, the inputs of the second group with the outputs of the second shift register, the outputs are connected With the second group of multiplexer inputs, the second and third inputs of the second shift register are connected respectively to the first output of the decoder and the high-order output of the first shift register.

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