RU2046453C1 - Process of manufacture of field-effect transistor with submicronic shottky-barrier gate - Google Patents

Abstract

FIELD: microelectronics. SUBSTANCE: process of manufacture of field-effect transistor with submicronic Shottky-barrier gate involves formation of thin doped and thick heavy-doped layers on semi-insulating substrate, formation of electrodes of source ands drain, application of dielectric strip between electrodes which width equals value of resolution of used technological method and which center is matched with edge of source electrode, formation of groove in heavy-doped layer which edge is aligned with edge of dielectric strip facing drain and formation of gate located in groove and partially on dielectric strip. EFFECT: reduced noise and increased gain factors. 5 dwg

Description

 The invention relates to methods for manufacturing semiconductor devices, namely field-effect transistors with a submicron Schottky gate (PTSH), and can be used in the manufacture of both discrete PTSh and integrated circuits.

Since PTSh are designed to amplify a high-frequency signal, the main improvements in their manufacturing technology are aimed at increasing the gain (K _ur ) and reduce the noise figure (K _w ). To do this, minimize the shutter length and the distance of the source of the shutter.

The maximum approximation of the source to the gate is provided in the manufacture of PTS by self-aligning the gate with the source and drain electrodes [1]
The minimum shutter length in this method is limited by the resolution of the technology of its formation. Moreover, the resolution of the technology of structure formation is understood as the sum of the resolving capabilities of each of the operations involved in the formation of this structure.

 There is also a known method of manufacturing PTSh with the so-called "division" of the shutter, according to which part of the shutter (of the order of half the length, taking into account the resolution of the structure formation technology) is placed on a thin doped (active) layer, and part on a thicker doped layer, on which the source electrode is applied [2] The working length of the shutter is reduced by a factor of two in relation to the length that allows the resolution of the technology used.

However, the part of the gate lying on a thick layer forms a large parasitic capacitance between the source and the gate, which leads to a decrease in K _ur and an increase in K _w .

 The closest in technical essence to the claimed one is the method according to which a thin doped layer and a thick strongly doped layer are created on a semi-insulating substrate, a dielectric strip is formed and then source and drain electrodes are formed on both sides from the two sides [3] After this, it is self-aligned with the dielectric strip on the drain side, create a groove in a thick layer and form a shutter so that part of it (about half) lies on the bottom of the groove (channel), and part on the dielectric film. The method also allows to obtain a gate with a working length half the resolution of the applied structure formation technology, and the presence of a dielectric film between the gate and the heavily doped source region reduces the parasitic gate-source capacitance and gate leakage currents.

However, in the manufacture of PTSh by this method, the minimum achievable source-gate distance cannot be less than the sum of the resolving capabilities of the source, dielectric strip, and gate operations. So, when applying optical methods of structure formation, it consists of the minimum attainable dielectric strip width (≈0.5 μm) and the distance from the strip edge to the source (≈0.5 μm), roughness of the source edge (≈0.5 μm), and roughness the edges of the strip on both sides (≈1 μm), inaccuracy of alignment of the strip (≈0.2 μm) and inaccuracy of alignment of the shutter relative to the strip (≈0.2 μm). As a result, under production conditions, the resolution of the technology of formation of the structure ensures that the source-gate distance is as small as possible ≈3 μm, which leads to an increase in channel resistance in the source-gate region, an increase in K _w and a decrease in K _ur .

 The aim of the invention is to improve the parameters of the PTS by reducing the channel resistance in the source gate region.

 The goal is achieved by the fact that according to the manufacturing method of PTSh, which includes creating thin doped and thick heavily doped layers on a semi-insulating substrate, forming source, drain and dielectric electrodes between them, creating a groove in the thick layer that is self-aligned with the edge of the dielectric strip facing the drain, and the formation of the gate, which is located in the groove and partially on the strip of dielectric, first form the electrodes of the source and drain, and the strip of dielectric is applied with a width equal to the resolution replaceable structure formation technology, combining the middle strip with the edge of the source. The working length of the shutter is the same as in the prototype, and the distance of the source of the shutter is reduced to a value that is approximately half the resolution of the applied technological method of forming the structure.

In the manufacture of the transistor structure by the proposed method, the middle of the dielectric strip is combined with the edge of the source, the distance of the source of the gate is reduced to half the width of the dielectric strip, equal to the resolution of the structure formation technology. Since the source and drain electrodes are formed before the dielectric strip, the resolution of the technology consists of half the minimum strip width, the inaccuracy of alignment of the strip relative to the source, the gate relative to the strip, and the roughness of the edge of the dielectric strip facing the groove. In the case of optical methods of structure formation, the resolution of which is 0.5-0.6 μm, this value will be ≈ 0.25 + +0.2 + 0.2 + 0.5 + 1.2 μm. Thus, the distance of the source of the gate, equal to 1.2 μm, is 2-2.5 times less than in the method of the prototype, which leads to a decrease in the resistance of the channel part between the source and the gate and, therefore, improves such parameters of the transistor as K _ur and K _sh . At the same time, due to the complete passivation of the most sensitive part of the surface of the device, its resistance to environmental influences is increased.

 In FIG. 1-5 shows the technological scheme of manufacturing PTSh in accordance with the proposed method.

PRI me R. A thin n-layer with a concentration of (2-3) x 10 ¹⁷ cm ^-3 and an n ⁺ layer with a carrier concentration of (1.5-2.0) x 10 ¹⁸ cm ^is created on a semi-insulating plate of gallium arsenide by epitaxial growth or ion doping ^{- 3} . All structural elements are formed using standard domestic optical lithography equipment. First, source and drain electrodes are formed by sputter fusion of the AuGe-Au system. The distance of the source drain is 3 μm. Then form a strip of SiO ₂ with a width of 2.4 μm and a thickness of 0.2 μm, located so that 1.2 μm covers part of the channel, and 1.2 μm are located on the source electrode. After that, the groove is etched and an aluminum shutter 0.5 μm long is formed so that part of the shutter 0.25 microns long lies on the SiO ₂ strip, and the other part (0.25 microns) lies in the groove and is the working part of the shutter. At a frequency of 12 GHz, the gain in the level of K _w is 0.2-0.3 dB, and in the level of K _ur 1-2 dB.

The best samples of transistors made by this method in the case have K _{w min} 0.9-1.0 dB and K _{ur opt} 10-11 dB at a frequency of 12 GHz. Best samples of serial two-domestic ZP343A transistor at this frequency have a K _{m m} K and 1.4-1.5 dB _{opt ur} 8-9 dB. Best foreign serial sample MESFET (as of 1990 g.) MGF1405 has a K _w of 1.2 _m and K _yp dB 13 dB _opt.

Claims (1)

 METHOD FOR PRODUCING A FIELD TRANSISTOR WITH A SUBMICRON SCHOTTLE SHUTTER, which includes the formation of an active structure by depositing doped and heavily doped layers on a semiconductor semi-insulating substrate, the thickness of the heavily doped layer exceeding the thickness of the doped layer, the formation of a structure with a width equal to source and drain electrodes, etching in a heavily doped layer of the groove, self connected with the edge of the strip of dielectric layer on the side of the drain electrode, the formation of a shutter partially located at the bottom of the groove and partially on the dielectric layer, characterized in that the source and drain electrodes are formed before the strip of the dielectric layer is formed, and when the strip of the dielectric layer is formed, its middle is combined with the edge of the source electrode.

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