RU2038701C1 - Device for security communications - Google Patents

Abstract

FIELD: security communication devices. SUBSTANCE: transmitting part of device has amplifier 1, analog-to-digital converter 2, modulo-two adder 3, encoded sequence generator 4, digital-to-analog converter 5, adder 6, controlled switch 7, clock 8 and threshold unit 9. Receiving part of device has low-pass filter 10, analog-to-digital converter 11, modulo two adder 12, encoded sequence generator 13, digital-to- analog converter 14, narrow band filter 15 and clock synchronization signals generator 16. EFFECT: increased reliability. 2 cl, 2 dwg

Description

 The invention relates to secret communications.

 A device is known comprising an analog-to-digital converter (ADC), a storage unit, a pseudo-random sequence generator, a control unit, and a digital-to-analog converter (DAC).

 The disadvantage of this device is its complexity and low cryptographic stability of the transmitted information.

 Closest to the invention, the technical solution is a secret communication device containing an amplifier, a first and a second ADC, a first and a second DAC, a first and a second controllable keys, an adder, a timing device, a low-pass filter, a threshold block, a first and a second computer.

 The disadvantage of this device is its low cryptographic stability of the transmitted information and hardware complexity.

 The purpose of the invention is to increase the cryptographic stability of the transmitted information and simplify the device.

 Figure 1 presents a structural electrical diagram of a secret communication device; in FIG. 2 is a block diagram of a code sequence generator.

 The secret communication device contains on the transmitting side an amplifier 1, an analog-to-digital converter (ADC) 2, an adder 3 modulo two, a code sequence generator 4, a digital-to-analog converter (DAC) 5, an adder 6, a control key 7, a synchronizer 8, a threshold block 9 , on the receiving side, a low-pass filter 10, an ADC 11, an adder 12 modulo two, a code sequence generator 13, a DAC 14, a narrow-band filter 15, a clock synchronizer 16. The code sequence generator 4 (13) comprises a shift register 17, a key switch 18, N adders 19 modulo two, and a majority element 20.

 The secret communication device operates as follows.

 On the transmitting side, the original analog signal to be classified is fed to the input of the amplifier 1, which provides matching in amplitude and spectrum of the signal source with the subsequent part of this device. The analog-to-digital converter 2 generates a digital signal from an analog signal according to known algorithms (for example, pulse-code modulation, differential pulse-code modulation, etc.). Next, the digitized signal is fed to the first input of the adder 3 modulo two, the second input of which is supplied with a binary code sequence from the generator 4 containing the shift register 17, a removable key switch 18, N adders 19 modulo two and a majority element 20. Binary input signal An N-bit shift register 17 is supplied from the first output of the adder 3 modulo two. From the output of each of the N bits of the shift register 17, the signal is supplied to the first input of the corresponding adder 19 modulo two, at the second input there is a binary signal (zero or one) specified by the removable key switch 18. In its simplest form, the replaceable key switch is a set of N independent two-position switches, one position of each of which corresponds to a low voltage level ("0"), the other high ("1").

$\genfrac{}{}{0ex}{}{\text{при}}{\text{при}}$ $\genfrac{}{}{0ex}{}{\text{m>N/2}}{\text{m<N/2}}$
Здесь m число входных сигналов X_i 1 в наборе из N двоичных символов X_j∈ (0,1). N нечетное число.Thus, by changing the position of each of the N switches, the corresponding key combination is typed, the total number of which is 2 ^N. From the output of each of the adders 19 modulo two signals are fed to the N inputs of the majority element 20, the output of which is formed by a signal according to the rule
M _aj (X ₁ , X ₂ X _N )

$\genfrac{}{}{0ex}{}{\text{at}}{\text{at}}$ $\genfrac{}{}{0ex}{}{\text{m> N / 2}}{\text{m <N / 2}}$
Here m is the number of input signals X _i 1 in the set of N binary symbols X _j ∈ (0,1). N is an odd number.

 The indicated function is nonlinear, and the inverse function for it is not defined.

 Thus, at the second output of adder 3, a binary encoded signal is generated in the form of a sum modulo two of the original signal and the code sequence, the information content of which is not known to the third party, since it does not know the key combination.

, где t время анализа одной ключевой комбинации с учетом выявления смыслового содержания передаваемого сигнала (например, речи);
n количество лиц, одновременно осуществляющих перебор.If a third party knows the operating principle of the device, then the mathematical expectation of the search time of all possible key combinations will be

, where t is the analysis time of one key combination, taking into account the identification of the semantic content of the transmitted signal (for example, speech);
n is the number of individuals simultaneously searching.

> T₁, где Т₁ время, в течение которого информация должна быть недоступна третьему лицу.Moreover, N must be chosen from the condition

> T ₁ , where T _{1 is the} time during which the information should be unavailable to a third party.

то условиенедоступности информации третьим лицам в течение времени Т₁ будет практически всегда выполняться.If the period T ₂ change key combinations will be T ₂ <

then the condition of the unavailability of information to third parties during the time T ₁ will almost always be fulfilled.

 If the operating principle of the device is not known, then restoration of the initial information is not possible due to the non-linearity of the majorization operation.

 Next, the encoded signal is converted into analog form in a digital-to-analog converter 5 in order to preserve the original frequency band and then fed to the first input of adder 6, the second input of which is supplied with a sinusoidal clock signal from the output of chronizer 8. The frequency of the clock signal is outside the spectrum occupied by the original signal. Chronizer 8, in addition, provides clock synchronization of all digital devices. From the output of adder 6, the combined signal is supplied to a controlled key 7, which prevents the combined signal from being transmitted to the communication channel when the amplitude of the original analog signal does not exceed the value specified by threshold unit 9. This is necessary so that when organizing duplex communication (for example, telephone ) to exclude the issuance of the code sequence in the communication channel, and also to exclude the influence of two simultaneously operating chronizers on each other when the original analog signal is absent (for example, a pause during conversation).

 On the receiving side, the combined signal transmitted through the communication channel is fed to the input of the low-pass filter 10 and to the input of the narrow-band filter 15. The low-pass filter 10 provides suppression of the spectral component of the sinusoidal clock signal in the recovery channel of the original signal. From the output of the low-pass filter, the signal is fed to an analog-to-digital converter 11, identical to converter 2. From the first output of the analog-to-digital converter 11, the signal is fed to the first input of adder 12 modulo two, to the second input of which a signal from the output of the code sequence generator 13 is supplied, identical to generator 4, including the key combination. The input of the code sequence generator 13 is connected to the second output of the analog-to-digital converter 11. Such a connection of the code sequence generators 4 on the transmitting side of the generator 13 and on the receiving side ensures their self-synchronization in terms of generating identical code sequences.

 Thus, in adder 12 modulo two, the code sequence superimposed on it is removed from the original signal. In the digital-to-analog Converter 14, it is restored to analog form.

 A synchronization channel, consisting of a narrow-band filter 15 and a clock synchronizer 16, extracts a sinusoidal clock signal from the combined one and generates the necessary clock frequencies from it, thereby ensuring synchronous operation of the receiving and transmitting parts at the clock frequency.

Claims (2)

 1. A SECRET COMMUNICATION DEVICE containing on the transmitting side an amplifier, an analog-to-digital converter (ADC), an adder, to the first input of which a chronizer output is connected, and a digital-to-analog converter (DAC), and on the receiving side an ADC, DAC and low-pass filter (low-pass filter) ), characterized in that a code sequence generator, an adder modulo two, a controlled key and a threshold block are introduced on the transmitting side, the first and second outputs of the amplifier are connected to the input of which and the ADC input, while the ADC output and output the code sequence generator is connected to the first and second inputs of the adder modulo two, the first output of which is connected to the input of the code sequence generator, and the second output of the adder modulo two through the DAC is connected to the second input of the adder, the output of which and the output of the threshold block are connected respectively to the first and the second inputs of the managed key, and on the receiving side, an adder modulo two, a code sequence generator and series-connected narrow-band filter and signal generator t synchronized output, while the output of the managed key through the communication channel is connected to the inputs of the narrow-band filter and low-pass filter, the output of which is connected to the ADC input, the first and second outputs of which are connected respectively to the first input of the adder modulo two and the input of the code sequence generator, the output of which is connected to the second input of the adder modulo two, the output of which is connected to the input of the DAC.  2. The device according to claim 1, characterized in that the code sequence generator is made in the form of a shift register, N outputs of which are connected to the first inputs of N adders modulo two, the second inputs of which are connected respectively to N outputs of the key switch, while the outputs of N adders modulo two are connected to the inputs of the majority element, the output of which, as well as the input of the shift register are respectively the output and input of the code sequence generator.

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