RU2029312C1 - Device for checking deviation of alternating voltage - Google Patents

Abstract

FIELD: voltage inspection. SUBSTANCE: device has filter, null detector, two comparators, OR gate, frequency multiplier, inverter, coincidence element, binary counter, two code comparison elements, three triggers and logic unit which is made on the base of four AND-NOT gates. EFFECT: improved precision. 2 cl, 3 dwg

Description

 The invention relates to techniques for electrical measurements and can be used for proactive voltage control, for example in automatic systems for monitoring the quality of electrical energy.

 A device for monitoring the voltage level (Information leaflet N 74/0818) containing two threshold elements configured for upper and lower tolerance limits of the controlled voltage, a matching circuit, an executive body.

 The known device has limited functionality due to the inability to control levels of alternating voltage.

 The closest in technical essence to the claimed invention should be considered the device described in A.S. USSR N 625167, cl. G 01 R 19/00, 1975, containing two threshold elements tuned to the upper and lower tolerance limits of the monitored voltage, two triggers, a matching logic, a inhibit element, an actuator, a clock, a differentiating circuit and a resistive voltage divider.

 The prototype also has limited functionality, as it does not allow you to control the levels of alternating voltage. This drawback is due to the fact that the threshold elements are configured only on the positive upper and lower tolerance limits of the controlled voltage.

 The purpose of the invention is the expansion of functionality due to automatic control of alternating, for example sinusoidal, voltages of a stable frequency.

 The goal is achieved by the fact that a filter, a zero-organ, a frequency multiplier, an OR element, an inverter, a third trigger, a binary counter, a logic block, and two are introduced into the voltage control device containing the first and second comparators, the first and second triggers and the coincidence element code comparison schemes, the first information inputs of which are interconnected and connected to the output of a binary counter, the input of a matching element connected to the output, the first, second and third inputs of which are connected respectively with the output of the third trigger, you the inverter and the output of the frequency multiplier, the input combined with the first inputs of the zero-organ, the first and second comparators and connected to the output of the filter, the input of which is the input of the device, the output combined with the output of the logic unit, the first and second inputs of which are associated with the inverse output of the first and direct output of the second triggers, the input to the zero of the first and second triggers is connected respectively to the output of the first and the second output of the code comparison circuits, and the installation inputs to a single state in ex triggers combined with each other and connected to the output of the zero-body, wherein the zero setting input of the third flip-flop is combined with the input of the inverter and is connected to the output of the OR gate, the first and second inputs of which are connected respectively with the output of the first and second output comparators. The logic block is made in the form of four AND-NOT elements, the first inputs of the first and second AND elements NOT combined and are the first input of the logic unit, the second input of which is connected simultaneously to the first input of the third and second input of the second elements, the output of the last of which connected simultaneously to the second inputs of the first and third elements, the output of each of which is associated with the corresponding input of the fourth element, the output combined with the output of the device.

 The essence of the invention consists in expanding the functionality of the device by measuring the values of the angles from the moment of transition of the positive and negative half-waves of the controlled voltage to the moment that the controlled voltage is equal to the specified positive and negative voltage values.

 The claimed technical solution differs from the prototype in the presence of new blocks and elements, namely: a filter, a zero-organ, a frequency multiplier, an OR element, an inverter, a third trigger, a binary counter, a logic block, and two code comparison schemes.

 These differences allow us to conclude that the claimed technical solution meets the criterion of "novelty."

 Comparison of the claimed technical solution with other solutions shows that in the scientific and technical literature there are no devices with such a totality of new elements and corresponding connections. Thus, the claimed technical solution meets the criterion of "significant differences".

 In FIG. 1 shows a functional diagram of a device for proactive voltage control; in FIG. 2 is a functional block diagram of a logic block; in FIG. 3 - time diagrams of the operation of the device.

 The device (Fig. 1) contains a filter 1, a zero-organ 2, the first and second comparators 3 and 4, an OR element 5, a frequency multiplier 6, an inverter 7, a coincidence element 8, a binary counter 9, the first and second comparison circuits 10 and 11 codes, the first, second and third triggers 12-14 and the logic block 15, made in the form of four elements AND 16-19.

 Filter 1 is designed to extract from the input signal its first harmonic component of a sinusoidal shape. The input of the filter 1 is the input of the device, and the output of the filter is connected simultaneously to the first inputs of the zero-organ 2, comparators 3, 4 and the input of the frequency multiplier 6.

 Zero-organ 2 is intended for the formation of pulses of a single level at each transition of the sinusoid of the first harmonic component of the input signal through zero. The output of the zero-organ 2 is connected simultaneously with the inputs of the installation in a single state of triggers 12-14.

 Comparators 3 and 4 are designed to compare the amplitude of the first harmonic component of the voltage of the input signal with the given values. The outputs of the comparators 3 and 4 are connected to the corresponding inputs of the OR element 5. The setpoint for the operation of the comparator 3 corresponds to the set positive voltage value, and the setpoint for the operation of the comparator 4 corresponds to the set negative voltage value.

The frequency multiplier 6 is designed to multiply the frequency of the input signal. The multiplication coefficient of the frequency multiplier 6 is chosen equal to 36 ˙ 10 ^S (where S is a positive integer). The output of the frequency multiplier 6 is connected to the third input of the coincidence element 8.

 An inverter 7 designed to invert the output signal of the OR element 5, the input is combined with the installation input to zero of the third trigger 14 and connected to the output of the OR element 5, and the output is connected to the second input of the coincidence element 8.

 The coincidence element 8, made in the form of a logical element And, is designed to pass to its output the counting pulses arriving at the third input, while at the same time there are unit level enable signals at its second and first inputs. The first input and output of element 8 are connected respectively with the output of the third trigger 14 and the counting input of the binary counter 9.

 Binary counter 9 is designed to count the number of pulses received at its counter input. The output of the counter 9 is connected simultaneously with the first information inputs of the code comparison circuits 10, 11.

 Code comparison schemes 10 and 11 are designed to compare the digital code of the controlled angle present on the code output of the binary counter 9 with the given codes proportional to the upper and lower boundary values of the angle, respectively. Schemes 10 and 11 can be performed on the basis of the well-known (see B. I. Gorshkov. Elements of electronic devices. Handbook. M.: Radio and Communications, 1988, p. 140, Fig. 11.16) principles for constructing similar functional devices. The output of the first circuit 10 and the output of the second circuit 11 are connected respectively to the input of the installation to zero of the first and second triggers 12 and 13.

 Triggers 12-14 are made in the form of RS-triggers.

 The inverse output of the first trigger 12 is connected to the second input of the logic block 15, the first input of which is connected to the direct output of the second trigger 13. The unit inputs of the triggers 12-14 are connected to each other and connected to the output of the null organ 2.

 Block 15 logic (Fig. 2) is designed to generate the output signal of the device depending on the result of the control. Block 15 logic is made in the form of four logical elements AND 16-19. The first inputs of the first and second elements 16 and 17 are interconnected and are the first input of the logic unit 15, the second input of which is connected simultaneously to the first input of the third and second input of the second AND-NOT elements 18 and 17. The output of the second AND-NOT 17 element is connected simultaneously to the second inputs of the first and third elements 16 and 18, the output of each of which is associated with the corresponding input of the fourth element AND 19, the input combined with the output of the inventive device.

In FIG. 3 is indicated:
± U _in and ± U _n - upper and lower tolerance limits of the first harmonic component of alternating voltage U _x ;
U _gr ⁱⁿ and U _gr ⁿ - upper and lower boundary sinusoids of the first harmonic component of alternating voltage U _x ;
+ U _s and -U _s - positive and negative set values of the operating voltage of the first and second comparators 3 and 4 (see in Fig. 1);
φ is the measured angle from the moment the first harmonic component of the controlled voltage passes through zero to the moment its value is equal to the given ± U _s voltages;
α and β are the specified upper and lower values of the measured angle φ.

The set voltage values + U _s and -U _s are chosen below the voltage values + U _n and -U _n, respectively, near the level of the constant component of the controlled voltage.

(1) где F( φ) - выходной сигнал устройства, зависящий от текущего значения угла φ.When the first harmonic component of the voltage U _x is within the tolerance field (+ U _n <U _x <+ U _in either -U _n <U _x <<-U _in ), that is, when the measured φ angle is in the range from β to α , there is no signal at the output of the device, and in case of exceeding the boundaries of the tolerance field, there is a signal. Then the decisive rule implemented by the device has the form
F (φ) =

(1) where F (φ) is the output signal of the device, depending on the current value of the angle φ.

Taking into account the values of logical variables in the “Normal”, “Above” or “Below” modes, the voltage norms are U _x , based on the well-known methods of logical synthesis (see V. Polyakov and others. Theoretical foundations of the construction of the logical part of relay protection and automation of power systems M .: Energy, 1979) and a set of AND-NOT elements, the functional block diagram of the logic unit 15 can be represented in the form shown in FIG. 2.

,

};
F_в(φ) = {

,

}; (2)
F_н(φ) = {

,

}, где

- переменная, принимающая значения Х или

.The output signals of the device in the “Normal”, “Above” or “Below” modes can be presented in the form
F _o (φ) = {

,

};
F _in (φ) = {

,

}; (2)
F _n (φ) = {

,

} where

- a variable taking the values of X or

.

или
t_φ=

(3) где f и Т - частота и период измеряемого сигнала;
t_φ- временной интервал, соответствующий углу φ (фиг. 3).Then the values of logical variables in individual modes can be represented in the form presented in the table. In addition, the measured angle φ is related to the frequency of the measured voltage f by the expression
^{φ = 2πft} φ ⁼

or
t _φ =

(3) where f and T are the frequency and period of the measured signal;
t _φ is the time interval corresponding to the angle φ (Fig. 3).

= t_φf_сч (4) где f_сч и Т_сч - частота и период следования счетных импульсов.When quantizing the time interval with counting pulses, we will have that the number n _{φ of} pulses falling in the interval t _φ will be
n _φ =

= t _φ f _cf (4) where f _cf and T _cf - frequency and period of the counting pulses.

In order to reduce the frequency error, we will fill the time interval t _{φ with} pulses proportional to the frequency f of the input signal.

The frequency f of the measured signal, which may be arbitrary, is associated with the frequency f _MF repetition count pulses dependence
f = Kf _MF, (5) where K is - a numerical factor representing the frequency multiplier.

k (7)
Таким образом, количество импульсов n_φ , заполняющих интервал t_φ, является функцией измеряемого угла φ , коэффициента К и не зависит от частоты f измеряемого сигнала.Then, according to (4), it has
n _φ = t _φ Kf (6) or, after substituting t _φ from (3) into (6), we have
n _φ =

k (7)
Thus, the number of pulses n _φ filling the interval t _φ is a function of the measured angle φ, coefficient K and does not depend on the frequency f of the measured signal.

 A device for proactive voltage control is as follows.

 In the initial state, there is no controlled voltage at the input of the device, binary counter 9 and triggers 12-14 are set to zero.

In measurement mode, a controlled voltage is applied to the input of the device. At the same time, at the output of filter 1, the first harmonic component U _{x of the} voltage appears (Fig. 3a), the amplitude of which is proportional to the controlled voltage, and its shape is sinusoidal.

With increasing voltage amplitude U _x (the first half-cycle in Fig. 3a) and each transition of the voltage sinusoid through zero, a pulse (Fig. 3b) of the logic unit level will appear at the output of null-organ 2, which translates triggers 12-14 at the S input to state (Fig. 3B, d, e), preparing them to receive information on the R-input. Since the outputs of the comparators 3 and 4 are a signal of the zero level (Fig. 3e, g), then the output of the inverter 7 will present a signal of a logical unit (Fig. 3h), which will be received at the second input of the coincidence element 8. At the first input of element 8 there will be a signal of a logical unit received from the output of trigger 14. At the same time, the first harmonic component of the voltage, changing with frequency f, is fed to the input of the frequency multiplier 6, the output of which will appear counting pulses with a repetition rate f _cc = Kf arriving at the third input of element 8 (Fig. 3i). These pulses will be repeated at the output of element 8 and fed to the counting input of the binary counter 9. At the moment when the voltage U _x becomes equal to the specified positive value + U _s (or -U _s , see the second half-cycle in Fig. 3a), the comparator will work 3 (or comparator 4 for the negative half-wave) and a signal of a logical unit will appear on its output. This signal, having passed through the OR element 5, will translate the trigger 14 to the zero state on the R-input and prohibit the passage of the counting pulses from the output of the frequency multiplier 6 through the coincidence element 8. At the same time, the signal of the logical unit present at the output of the OR element 5, after inverting by the inverter 7, will go to the second input of the coincidence element 8, having a logic zero level. Thus, in the counter 9, the number n _{φ of} pulses will be accumulated (Fig. 3 k) and its code output will be fixed to the code N _φ proportional to the measured angle φ.

 The angle measurement cycle is completed.

In the angle comparison cycle, the code N _{φ is} supplied simultaneously to the first information inputs of the code comparison schemes 10 and 11. In this case, at the second information input of the circuit 10 and the second information input of the circuit 11, there are respectively set digital codes N _α and N _β . Moreover, the code N _{α is} proportional to the upper boundary value α of the measured angle φ, and the code N _β to the lower boundary value β of the measured angle.

The pulse at the output of circuit 10 or circuit 11 appears only if the code N _φ is less than the specified code N _α or N _β, respectively.

If the voltage amplitude U _x increases according to the results of comparison (see the first period in Fig. 3a), the digital code N _φ will be less than the specified codes N _α and N _β , therefore, an impulse will appear at the output of circuits 10 and 11 (Fig. 3l, m), which translates triggers 12 and 13, respectively, to the zero state. At the same time, from the inverted output of trigger 12, a unit-level signal (Fig. 3d) will go to the second input of logic block 15, and to the first input of block 15, a zero-level signal is present at the direct output of trigger 13 (Fig. 3c). The comparison cycle is complete.

After logical transformations of the signals received at the inputs of block 15, in accordance with expression (2) and the table, the output of the device will display a logical unit signal recording the event of an upcoming excess of the voltage U _{x the} upper tolerance limit ± U _n (that is, until the equality U _x = ± U _c ).

When finding the upcoming voltage U _x is within the tolerance (mode "Normal", the second period in FIG. 3a), where ± U _n <U _x <± U _{in the} measuring cycle is similar to the angle φ considered.

In the cycle of comparing the code N _φ with the given codes N _α and N _{β, the} signal of the logical unit at the output of the code comparison circuit 11 will be absent, since N _φ > N _α . Therefore, the trigger 13 will save a single state, and the trigger 12 will change the state to zero. In this case, from the direct output of the trigger 13 and the inverse output of the trigger 12 to the inputs of the block 15 of the logic will receive a signal of a logical unit.

After logical transformations of the signals in block 15, the output of the device will contain a signal of the zero level, fixing the event of the upcoming location of the voltage amplitude U _x within the tolerance field (± U _n <U _x <± U _in ).

With the forthcoming decrease in the voltage amplitude (see the positive half-wave of the third period in Fig. 3a) below the boundary ± U _{n of} the tolerance field (“Below” norm), when U _x <± U _n , the cycle of measuring the angle φ is similar to that considered.

In the cycle of comparing the code N _φ with the given codes N _α and N _β , a logic zero will be present at the output of circuits 10 and 11 and the triggers 12 and 13 retain a single state. In this case, from the inverse output of the trigger 12 to the second input of the block 15 of the logic will receive a signal of zero level, and the first input of the block 15 is a single signal present at the direct output of the trigger 13. The comparison cycle is completed.

After logical transformations of the signals in block 15, the output of the device will contain a logical unit signal recording the event of the forthcoming decrease in the voltage amplitude U _x below the tolerance limit ± U _n (that is, until the equality U _x = ± U _{n is} fulfilled).

The technical and economic effect of the claimed device is that this device allows you to control the upcoming change in the voltage amplitude not only in the region of positive voltage values U _x , but also in the region of negative values, which confirms the reliability of achieving the goal, which is to expand the functionality of the device.

Claims (2)

 1. DEVICE FOR MONITORING AC VARIABILITY CONTROL, comprising a first comparator, a zero-organ, a frequency multiplier, a coincidence element, a binary counter, the first input of the first comparator is connected to the first input of the zero-organ, the second input of which is connected to a common bus, the second input of the first comparator connected to the first output of the reference voltage source, the output of the frequency multiplier is connected to the first input of the coincidence element, the output of which is connected to the input of the binary counter, characterized in that, in order to expand the function In order to achieve this, a filter, an OR element, a second comparator, an inverter, three triggers, a logic block and two code comparison elements are introduced, the filter input connected to the device input and the output connected to the first inputs of the first and second comparators and the multiplier input, the outputs of the first and the second comparators are connected respectively to the first and second inputs of the OR element, the output of which is connected to the inverter input and the installation input at “0” of the first trigger, the output of which is connected to the second input of the coincidence element, the third input connected to the inverter output, the second input of the second comparator is connected to the second output of the reference voltage source, the zero-organ output is connected to the unit inputs of all triggers, the output of the binary counter is connected to the first information inputs of the code comparison elements, the second information inputs of which are connected to the outputs of the code setter, and the outputs are connected to the inputs of the “0” setting of the second and third triggers, respectively, the direct output of the third trigger and the inverse output of the second trigger with are connected respectively with the first and second inputs of the logic block, the output of which is connected to the output of the device.  2. The device according to claim 1, characterized in that the logical unit contains four AND elements - NOT, moreover, the first inputs of the first and second elements AND - NOT combined and connected to the first input of the block, the second input of which is connected to the first input of the third and second input the second element AND is NOT, the output of the second element AND is NOT connected to the second inputs of the first and third elements AND is NOT, the output of each of which is connected respectively to the input of the fourth element AND is NOT, the output of which is connected to the output of the block.

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