RU2024920C1 - Device for time count - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: effect is achieved by the fact that a reconfiguration unit with new connections is complementarily introduced into the device having two bidirectional commutators, a counter, a control unit, a comparator unit, memory unit of information digits, memory unit of checking digits, two commutators, a register, transfer prognosis block, prognosis block of the byte parity, block of signal normalization of the device state, element of convolution to the modulus two and OR element with the corresponding connections. EFFECT: reduction of apparatus expenses. 5 dwg

Description

 The invention relates to computer technology and is intended for organizing, together with the processor in a computer, an astronomical time reference (clock function) for fixing a predetermined time instant (comparator function), for measuring the elapsed processor time (processor timer function) and can be used in any computer class, for example, in EU computers.

A device for counting time, containing a 20-bit counter, the first and second buffer memory. In the indicated device, using a 20-bit counter, every second (after 2 ²⁰ μs) signals are generated about the microprogram interrupt to the processor (microprocessor), which are requests to the processor to service the device. In parallel, the indicated request signal is stored in the first buffer memory and subsequently rewritten in the second buffer memory if the processor does not read data from it. If there is a delay in the occurrence of a firmware interrupt in the processor for servicing the device (due to, for example, a processor shutdown or due to the execution of the “boot-up” procedure in the processor), for a few seconds all the indicated request signals arising every second are stored (accumulated) in the second buffer memory ( through the first buffer memory). When the processor “serves” the device, it reads all the data from the second buffer memory sequentially and accordingly modifies the second counter organized by the firmware in the processor. In this case, overwriting data from the first buffer memory to the second is prevented, and possible new request signals generated by a 20-bit counter in the device are stored (accumulated) in the first buffer memory. Data from the first buffer memory is written to the second buffer memory after the processor has finished reading data from it.

 The disadvantages of this device are the large hardware costs associated with the use of the first and second buffer memories and a limited class of tasks due to the inability to organize a processor timer and a comparator using the device.

 A device for counting time, containing a 20-bit counter comparator and a 52-bit hour meter. The highest (32) bits of the processor timer, when using the specified device, are organized in the processor as a microprogram counter by using the corresponding (32-bit) cell in the local memory of the processor, the contents of which are modified (the unit is subtracted) after the transfer from the high-order bit of the 20-bit counter appears processor timer and corresponding firmware interrupt in the processor. To organize the comparator, a 52-bit cell is allocated in the processor’s local memory in which the comparator value is stored. According to the signals from the device generated every second, a firmware interrupt is carried out in the processor, after which the processor performs "maintenance" of the device. The clock value is read from the 52-bit counter and the comparator value is subtracted from the clock value. If the obtained difference corresponds to a time value greater than one second, then the calculation of the specified difference is repeated after a second. If the received difference has a value less than (equal to) one second, then the difference code is loaded into the 20-bit counter of the comparator, which, after the remaining time, issues an external interrupt request from the comparator.

 The disadvantage of this device is the high hardware costs due to the use of a 52-bit hour meter and low reliability of the account.

 Closest to the technical nature of the claimed is a device for counting time, containing the first and second bidirectional switches, counter, control unit, a comparison unit, a memory block of information bits, a memory block of control bits, the first and second switches, a register, a byte parity prediction block, a state block, a convolution element modulo two, an OR element, wherein the group of address inputs of the memory block of the control bits is connected to the group of address inputs of the memory block of the information bits and with uppa of the address outputs of the control unit, the start input of which is the start of the device, the input of the external exchange operation task is connected to the input of the external exchange operation task input, the group of inputs of the initial conditions setting which is the group of inputs of the initial conditions setting of the device, the first group of clock inputs of the control unit is the first group of clock inputs of the device, the input of the overflow fixation of the device status block is connected to the overflow output of the prediction block noses, the group of outputs of which is connected to the second group of inputs of the byte prediction unit, the first group of inputs of which is connected to the group of information inputs of the carry prediction unit, with the group of bit outputs of the counter and with the group of information inputs of the memory block of information bits, the control input of which is connected to the control input the memory block of the control bits and with the sixth output of the control unit, the seventh output of which is connected to the control input of the second switch, the group of outputs of which is connected to the group of information inputs of the register, and the second group of information inputs of the second switch is connected to the second group of outputs of the byte prediction unit, the first group of outputs of which is connected to the second group of inputs of the comparison unit, the first group of inputs of which is connected to the group of bit outputs of the register and to the group of information the inputs of the control bit memory block, the output group of which is connected to the first group of information inputs of the second switch and to the second group of information inputs / outputs of the second bi-directional switch, the second group of information inputs / outputs of the first bi-directional switch is connected to the group of outputs of the memory block information bits and to the group of information inputs of the counter, the input resolution account which is connected to the first output of the control unit, the second output of which is connected to the input ban the first, second bi-directional switches and the first switch, inputs for controlling the transmission of information of the first and second bi-directional switches s with the third output of the control unit, the fourth output of which is connected to the information transfer control input of the first switch, the first group of information inputs / outputs of the first bi-directional switch is a group of inputs / outputs for setting the time of the device, the first group of inputs / outputs of the second bi-directional switch is a group of inputs / outputs control bits of the device, the group of information outputs together with the output of the parity bit of the first switch is a group of signal outputs in the state together with the output of the parity check bit of the device, the error output of which is connected to the output of the comparison unit, and the group of status block status outputs is connected to the corresponding inputs of the convolution element modulo two and to the information inputs of the first switch, the input of the parity discharge of which is connected to the output of the element two convolutions, the corresponding inputs of which are connected to the inputs of the OR element, the output of which is connected to the output of the device request, the control input of the status block is connected with the fifth output of the control unit, the output of the end of the external exchange operation of which is the output of the end of the external exchange operation of the device, the corresponding clock inputs of the second group of clock inputs of which are connected to the groups of clock inputs of the first; the second bi-directional switches, the first switch, counter, register, status block and with the second group of clock inputs of the control unit.

 The disadvantage of this device is the large hardware costs due to the need to use 52-bit counters of the first bi-directional switch, memory block information bits.

 The purpose of the invention is to reduce hardware costs by making it possible to use a 20-bit counter, a first bi-directional switch, a memory block of information bits while providing a solution in a computer processor for all tasks solved using the prototype.

 This goal is achieved in that the device for counting time, containing the first and second bi-directional switches, counter, control unit, comparison unit, memory block information bits, memory block control bits, the first and second switches, register, transfer prediction unit, parity prediction block bytes, a status block, a convolution element modulo two, an OR element, and the group of address inputs of the memory block of the control bits is connected to the group of address inputs of the memory block of the information bits and with a group of address outputs of the control unit, the start-up input of which is the start-up input of the device, the input of the external exchange operation task is connected to the input of the external exchange operation task input, the group of inputs of the initial condition setting of which is the group of input settings of the device initial conditions, the first group of clock inputs of the block control is the first group of clock inputs of the device, the input of the overflow fixation of the status block is connected to the overflow output of the carry prediction block, g the output sequence of which is connected to the second group of inputs of the byte parity prediction block, the first group of inputs of which is connected to the group of information inputs of the carry prediction block, with the group of bit outputs of the counter and with the group of information inputs of the memory block of information bits, the control input of which is connected to the control input of the memory block control discharges and with the sixth output of the control unit, the seventh output of which is connected to the control input of the second switch, the group of outputs of which is connected on with a group of information inputs of the register, and the second group of information inputs of the second switch is connected to the second group of outputs of the byte prediction unit, the first group of outputs of which is connected to the second group of inputs of the comparison unit, the first group of inputs of which is connected to the group of bit outputs of the register and to the group of information the inputs of the control bit memory block, the output group of which is connected to the first group of information inputs of the second switch and to the second group of information inputs o / outputs of the second bi-directional switch, the second group of information inputs / outputs of the first bi-directional switch is connected to the group of outputs of the memory block information bits and to the group of information inputs of the counter, the input of the resolution of which is connected to the first output of the control unit, the second output of which is connected to the input of the prohibition of the first , the second bidirectional switches and the first switch, the information control inputs of the first and second bidirectional switches are connected to third the second output of the control unit, the fourth output of which is connected to the control information transfer input of the first switch, the first group of information inputs / outputs of the first bidirectional switch is a group of inputs / outputs of the device's time setting, the first group of information inputs / outputs of the second bi-directional switch is a group of control inputs / outputs bits of the device, the group of information outputs together with the output of the parity bit of the first switch is a group of outputs status signals together with the output of the parity bit of the device, the error output of which is connected to the output of the comparison unit, and the group of status block status outputs is connected to the corresponding inputs of the convolution element modulo two and to the information inputs of the first switch, the input of the parity bit of which is connected to the output of the element two convolutions, the corresponding inputs of which are connected to the inputs of the OR element, the output of which is connected to the output of the device request, the output of the end of external exchange operations which is connected to the output of the end of the external exchange operation of the control unit, the fifth output of which is connected to the control input of the status unit, the group of clock inputs of which, as well as the group of clock inputs of the first and second bi-directional switches, the first switch, counter, register and the second group of clock inputs of the control unit connected to the corresponding clock inputs of the second group of clock inputs of the device, further comprises a reconfiguration node, and the control output of the status block is connected to the first the control input of the reconfiguration node, the first output of which is connected to the counter reset input, the counting input of which is connected to the control input of the carry prediction unit and the byte parity predictor and the second output of the reconfiguration node, the second control input of which is connected to the eighth output of the control unit carry prediction is connected to the third control input of the reconfiguration node, the group of clock inputs of which is connected to the corresponding clock inputs of the second group of clock inputs rows device.

 The proposed device contains such features as a reconfiguration node with connections that are absent in all analogues and due to which a positive effect is achieved - a reduction in hardware costs by reducing the bit capacity (up to 20 bits) of the counter (hours). The structure of the reconfiguration node is also new, but may be different depending on the element base used.

 Since the proposed device contains signs that are not found in any analogue and ensure the achievement of a positive effect, it meets the criterion of "significant differences".

 In FIG. 1 shows a block diagram of a device; in FIG. 2 is a block diagram of a device control unit; in FIG. 3 is a functional block diagram of a device status block; in FIG. 4 is a functional diagram of a device reconfiguration unit; in FIG. 5 is a functional diagram of a carry prediction unit and a parity prediction unit with links.

 Numbers in rectangles (squares) and near them in FIG. 1 - FIG. 5 marked: 1 - the first bi-directional switch; 2 - the second bi-directional switch; 3 - the first switch; 4 - counter; 5 - control unit; 6 - block comparison; 7 - memory block information bits; 8 - memory block control bits; 9 - the second switch; 10 - register; 11 - block prediction hyphenation; 12 - block prediction parity bytes; 13 - reconfiguration node; 14 - state block; 15 - a convolution element modulo two; 16 - element OR; 17 - the first output of the node 13, the reset input of the counter 4 and register 10; 18 - the second output of the node 13, the counting input of the counter 4, the control input of blocks 11 and 12; 19 - control output of block 14, the first control input of node 13; 20 - the second control input of the node 13, the eighth output of block 5; 21 - the first group of inputs / outputs of the switch 1; 22 - the first group of inputs / outputs of the switch 2, a group of inputs / outputs of the control bits of the device; 23 - a group of outputs together with the output of the parity bit of the switch 31, a group of outputs of the status of the device together with the output of the parity bit; 24 - group of status outputs of block 14, the corresponding inputs of element 15, a group of information inputs of switch 3; 25 - the output of the device request, the output of element 16; 26 is the output of the end of the external exchange operation of unit 5 and the device; 27 - input job external operations of the device and unit 5; 28 - inputs of element 16; 29 - input bit parity group information inputs of the switch 3, the output of the element 15; 30 - a group of outputs of the switch 9, a group of information inputs of the register 10; 31 - a group of bit outputs of the counter 4, a group of information inputs of blocks 7, 11, the first group of inputs of a block 12; 32 - group of outputs of block 11, the second group of inputs of block 12; 33 - the output of block 6, the error output of the device; 34 - output overflow block 11, input fixation overflow block 14, the third control input node 13; 35 - the second group of outputs of block 12, the second group of information inputs of the switch 9; 36 - the first group of outputs of block 12, the second group of inputs of block 6; 37 — control input of block 14, fifth output of block 5; 38 - the first group of inputs of block 6, the group of outputs of register 10, the group of information inputs of block 8; 39 - control input of the switch 9, the seventh output of block 5; 40 - control input of blocks 7, 8, the sixth output of block 5; 41 - group of address inputs 7, 8, group of address outputs of block 5; 42 - group of outputs of block 8, the second group of information inputs / outputs of switch 2, the first group of information inputs of switch 9; 43 - input counter resolution counter 4, the first output of block 5; 44 - input control information transfer switch 3, the fourth output of block 5; 45 - input prohibition of switches 1, 2, 3, the second output of block 5; 46 - input control information transfer switches 1, 2, 3, the third output of block 5; 47 - the second group of clock inputs of the device; 48 - the second group of clock inputs of block 5; 49 - input start device and block 5; 50 - group of inputs for setting the initial conditions of the device and block 5; 51 - the first group of clock inputs of the device and block 5; 52 - group of clock inputs of block 14, the corresponding clock inputs of the group of inputs 47; 53 - a group of clock inputs of the counter 4, register 10, node 13; 54 - a group of clock inputs of switches 1, 2, 3; 55 - group of outputs of block 7, a group of information inputs / outputs of switch 2; 56 - internal control unit of block 5; 57 - control unit external exchange unit 5; 58 - node comparison unit 5; 59 - node generating the address signals of block 5; 60 - the first group of clock inputs of the node 56 (clock signals> T3BOV,> T4BOV), the corresponding inputs of the group of inputs 51; 61 is a group of clock inputs of the node 58 (clock signals> SI2-BOV,> SI4-BOV), the corresponding inputs of the group of inputs 48; 62 - the second group of clock inputs of the node 56 (clock signals> SI4-BOV,> SI6-BOV), the corresponding inputs of the group of inputs 48; 63 - the second group of clock inputs of the node 57, (clock signals> C1BOVD,> S2BOVD,> TI2-SI2,> TI3-C2), the corresponding inputs of the group of inputs 48; 64 - the first group of clock inputs of node 57 (clock signals> TT2-C1,> TT4-C2,> RTI1P1,> TT5-C1, RTI2B,> T5BOV), the corresponding inputs of the group of outputs 51; 65 - group of clock inputs of the node 59 (clock signals> SI1-BOV,> SI6-BOV), the corresponding inputs of the group of inputs 48; 66 is a group of address outputs of a node 57, a first group of inputs of a node 58, a second group of inputs of which are connected to a group of address outputs of a node 79 and to a group of address outputs 41; 67, 68, 69, 80 - triggers in block 14; 70, 75, 76 - AND-NOT elements in block 14; 71, 73, 74, 77, 81 - AND-NOT elements in block 14; 72 - element NOT in block 14; 78 - element And in block 14; 79 - element 3 AND-OR-NOT in block 14; 82 - synchronization input (corresponding to the signal> SI3-BOV) of the group of inputs 52; 83 - synchronization input (corresponding to the signal> SI4-BOV) of the group of inputs 52; 84, 85, 86 — inverse outputs of elements 70, 75, 76, respectively; 87 — inverse output of element 79; 88 - inverse trigger output 80; 89 - direct output of the trigger 80, the corresponding discharge of output 19; 90 - output element 81, the corresponding discharge output 19; 91 - an AND-NOT element in node 13; 92 - AND-NOT element in node 13; 93, 94 - triggers in node 13; 95 - the element And in the node 13; 96 - AND-NOT element in node 13; 97 - an AND-NOT element in node 13; 98, 99 - And elements in block 11; 100, 101 - And elements in block 11; 102 is a node generating parity signals in block 12; 103 — output of predicted byte parity signals of node 102; 104, 105 - the switch in block 12.

 The signal identifiers shown above the corresponding links in FIG. 2-4 correspond to the accepted identifiers (designations) of the same signals (and links) in the document [3].

 The numbers around the groups of inputs and outputs in FIG. 5 indicate the numbers of discharges or inputs and outputs.

 Bidirectional switches 1, 2 and switch 3 are designed to connect the device to a common trunk of the central processor and organize the exchange of information with the central processor. In structure and functioning, switches 1, 2, 3 are identical to the prototype switch of the same name and can be built on microchips of the type KM500RS3 or KS1543IR1. Switches 1, 2, 3 operate as follows. When logic 45 is set at input 45 (> ЕРД = 0), information is prohibited from recording from any group of inputs / outputs of the switches to the internal register. When a logical unit is installed at input 45 (> ERD = 1), information is recorded in the internal register of switches 1, 2, 3 from the first or second group of information inputs / outputs of switches (depending on control signals at input 46, 44) under the action of clock pulses at the clock inputs 54. The group 54 clock inputs consists of two clock inputs, the first of which is supplied with a clock signal> C1BOV, which captures the input information, and the second -> signal S2BOV, which records the information for transmission to the outputs.

 When generating signals> DE1RD = 0 and> DE3RD = 0 at the bits of the inputs 44, 46, the transmission of information to the inputs / outputs from the outputs of the internal register is blocked. When generating signals> DE1RD = 1,> DE3RD = 1, information is transferred from the second group of information inputs / outputs and from inputs 24 and 29 to the information inputs of the internal registers for writing to the registers and information is transmitted from the outputs of the internal registers of the switches to the outputs 23 of the switch 3 and (when generating a signal> SРД = 0 on the corresponding discharge bit of output 46 (see Fig. 2)) to the first group of information inputs / outputs of switches 1, 2. When generating a signal> SРД = 1 (with a signal> ДЕ1РД = 1), transferring information back m direction. Information transfer in the opposite direction in the switch 3 is not provided.

 Counter 4 is intended for intermediate storing of clock values, comparator, processor timer and for modification (counting) of indicated values. Counter 4 can be implemented, for example, on microchips of the type KM500ST2 or KS1543IE1. The counter 4 operates as follows. With a logical zero (> E2C4 = 0) at input 43, counter 4 is set to write code from the information group of inputs under the action of clock signals at inputs 53. With a logical unit (> E2C4 = 1) at input 43, counter 4 is set to counting mode at logical unit at input 18 or in storage mode with a logical zero at input 18.

 The described modes are set with a logical unit at input 17. With a logical zero at input 17, counter 4 is "reset" under the action of clock signals at inputs 53.

 The control unit 5 (Fig. 2) is designed to generate control signals for all nodes and units of the device, to generate the addresses of the clock, switch and processor timer in the required time period and to generate the signal for the end of the external exchange operation at the output 26.

 The block diagram of block 5 is shown in FIG. 2. Block 5 comprises an internal control unit 56, an external exchange control unit 57, a comparison unit 58, an address signal generation unit 59.

 The block diagram of block 5 differs from the block diagram of the prototype control unit by the presence of an additional output 20, on the discharges of which the signals> PKM1,> 3PBOV,> SPADR2, RTP,> P4C2 are generated, the formation of which is already provided for in the prototype control unit.

 Due to the fact that the structural changes of block 5 are unambiguously determined by the presence of a sign — output 20 and the functioning algorithm of node 13, the authors and the applicant consider it inappropriate to include the signs of the control unit in the claims.

 The moments of appearance and destination of signals 3PBOV, SPADR2,> P4C2,> RKM2,> RTP2,> RESET, RTP,> RKM1,> UPR, UPR,> WRRAMD,> E1RAMD,> ADR1,> ADR2,> TSP,> SPADR1 will be explained below and when describing the operation of the device.

 Block 6 comparison is designed to compare the values of the control bits from the group of outputs 38 of the register 10 and from the group of outputs 36 to generate error signals at the output 33.

 Block 7 memory information bits and block 8 memory control bits are designed to store codes of the current values of the clock (comparator, processor timer) and control codes of values of byte signals of parity codes of the current values of the clock (comparator, processor timer). Blocks 7, 8 operate as follows. When generating a signal> E1 RAMD = 0 at the corresponding bit of input 40, the outputs of blocks 7, 8 are blocked, and when generating a signal> E1 RAMD = 1 and a signal> WRRAMD = 0 at the corresponding bits of input 40, the information stored in the blocks is read out at the address whose code is installed on inputs 41. When generating signals> Е1 RAMD = 1 and> WRRAMD = 1, the write operation is performed in blocks 7, 8 at the address whose code is installed on inputs 41.

 The switch 9 is intended for transmitting control codes of parity signals from the group of outputs of block 8 (for signals> UPR = 1, UPR = 0 at the corresponding bits of input 39) or from the group of outputs 35 (for signals> UPR = 0, UPR = 1).

 Register 10 is intended for temporary storage of control codes of parity signals transmitted from the outputs of block 8 or outputs 35 of block 12.

 Block 11 prediction carry (Fig. 5) is designed to generate signals byte-predicted hyphenation at outputs 32, the predicted overflow signal at output 34.

 Block 11 can be built on the elements And 98, 99, 100, 101. With a logical zero at the input 18 of block 11 at all outputs 32, 34 is set to logical zero (ie, the formation of transfers is blocked). With a logical unit at the input 18 of block 11, the formation of carry signals is provided in accordance with the algorithm specified by the functional diagram of block 11 in FIG. 5.

 The structure and functioning of block 11 are identical to the structure and functioning of the prototype block of the same name with the difference that the number of outputs in the group of outputs 32 is two (instead of six) and control input 18 is introduced.

 The byte parity prediction block 12 (Fig. 5) is used to generate byte parity signals (at the outputs 36) for the code installed at input 31 and the predicted byte parity signals (at the outputs 35) for the code installed at input 31 after its modification. Block 12 contains a parity signal generation section 102, switches 104, 105. At the output 36, parity byte parity signals are generated for the code installed at input 31. At the outputs 103, predicted parity signals are generated for each code byte installed at input 31, i.e. it is assumed that one is added to the code value of each byte (in the least significant bit of the byte) and a predicted parity signal is generated at the corresponding output 103 for the sum code received. Node 102 can be built on ROM elements appropriately encoded (as in the prototype). Depending on the presence or absence of transferring the code in bytes to the corresponding output 35, a signal is transmitted either from the corresponding output 103 or from the corresponding output 36. With a logic zero at input 18, the signal from the corresponding output of the group of outputs 36 is always transmitted. With a logical unit at input 18, the signal from the corresponding output of the group of outputs 103 is always transmitted to the corresponding output of the group of outputs 35.

 The structure of block 12 differs from the structure of the eponymous block of the prototype by the presence of an additional switch 104 with connections.

 Since changes in the structure of blocks 11, 12 are due to the presence of a sign - connection 18, the authors consider it inappropriate to describe the structure of blocks 11 and 12 in the claims.

 Reconfiguration node 13 is designed to generate control signals that automatically change the operating mode of the device (reconfiguration of connections in the device) so that the device switches from the "count" mode (hours, comparator, processor timer) to the "save hour count" mode. Node 13 (Fig. 4) can be built on AND-NOT elements 91, 92, 96, 97, AND 95, triggers 93, 94. In the initial state, bits 0, 9 of input 19 are set to logical zeros, under which triggers 93 , 94 are kept in the "zero" state, and at the outputs 17, 18 - logical units. When the logic unit 19 input 19 is set at bit 90, trigger 94 switches to the “single” state only when signals> P4C2 = 1, RTP = 1,> PO = 1 at the corresponding bits of input 20. When this occurs, the subsequent signal RTP = 0 trigger 94 again goes into the “zero” state and saves it until the signal reappears> P4C2 = 1,> PO = 1. When a signal> P4C2 = 1 appears, a logic zero is set at the inverted output of element 96, which holds a logical unit at output 18, regardless of the state of discharge 89 of input 19. Logical zero at output 18 is set only with a logical unit at discharge 89 of input 19, the presence of a signal > Р4С2 = 0 and the “zero” state of the trigger 94. Each time when signals> 3ПБОВ = 1,> СПАДР2 = 1, the triggers 93, 94 are set to the “zero” state. Moreover, with a logical unit at bit 89 and a signal> PKM1 = 1, logic zero is set at output 17, and trigger 93 is set to a “single” state. Triggers 93, 94 are switched by the action of clock signals> SI3 = 1,> SI4 = 1, which are formed sequentially at the inputs 82, 83 of the group of inputs 53.

, F обозначены соответственно инверсный и прямой выходы триггеров, переключение состояния которых осуществляется после окончания действия сигнала > СИ3=1 на входе С1 и начала действия сигнала > СИ4=1 на входе С2.In FIG. 4 letters D, R, E near the inputs of flip-flops 93, 94 (as in Fig. 3 near the inputs of flip-flops 67, 68, 69, 80) respectively indicate the information input, reset input (with a logic zero), and a switch inhibit input ( at logical zero). Letters

, F denotes the inverse and direct outputs of triggers, respectively, the switching of the state of which is carried out after the action of the signal> SI3 = 1 at the input C1 and the start of the signal> SI4 = 1 at the input C2.

 The state block 14 (Fig. 3) is intended for generating device status signals, including an interrupt signal (> PRTP) from the processor timer, an interrupt signal (> PRKM) from the comparator, an interrupt signal (> ППС) from a clock, a signal (> PRKF ) interruptions for reconfiguration.

 Block 14 can be built on the elements AND-NOT 70, 71, 75, 73, 76, 77, 74, 81, NOT 72, 3-OR 79, triggers 67, 68, 69, 80. Triggers 67, 68, 69, 80 function in the same way as triggers in node 4 (see description of node 4) and can be implemented on KC1543TM2 or KM500TT2 microcircuits.

 Triggers 67, 68, 69 are set to “zero” state when generating a signal> RESET = 1 at the corresponding bit of input 37. Moreover, triggers 67, 68, 69 are set to “zero” state only if they were in “single” trigger state 80 or in a “single” state. If trigger 67 (68, 69) is in the “zero” state (with the trigger state zero) and signals RESET = 1,> RFC2 = 1 (> RCM2 = 1,> РТП2 = 1),> РО = 1, at the discharges of input 37, then setting the “zero” state of trigger 67 (68, 69) is pre it is rejected (due to the blocking of element 71 (73, 74) and the setting of the “single” state of the specified trigger by writing a logical unit from the input> PO = 1 is ensured. Thus, unlike the prototype, loss of interrupt signals is prevented (due to the use of elements 70, 71 (73, 75 and 74, 76) when generating a signal> RESET = 1). The described positive effect is additional in relation to the main one and is dependent on the main one. If the logical unit from input 34 (> PO = 1) is fixed in one of the triggers 67, 68, 69 with the simultaneous appearance of the signal> RFC2 = 1 (> RCM2 = 1,> RTP2 = 1) and after that the signal> RESET does not appear = 1 up to the reappearance of the signal> PO = 1, then when the signal reappears> PO = 1 with the simultaneous appearance of the signal> RFC2 = 1 (> RCM2 = 1,> RTP2 = 1), switching to the "single" state (via the element 79) trigger 80. At bits 89, 90, logical units are set. At the same time, at bit 90, the logical unit is set before the appearance of clock signals> SI3 = 1,> SI4 = 1, and at bit 89 of output 89, the logical unit is set after the signal> SI3 = 1 at the time of the signal> SI4 = 1. As a result, timely switching is ensured flip-flops in node 13 and a change in the operating modes of the counter 4. When signals> 3ПБОВ = 1,> СПАДР2 = 1, trigger 80 is set to the "zero" state.

 The device operates as follows. In the initial state, inputs 47, 51 do not receive clock signals. After power is turned on, through serial reset circuits not shown in the drawings, zero codes are entered into all trigger and register memory elements. At inputs 27, a zero code is set. The inputs 50 are set to the required codes of the initial conditions. Input 49 is a trigger signal representing 500 ns pulses arriving at input 49 with a frequency of 1 μs. Then the clock signals are launched at inputs 47, 52. The input clock 47 starts receiving clock signals of the master series:> C1BOV (> C1BOVD),> S2BOV (> S2BOVD), the main one; series:> SI1-BOV,> SI2-BOV,> SI3-BOV,> SI4-BOV,> SI6-BOV; processor series:> TI2-C2,> TI3-C2. Input 51 starts to receive clock signals of the auxiliary main series:> T3BOV,> T4BOV,> T5BOV and auxiliary processor series:> TT2-C1,> TT4-C2,> TT5-C1,> RTI1P, RTI2V. Signals> С1БОВ (> С1БОВД) and> С2БОВ (> С2БОВД) are pulses with a duration of less than 20 ns and more than 10 ns, each arriving at its own clock input with a frequency of (40-46.6) ns. In this case, in the absence of a pulse> С1БОВ (> С1БОВД), a pulse> С2БОВ (> С2БОВД) appears and vice versa. Signals> SI1-BOV,> SI2-BOV,> SI3-BOV,> SI4-BOV,> SI5-BOV,> SI6-BOV are signals of the same duration as the signals> C1BOV (> S2BOV), arriving in series each to "own", respectively, the first, second, third, fourth, fifth, sixth clock inputs. The frequency of arrival of each pulse at its own clock input is (120-140) ns. In this case, the pulse> SI-BOV appears at the i-th clock input in (20-23.6) ns after the onset of the pulse> SI (i-1) -BOV at the (i-1) -th clock input. Signals> TI2-C2 and> TI3-C2 correspond to signals> SI2-BOV and> SI3-BOV, but the appearance of pulses> TI2-C2 and> TI3-C2 is not synchronized with the appearance of pulses> SI2-BOV and> SI3-BOV. For this reason, the moments of the appearance of pulses> TI2-C2 can coincide with the moments of the appearance of pulses> SI2-BOV or> SI4-BOV,> SI6-BOV, and the moments of the appearance of pulses> TI3-C2 can coincide with the moments of the appearance of pulses> SI1-BOV, > SI5-BOV. Signal> SI5-BOV to the device is not used. Signals> T3BOV,> T4BOV,> T5BOV are pulses of duration (40-46.6) ns, each arriving at its own clock input with a frequency of (120-140) ns. In this case, the pulse> T3BOV acts during the action of pulses> SI2-BOV,> SI3-BOV, the pulse> T4BOV acts during the action of pulses> SI3-BOV,> SI4-BOV, the pulse> T5BOV acts during the action of pulses> SI4-BOV ,> SI5-BOV. Clock signals> T1BOV,> T2BOV,> T6BOV in the device are not used.

 Signals> TT2-C2,> TT4-C2,> TT5-C1 are similar to signals> T2BOV,> T4BOV,> T5BOV, but they are formed asynchronously, i.e. signals> TT2-C2 (> TT4-C2) can coincide in time of appearance with signals> T2BOV,> T4BOV,> T6BOV, and the signal> TT5-C1 can coincide with signals> T1BOV,> T3BOV,> T5BOV.

 Signals> RTI1P1 and RTI2B are pulses whose duration is a multiple of (120-140) ns, and the frequency of occurrence is asynchronous, i.e. the moments of occurrence are not predetermined, because correspond to the moments of turning on (turning off) the synchronization of the central processor during interruptions in its operation in connection with the interaction of RAM with input / output channels.

 Signals> TT2-C2,> TT4-C2,> TT5-C1,> RTI1P1,> RTI2V,> TI2-C2,> TI3-C2 must be used to partially synchronize the operation of the device with the operation of the central processor during information exchange, which is associated with a specific the implementation of the device, its use.

 Then, the firmware (using the central processor) through the inputs / outputs 22, 21 sets the zero readings (zero code) of the clock, the comparator, the processor timer by setting the inputs 27 sequentially, each time after the ready signal appears on the output 26, the clock recording code, comparator, processor timer.

 Then, the clock reading code is set at the inputs 27 and, after the ready signal appears at the output 26, the device is considered initialized.

Thus, the following codes can be set at input 27:
- zero code - in the absence of external information exchange operations (with a central processor or processor);
- code for recording hours (КЗЧ) - to record a new value for hours;
- Comparator Record Code (CLC) - to record a new comparator value;
- processor timer recording code (CTC) - to record a new processor timer value;
- code for reading the clock (KCHCH) - to read the value of the clock;
- comparator read code (CCC) - to read the value of the comparator;
- processor timer read code (CCT) - to read the value of the comparator.

 At the same time, when the input of 27 codes КЗЧ, КЗК, КЗТ is set at the inputs / outputs 21, codes for the values of the clock, the comparator of the processor timer are transmitted from the central processor, and at the inputs / outputs 22 are set their parity codes. In block 5, after the appearance of the signal> TSP at the input of the node 58 and the sequential appearance of the signals> ADR1 and> ADR2 at the corresponding outputs of the node 59, the signals> SPADR1 and> SPADR2 appear in the corresponding sequence in the corresponding outputs. Under the action of a signal> E1 RAMD, at the discharge of input 40 and a code at input 27 of node 57 and a combination of clock signals at inputs 63, 64 of node 57 at outputs 44, 45, 46 of node 57 and block 5, signals are generated in the required sequence to record the codes set at the inputs / outputs 21, 22 to the internal register of switches 1, 2. However, only after the required combination of signals OPR,> UPR,> E2C4,> WRRAMD,> E1 RAMD appears at the outputs 39, 43, 40, providing rewriting of codes from the internal registers of the switches 1, 2 to counter 4 and register 10 onwards to memory blocks 7 , 8, under the action of the signal> SPADR2 at the input of node 57, output 26 displays a signal (logical unit) of the end of the external exchange operation. At the same time, the parity of the received codes is monitored using blocks 11, 12, 6. If an error occurs, an error code is generated at output 33. Signals (logical units)> ADR1,> ADR2 appear sequentially one after another for a time (120-130) ns each (in a time interval (> SI1-BOV -> SI6-BOV) with a frequency of (240-260) ns. Signals> SPADR1,> SPADR2 are identical to the signals, respectively> ADR1,> ADR2, but only appear when a signal> TSP appears at the output of node 58.

 The described mode of operation of the device is a recording mode (RE).

 When 27 codes of KCHCh, KChK, KChT are installed at the input, the device starts functioning in the reading mode, which differs from the counting mode (PC), set when the code at input 53 is zero, only in that during the action of the signal> SPADR1 at outputs 44, 45 , 46 of block 5, such a set of signals is formed that provides for writing codes read from blocks 7, 8 and from inputs 29, 24 to the internal register of switches 1, 2, 3 and issuing them to inputs / outputs 21, 22, 23 at the required moment time determined by the moment of occurrence of the pulse TI2-C2. Moreover, as in the reading mode, the signal (logical unit) at the output 26 appears under the action of the signal> SPADR2 at the time of the signal> TT4-C2. Logical zero at output 26 is set both in the recording mode and in the reading mode through (120-130) ns at the moments of the action of signals> TT4-C2, RTI2V. In read mode, a reset signal (logical unit) is also generated (> RESET) at the discharge bit of output 37 of block 5 (see Fig. 2), under the action of which, all status triggers in block 14 are reset (zeroing) (Fig. 3), the outputs of which are connected to the outputs 24, in addition to the trigger 80 status reconfiguration. The codes of these triggers, which are bits of a dynamic status code of timers (DCS SOV), are recorded in the internal register of switch 3 for transmission to the central processor for storage and analysis.

 In the control bit of the internal register of switch 3, a parity value code is written for the code at input 24 to control the reliability of the transmission of the DCSS code from the group of outputs 23 of the switch 3 to the central processor. Trigger 80 in block 14 is reset only at the moment of the appearance of signals> 3PBOV = 1 and> SPADR = 2, i.e. when the device ends recording mode. The signal> TSC at the output of node 58 is formed under the influence of signals> SI2-BOV,> SI4-BOV with the equality of address codes at input 41 and output 66. At output 66, the address code of the clock or comparator or processor timer is generated, depending on the operation code, installed at input 27, respectively, КЗЧ, КЧЧ or КЗК, КЧК or КЗТ, КЧТ. In the counting mode (when the zero code is set at input 27), the zero code is also set at the outputs 66 (Fig. 2). As a result, a zero code is set at the output of node 58. At the outputs 44, 45, 46, a combination of signals is established in which the switches 1, 2, 3 are disconnected from the inputs / outputs.

 At the same time, when the input of 27 codes КЗЧ, КЗК, КЗТ is set at the inputs / outputs 21, codes for the values of the clock, the comparator of the processor timer are transmitted from the central processor, and at the inputs / outputs 22 are set their parity codes. In block 5, after the appearance of the signal> TSP at the input of the node 58 and the sequential appearance of the signals> ADR1 and> ADR2 at the corresponding outputs of the node 59, the signals> SPADR1 and> SPADR2 appear in the corresponding sequence in the corresponding outputs. Under the action of a signal> E1 RAMD, at the discharge of input 40 and a code at input 27 of node 57 and a combination of clock signals at inputs 63, 64 of node 57 at outputs 44, 45, 46 of node 57 and block 5, signals are generated in the required sequence to record the codes set at the inputs / outputs 21, 22 to the internal register of switches 1, 2. However, only after the required combination of signals OPR,> UPR,> E2C4,> WRRAMD,> E1 RAMD appears at the outputs 39, 43, 40, providing rewriting of codes from the internal registers of the switches 1, 2 to counter 4 and register 10 onwards to memory blocks 7 , 8, under the action of the signal> SPADR2 at the input of node 57, output 26 displays a signal (logical unit) of the end of the external exchange operation. At the same time, the parity of the received codes is monitored using blocks 11, 12, 6. If an error occurs, an error code is generated at output 33. Signals (logical units)> ADR1,> ADR2 appear sequentially one after another for a time (120-130) ns each (in a time interval (> SI1-BOV -> SI6-BOV) with a frequency of (240-260) ns. Signals> SPADR1,> SPADR2 are identical to the signals, respectively> ADR1,> ADR2, but only appear when a signal> TSP appears at the output of node 58.

 The described mode of operation of the device is a recording mode (RE).

 When 27 codes of KCHCh, KChK, KChT are installed at the input, the device starts functioning in the reading mode, which differs from the counting mode (PC), set when the code at input 53 is zero, only in that during the action of the signal> SPADR1 at outputs 44, 45 , 46 of block 5, such a set of signals is formed that provides for writing codes read from blocks 7, 8 and from inputs 29, 24 to the internal register of switches 1, 2, 3 and issuing them to inputs / outputs 21, 22, 23 at the required moment time determined by the moment of occurrence of the pulse TI2-C2. Moreover, as in the reading mode, the signal (logical unit) at the output 26 appears under the action of the signal> SPADR2 at the time of the signal> TT4-C2. Logical zero at output 26 is set both in the recording mode and in the reading mode through (120-130) ns at the moments of the action of signals> TT4-C2, RTI2V. In read mode, a reset signal (logical unit) is also generated (> RESET) at the discharge bit of output 37 of block 5 (see Fig. 2), under the action of which, all status triggers in block 14 are reset (zeroing) (Fig. 3), the outputs of which are connected to the outputs 24, in addition to the trigger 80 status reconfiguration. The codes of these triggers, which are bits of a dynamic status code of timers (DCS SOV), are recorded in the internal register of switch 3 for transmission to the central processor for storage and analysis.

 In the control bit of the internal register of switch 3, a parity value code is written for the code at input 24 to control the reliability of the transmission of the DCSS code from the group of outputs 23 of the switch 3 to the central processor. Trigger 80 in block 14 is reset only at the moment of the appearance of signals> 3PBOV = 1 and> SPADR = 2, i.e. when the device ends recording mode. The signal> TSC at the output of node 58 is formed under the influence of signals> SI2-BOV,> SI4-BOV with the equality of address codes at input 41 and output 66. At output 66, the address code of the clock or comparator or processor timer is generated, depending on the operation code, installed at input 27, respectively, КЗЧ, КЧЧ or КЗК, КЧК or КЗТ, КЧТ. In the counting mode (when the zero code is set at input 27), the zero code is also set at the outputs 66 (Fig. 2). As a result, a zero code is set at the output of node 58. At the outputs 44, 45, 46, a combination of signals is established in which the switches 1, 2, 3 are disconnected from the inputs / outputs.

 With each occurrence of a signal (logical unit)> GI at input 49, a sequence of ADR1 and> ADR2 signals starts to be generated, and at output 41 a clock address code (> RCF), a comparator address code (> RCM), and a processor timer address code (> RTP). Each new code at the output 41 is held during the action of the signals> ADR1 and> ADR2. The appearance of the signal> RKM2 (> RFCh2,> RTP2) on the corresponding bit of output 37 coincides in time with the appearance of the signal> ADR2 and setting the code of the comparator address (hours, processor timer) at output 41.

 Signals> RKM2,> RTP2,> RFCh2 control the fixation of the overflow (transfer) signal from the input 34T of block 14 separately for the comparator, processor timer, hours. Additionally, the identification of the recording, reading and counting modes of the device in block 14 is carried out using signals> SPADR2,> 3PBOV in the input bits 37.

 In counting mode (PC) (as well as reading) during the action of the signal> ADR1, codes from blocks 7, 8 are read and written to counter 4 and register 10 under the action of signals> SI3-BOV,> SI4-BOV due to the setting the corresponding combination of control signals at inputs 39, 40, 43. A control code is generated at the outputs 36, which is compared with a control code from the outputs of the register 10. An error signal (if any) is generated at the output 33. During the action of the signal> ADR2, the modification ( account) of the codes stored in counter 4 and recording in p Trunk 10 predicted control code from input signals 35 by the action> Cu3-CWA> SI4-CWA by installing at the inputs 39, 43 corresponding to the signal constellation. Using blocks 6, 12, the correctness of the code modification is monitored with the formation of the corresponding signal at the output 33. Possible overflow signals (logical unit of transfer from the high order of the code modified in counter 4) from output 34 are fixed in block 14 under the action of signals> SI3-BOV,> SI4-BOV (triggers 67, 68, 69 (Fig. 3) when modifying the codes respectively hours, comparator, processor timer). At the corresponding outputs 24 and output 25, a signal is formed - a logical unit.

 If the transfer signal> PO (second transfer signal) when modifying the code of the clock, comparator, processor timer appears at the moment when the previous transfer signal (first transfer signal) that occurred when the code of the clock, comparator, processor timer and in the trigger, respectively, 67, 68, 69, then through the elements 78, 79 (Fig. 3) the trigger 80 is set to a single state under the action of the signals> SI3-BOV,> SI4-BOV. On bits 90 and 89 of output 19 and output 24 are set logical units. The device goes into reconfiguration mode (RRK). At the moment of the action of the closest (in time) signal> PKM1 = 1, a logical zero is generated at the output 17 (Fig. 4), under the action of which, instead of the comparator code, a zero code is set in counter 4. In parallel, the trigger 93 is set to a single value (Fig. 4), due to which, in the reconfiguration mode, the formation of a logical zero at the output 17 is prevented. In addition, the second transfer signal that occurred during the modification of the clock code (from the clock) is fixed in the trigger 80 of the block 14 he, as well as all subsequent transfer signals from the clock in reconfiguration mode are recorded in the trigger 94 of the node 13 (Fig. 4). As a result, at the time of modifying the code, which in other modes represented the comparator code, the number of transfers from the clock will be calculated, since output 18 sets the unit for the duration of the signals> PKM1 = 1 and> PKM2 = 1.

 At the moment the signal RTP = 0 appears (at the input bit 20), the trigger 94 of node 13 is reset (zeroed) and, at the moment of the subsequent signal> RFP2 = 1, the subsequent transfer signal from the clock can again be recorded in trigger 94, which is added to the already calculated number of signals hyphenation, the code of which is modified in the counter 4 at the time of the signal> PKM2 = 1. Since the trigger 94 is reset already at the moment of the signal> RTP1 = 1, by the time of the signal> RTP2 = 1, logical units are set at all inputs of the element 91 of node 13 and, therefore, logic zero is set at the output 18 of node 13. As a result, the timer code recorded in counter 4 will not be modified and will be written back to memory block 7 without changes, and its control bits without changes will be written to memory block 8. This is because when output 18 is set to logic zero counter 4 goes into storage mode, and in block 12, the control code from outputs 36 is transmitted to outputs 35 (see Fig. 5). In this case, in block 11, the formation of the transfer signal is blocked (see Fig. 5). Only when the external exchange-write operation is set in the device for a new clock, comparator or processor timer at the moment of simultaneous operation of signals> 3PBOV = 1 and> SPADR2 = 1 in block 14 and node 13, triggers 80, 93, 94 are reset and the device goes to account mode. In this case, at bits 89, 90 of output 19 and output 24, logical zeros are set. The outputs 17, 18 of the node 13 are constantly set logical units.

 In all cases, according to the signal at output 25, the central processor “sets” the reading mode at the address of the clock in the device by setting the KPH code at input 27. In parallel, the status code of the device DCSS is read through inputs 24 and 23.

 We show that using the proposed device through the use of the reconfiguration node with connections, a solution is provided in the computer processor for all the tasks solved by the prototype.

 The proposed device is intended for the implementation of timers (SOW) in the Central processor (CPU) in the following way.

 In accordance with the principles of functioning of modern computers, for example, the well-known EU computer, using the prototype in the processor, the following time counters are organized (not counting the interval timer): hours (ES), comparator (CM), processor timer (TP), the value of each of which appears to be 52-bit binary. In the process of operation (functioning) of time counters, the unit is added to the lowest (51st digit of the clock code every microsecond (thus, counting (modification of the clock) is performed)), the value of the comparator is compared to the modified clock value every microsecond, and from the younger (51st a unit of the processor timer code is subtracted every microsecond, and at the moment when the value of the comparator becomes less than the clock or the sign (zero) of the processor timer is reversed (becomes I am equal to a logical one), the processor is formed on the external interrupt request from the comparator or of the processor clock. Means timing are treated as external devices to the processor.

 At the same time, the operation of the clock should not be influenced by such states, processor operating modes, and procedures performed in the processor as: “wait” / “count”, “task” / “supervisor”, “stop” / “work”, “command operation "," push operation "," control "mode," reset "of the processor," initial reset "," software reset "," initial software reset "," reset with cleaning "," initial load ".

 The clock should be set to zero after a “power-on reset”.

 The value of the comparator should be maintained under such conditions, processor operating modes and procedures performed in the processor as: “wait” / “count”, “task” / “supervisor”, “stop” / “work”, “command operation”, “ contact work "," control mode "," reset "of the processor," software reset "," boot ".

 The value of the comparator should become zero and a request for an external interrupt from the comparator should be formed in the processor after the "initial reset" of the processor, the "initial software reset", "reset with cleaning", "reset at power-up".

 The processor timer value should be saved and the processor timer should decrease under such conditions, processor operating modes and procedures performed in the processor as: “wait” / “count”, “task” / “supervisor”, “work” (including when executing a command in the process of team work), "processor reset", "software reset", "boot".

 The processor timer value must be maintained and the processor timer must not decrease when the processor stops. The processor timer value should become zero during the "initial reset" of the processor, "initial software reset", "reset with cleaning", "reset at power-up".

 After performing such procedures in the processor as “resetting” the processor, “soft reset”, “initial reset”, “initial soft reset”, “reset with cleaning”, the processor switches to the “stop” state from which it is output by the operator or by a signal from another processor.

 In the "stop" or in the "boot" mode, the processor may be an indefinite time interval greater than 1 s. In this case, the clock should continuously count down the time without loss of accuracy, and the comparator value should be compared with the clock value with the formation of the corresponding requests to the processor for an external interrupt. The processor timer should count down the time interval during the execution of the processor “reset”, “soft reset”, “boot” procedures until the processor stops, at which the processor timer should stop. When performing procedures such as “initial reset”, “initial software reset”, “reset with cleaning”, “reset at power-up”, the timer value of the processor and comparator is set to zero and remains the same after setting the processor's “stop” state. When performing the “reset on power-up” procedure, the clock value is set to zero, however, immediately after the reset, the clock should begin to count down. In all cases, the count in hours and processor timer should be carried out at the same speed.

 Using the proposed device, only 20 (in bits 32/51) low-order bits of all time counters are counted. The senior 32 bits (bits 0/31) of all time counters (including hours) are stored in the cells of the local (LP) or in the working area of the main (operational) processor memory and the count in them (when a transfer occurs from the 32nd discharge) is carried out by means of the processor.

 At the same time, it is not obvious how to ensure the safety of the countdown and the accuracy of the countdown by hours and time intervals by the processor timer when setting the processor “stop” state and when performing the “boot” procedures (for a period of time greater than 1 s)? For this reason, in well-known analogues, the watch is built on a 52-bit hardware counter, which requires large hardware costs (in the TEZs).

 The proposed device provides additional special hardware (reconfiguration node with appropriate connections) that are absent in all analogues, with which it is possible to maintain the reference and accuracy of the clock and time intervals by the processor timer and, therefore, it is possible to organize the account by hardware only at 20 discharges of all time reference devices, which in turn leads to a reduction in hardware costs (by two FCs compared to the prototype). The cost of additional resources (cells, which are usually available in reserve) of the local or main processor memory are cheaper than additional hardware costs.

 Just as in the prototype for using the proposed device in the local memory (LP) or in the working area of the main (operational) memory (OP) of the CPU, the area of time counters (OSO) is allocated, consisting of a cell (КС52) for storing 52-bit static code (SKK52) comparator, cell (TD32) for storing 32 high order bits of the dynamic code (DKT32) of the processor timer, cell (TD20) for storing 20 low order bits of the dynamic code DKT20 of the processor timer for the time the processor stops, cell (YaS8) for storing static code with standing (SKS8) timing means. In addition to the indicated cells in the OSOV, it is necessary to select a cell (KD32) for storing 32 high-order bits of the dynamic code (DKK32) of the comparator, a cell (ChS32) for storing the 32 high-order bits of the clock (KChS32), a cell (ChS20) for storing code 20 -the lowest bits of the clock (CoES20).

 The reset procedures in the processor do not provide for resetting all cells in the OSOV area, but setting the required values in accordance with the principles described above. So, when performing the “reset on power-up” procedure, zero codes are entered in all cells of the OSOV area, except for the JC cell in the interrupt request bit from the comparator, the value of which is set to a logical unit (meaning that there is an external interrupt request from the comparator). The procedure "reset with cleaning", "initial reset of the processor", "initial soft reset" in all cells of the OSOV area, except for cells ChS32, YaS8, zero codes are entered. Cell ЧС32 remains unchanged. In cell ЯС8, in the bit of the interrupt request from the comparator, a logical unit is set.

 The processor reset and software reset procedure does not provide for changing the state of the cells in the OSOV area.

+1
Если указанная разность отрицательна, то сразу формируется запрос на внешнее прерывание в процессор от компаратора, т.е. устанавливается логическая единица в соответствующий бит кода СКС8. Старшие 32 разряда кода ДКК52 представляют собой код ДКК32, который хранится в ячейке КД32 и модифицируется средствами процессора. Младшие 20 разрядов кода ДКК52 представляют собой код КД20, который хранится в памяти устройства и модифицируется в счетчике устройства.The dynamic code of the comparator (DCC52) is (as in the prototype) a 52-bit additional code from the code obtained by subtracting the value of the static code of the comparator (CCC52) from the value (code) of the clock (CSC52), if the resulting difference is positive
DKK52 =

+1
If the indicated difference is negative, then a request is immediately generated for an external interrupt to the processor from the comparator, i.e. the logical unit is set to the corresponding bit of the SCS8 code. The senior 32 bits of the DKK52 code are the DKK32 code, which is stored in the KD32 cell and modified by means of the processor. The lower 20 bits of the DKK52 code are the KD20 code, which is stored in the device memory and modified in the device counter.

+1
Старшие 32 разряда кода ДКТ52 представляют собой код ДКТ32, который хранится в ячейке ТД32 и модифицируется средствами процессора. Младшие 20 разрядов кода ДКТ20 представляют собой код ДКТ20, который хранится в памяти устройства и модифицируется в счетчике устройства.The dynamic processor timer code (DKT52) is (as in the prototype) an additional code from the SKT52 static code, which is set in the command to set a new processor timer value
DKT52 =

+1
The senior 32 bits of the DKT52 code are the DKT32 code, which is stored in the TD32 cell and is modified by the processor. The lower 20 bits of the DKT20 code are the DKT20 code, which is stored in the device memory and modified in the device counter.

 When using the proposed device, it is envisaged to modify (count) the codes КЧС52, ДКК52, ДКТК by adding the codes КЧС20, ДКК20, ДКТ20 in the device to the least significant digit each microsecond. At the same time, when the indicated codes are transferred from the high-order bit, the device fixes in the dynamic status code of the time counters (DSSS) stored in the device status block overflow signals, the appearance of which causes the formation of requests for a firmware interrupt in the processor. When processing these requests, the DKSSOV is transmitted and analyzed from the device to the processor, and all the DKSSOV bits in the device are reset. According to the results of the analysis of DKSOV in the processor, the resulting transfer (logical unit) is added to the low order of the corresponding code KCHS32, DKK32, DKT32 (i.e., the codes KCHS32, DKK32, DKT32 are modified when the transfer from the high order of the codes KChS20, DKK20, DKT20 appears ) At the same time, when modifying the DKK32, DKT32 codes, overflow signals are recorded (by setting a logical unit in the corresponding SCS8 bits), the appearance of which means the generation of external interrupt requests to the processor from the comparator and processor timer, respectively. External interrupt processing is carried out in accordance with the priorities provided by well-known principles. After processing an external interrupt from the comparator or processor timer, a logical zero is set in the corresponding bit of the SCS8 code.

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При выполнении в процессоре команды "установка нового значения часов" соответствующим образом обновляется содержимое ячейки ЧС32. Младшие разряды (20) разрядов кода нового значения часов записываются в соответствующую ячейку памяти устройства.When the processor reads the comparator value, the comparator value is read from cell KC52. When the processor reads the clock value or reads the timer value of the processor, the 20 least significant bits of the KCHS52 or DKT52 code are read from the device memory (i.e., the codes KChS20 or DKT20 are read) and the 32 most significant bits of the codes KChS52 or DKT52 from cells ЧС32 or ТД32 (i.e. codes КЧС32 or ДКТ32 are read). Then, the processor glues together the 20 lower and 32 senior bits of the code KCHS52 or DKT52 in a 52-bit code. For the code DKT52 carry out the conversion
SKT52 =

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When the "set a new clock value" command is executed in the processor, the contents of cell CS32 are updated accordingly. The least significant bits (20) of the code bits of the new clock value are recorded in the corresponding memory location of the device.

 When the command "set a new value of the comparator" or the command "set a new value of the timer of the processor" is executed in the processor, a new value of code SKK52 is recorded in cell KC52, codes DKK52 and DKT52 are calculated according to the algorithm described above. The least significant bits (20) of the bits of the codes DKK52 DKT52, i.e. DKK20 and DKT20 codes are recorded in the corresponding memory cells of the device, and the most significant bits (32) of the discharge) are recorded in the cells KD32 and TD32 of the OSOV area.

 Before processor stops, set either from the operator’s console, or during errors and failures, or after performing reset procedures, or in the process of command operation (microprogram, as well as before the “initial boot” procedure, the 20 least significant bits of the processor timer are read (DKT20 code ) and hours (code КЧС20) from the device’s memory and writing them to the TD20 and ЧС20 cells of the OSOV area, respectively. When the processor starts up again from the “stop” state, the code from the TD20 cell of the OSOV area (firmware) is written to the corresponding device memory After that, the DKT20 code is read from the device’s memory together with the dynamic status code of the timers (DKSSOV), and if the transfer signal from the high-order bit of the DKT20 is recorded in the DKSSOV code, it is ignored, thus stopping the processor timer at the moment processor shutdown and start the processor timer when the processor starts.Pre-memorization of the code КЧС20 in the cell ЧС20 is necessary to restore the processor timer after the "boot" procedure, which will be described ilk.

When performing the "initial boot" procedure, which can take place for a time longer than 1 s, and also due to the fact that the processor may be in a state of performing reset and subsequent shutdown procedures for a time longer than 1 s, as well as in connection with processor stops, set from the operator’s console or by command from another processor for a time longer than 1 s, it is not possible in the processor to timely (within 1 s - counting time 2 ²⁰ μs) modify the codes КЧС32, ДКК32, ДКТ32 (since for 1 c ends at 20- the lowest bits of hours). For this reason, until now, in universal computers, clocks (all 52 bits) were implemented in hardware (in the form of a 52-bit counter) and independently of the processor, which was justified by the need to maintain the count and accuracy of the clock count (i.e., to prevent the loss of counting time during shutdowns processor and during the execution of the processor procedures “bootstrap.” As a result, to build a means of counting time required a lot of hardware.

To prevent the loss of time reference in these cases, the proposed device provides special hardware with which the hardware implementation of only 20 low-order bits of the codes of the clocks, the comparator, the processor timer ensures the saving (i.e., the loss of) the countdown of all timers , including hours when the processor stops or when performing bootstrapping procedures for any period of time up to 2 ²⁰ s. This allows you to significantly reduce the hardware cost of constructing time counters by using the reserve resources of the processor memory (two 52-bit memory cells).

 Prevention of the loss of countdown by hours and time intervals by the processor timer during bootstrapping, resetting and shutdowns in the processor is achieved by fixing the device status (reconfiguration state) when the appearance of the subsequent transfer signal from 32 bits separately by any means (hours, comparator, processor timer) (i.e., the transfer signal from the zero discharge separately of any of the codes КЧС20, ДКК20, ДКТК20) occurred at the moment when the previous signal p was not yet reset (in the DCSS code in the device) transfer from the 32nd bit of the same tool (which means that for 1 second the processor was unable to “service” the device and, therefore, it (the processor) is either in the “stop” state or the boot procedure is being performed in it). In this case, the reconfiguration (using the reconfiguration node) of the connections in the device is automatically performed so that the low-order bits of the DKT20 code in the device are stopped and the current (formed) value of the DKT20 code in the device is saved without changes. The bits of the 20 least significant bits of the comparator (DKK20 code) in the device are reset, and instead of the least significant bits of the DKK20 code, the upper 20 bits (12/31 bits) of the clock (KCHS20R code) are generated by counting the transfer signals from the zero bit of the KChCh20 code that appear during the process modifications of the code КЧС20. In this case, the corresponding reconfiguration bit in the DKSSOV status code is set equal to a logical unit, under the action of which a request (signal) is generated for a firmware interrupt for “servicing” the device. After the processor finishes the execution of the “boot” procedures or exits the “stop” state, the device status block is read from the corresponding register, transferred to the processor, and the DCSS code is analyzed. The presence of a logical unit in the DKSSOV code reconfiguration bit means that the time reference means (clock, comparator, processor timer) must be restored. To do this, the processor “reads” the code КЧС20 from the corresponding memory cell of the device and the code КЧС20Р from the memory cell of the device in which the DCC20 code was previously stored. The code КЧС20Р and the read code КЧС20 are glued into the code КЧС40 and recorded for temporary storage in the DKK52 OSOV cell. Further, a zero code is recorded in the memory cell of the device in which the DCC20 (KCHS20R) code is stored. The device reconfiguration state is reset. Further, if the restoration of the time counters is carried out after the “boot-up” procedure is performed, then the value of the code КЧС20 stored in the cell КЧС20 of the OSOV area is subtracted from the value of the code КЧС40 and the code of the received difference is added to the code ДКТ52, read from the cells ТД32 and ТД20 ОСОВ. If in this case a transfer occurs from the zero bit of DKT52, then a request is generated (by setting the logical unit in the corresponding bit (bit) of SKS8 code) for an external interrupt from the processor timer. If the transfer from the zero bit of DKT52 does not occur, then the 20 least significant bits of the DKT52 code are recorded in the corresponding memory location of the device as the DKT20 code, and the 32 high-order bits of the DKT52 code are recorded in the TD32 cell as the DKT32 code. Thus, the processor timer is restored after the boot procedure in the processor.

 To restore the clock, the code КЧС20Р is added to the code КЧС32 from the cell ЧС32 and the received code of the sum is recorded in the cell ЧС32. Thus, the clock is restored, since the code КЧС20 continues to be modified in the device.

 The value of the DKT20 code after the “stop” state of the processor is restored (as described) due to the use of the TD20 OSOV cell, in which the DKT20 code is entered before the processor stops. Using the recovered code for the clock value and the saved code KCHC52, the DKK52 code (and, therefore, the DKK32 and DKK20 codes) is re-generated as described above.

 Thus, using the proposed device provides a solution in the computer processor of all the tasks solved by the prototype. At the same time, in the proposed device, instead of the 52-bit first bi-directional switch, counter and memory block of information bits, only 20-bit first bi-directional switch, counter and memory block of information bits are used, thereby reducing hardware costs by two TEZs. Therefore, the goal is achieved - reducing hardware costs.

Claims (1)

 DEVICE FOR TIME COUNTING, comprising first and second bi-directional switches, counter, control unit, comparison unit, information bit memory unit, control bit memory unit, first and second switches, register, carry prediction unit, byte parity predictor, status signal generating unit , a convolution element modulo two, an OR element, wherein the group of address inputs of the memory block of the control bits is connected to the group of address inputs of the memory block of the information bits and to the group of outputs in the control unit, the start-up input of which is the start-up input of the device, the input of the external exchange operation task is connected to the input of the external exchange operation task input, the group of inputs of the initial conditions setting of which is the group of inputs of the initial conditions of the device, the first clock input of the control unit is the first clock the input of the device, the input of the overflow fixation of the state signal generation unit is connected to the overflow output of the carry prediction unit, the group of outputs of which connected to the first group of inputs of the byte parity prediction block, the second group of inputs of which, the group of information inputs of the hyphenation block, the group of information inputs of the memory block of information bits are connected to the group of bit outputs of the counter, the write control inputs for reading the memory block of information bits and the memory block of control bits connected to the first output of the control unit, the group of outputs of the first switch is connected to the group of information inputs of the register, and the second group of inf the input inputs of the first switch are connected to the first group of outputs of the byte parity prediction block, the second group of outputs of which is connected to the first group of inputs of the comparison unit, the second group of inputs of which is connected to the group of bit outputs of the register and the group of information inputs of the control bit memory block, the output group of which is connected with the first group of information inputs of the first switch and with the first group of information inputs / outputs of the second bi-directional switch, the first group of inf The input / output of the first bi-directional switch is connected to the group of outputs of the information bit memory block and to the group of information inputs of the counter, the account resolution input of which is connected to the second output of the control unit, the third output of which is connected to the control inputs of the first, second bi-directional switches and second switch, inputs control information transfer of the first and second bi-directional switches connected to the fourth output of the control unit, the fifth output of which is connected the information transfer control input of the second switch, the second group of information inputs / outputs of the first bi-directional switch is a group of inputs / outputs for setting the device time, the second group of information inputs / outputs of the second bi-directional switch is a group of inputs / outputs of the device parity control codes, the group of information outputs and the discharge output the parity of the second switch are a group of outputs of the status signals and the output of the sign of the parity of the device, the device error output is connected to the output of the comparison unit, and the group of status outputs of the status signal generation unit is connected to the corresponding inputs of the convolution element modulo two, the OR element and to the information inputs of the second switch, the input of the parity bit of which is connected to the output of the convolution element modulo two, the output of the OR element is connected to the output of the device request, the output of the end of the external exchange operation of which is connected to the sixth output of the control unit, the seventh output of which is connected to the control the input of the status signal generating unit, the clock inputs of the status signal generating unit, the first and second bi-directional switches, the second switch, counter, register and the second clock input of the control unit are connected to the second clock input of the device, the eighth output of the control unit is connected to the control input of the first switch, the fact that, in order to reduce hardware costs, the device contains a reconfiguration node, moreover, a group of control outputs of the unit for generating status signals of the connection it is connected with a group of inputs for setting the initial conditions of the reconfiguration node, the first output of which is connected to the reset input of the counter, the counting input of which is connected to the control inputs of the carry prediction unit and the byte parity prediction block and with the second output of the reconfiguration node, the group of mode setting inputs of which is connected to the ninth output of the control unit, the output of the transfer prediction unit is connected to the input of the mode setting of the reconfiguration unit, the clock input of which is connected to the second clock input of the device, the reconfiguration unit The guration contains two triggers, five AND elements - NOT, the first input of setting the initial conditions of the reconfiguration node connected to the first inputs of the first and second elements AND - NOT, the second input of the initial conditions of the reconfiguration node connected to the first inputs of the third and fourth elements AND - NOT, the inputs from the first to fifth groups of inputs of the job mode of the reconfiguration node are connected respectively to the second input of the first element AND - NOT, the first and second inputs of the fifth element AND - NOT, the second inputs of the third and fourth elements AND - E, the inverse outputs of the first and second elements AND are NOT the first and second outputs of the reconfiguration node, the direct output of the first element AND is NOT connected to the information input of the first trigger, the input of which is set to “0” and connected to the third input of the third element AND is NOT and connected to the inverse output of the fifth element AND - NOT, the direct outputs of the third and fourth elements AND - NOT connected respectively to the input of the set to "0" and the gate input of the second trigger, the inverse outputs of the fourth element AND - NOT and the second trigger connected respectively, with the second and third inputs of the second AND element - NOT, the input of the mode setting of the reconfiguration node is connected to the information input of the second trigger, the sync inputs of the first and second triggers are connected to the clock input of the reconfiguration node, the inverse output of the first trigger is connected to the third input of the first element And - NOT, and gate input of the first trigger.

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