RU2023293C1 - Multichannel equipment to connect users to common main line - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: this equipment is designed for multimachine computer systems and local computer networks for control over access to common line. Equipment has channels each composed of counters 1, 2, multiplexers 3,4, comparison circuit 5, flip-flops 6-9, AND gates 10,11, OR gates 12. 13, register 14. Main feature of invention lies in following procedure: if priority code of user coincides with code of its ordinal number and generation of priority code into main line starts from the more significant digit then each following digit of priority code can be sent into main line in the course of shorter time than the preceding one. EFFECT: enhanced productivity of equipment thanks to reduction of time spent on arbitration of requirements. 1 dwg

Description

 The invention relates to computer technology and can be used in multi-machine computing systems and local area networks to control access to a common highway.

 A device for connecting information sources to a common highway, containing two counters, two triggers, elements AND, OR, NOT, trunk amplifiers and register. However, the device does not have sufficient reliability, since it implements a synchronous procedure for the transfer of authority [1].

 The closest in technical essence to the proposed one is a device for connecting subscribers to a common trunk, containing N identical channels, each of which contains the first and second counters, the first multiplexer, the comparison circuit, the first and fourth triggers, the first, second elements And, the first, second OR elements, with the first input of the third trigger connected to the first control input of the device, the second control input of the device connected to the second input of the third trigger, with the third input of the second trigger, with the first the input of the second OR element, the second input of which is with the first output of the first counter, with the second input of the second trigger, the first input of which is with the first output of the first trigger with the first input of the first OR element, with the first input of the second AND element, the second input of which is with the output the first multiplexer, with the first input of the comparison circuit, the second input of which is with the output of the second AND element, with the data highway, the busy line of the highway is connected to the output of the first OR element, with the second input of the first counter, with the first input of the first ele And, the second input of which is with the output of the third trigger, the output is with the first input of the first trigger, the second input of which is with the output of the fourth trigger, with the first input of the first counter, the second output of which is with the first input of the first multiplexer, l of the second inputs of which with l register outputs, the output of the comparison circuit is connected to the third input of the first trigger, the fourth input of which is with the output of the second OR element, the second output is with the second input of the second counter, with the second input of the fourth trigger, the first input of which is with the W th counter, the second latch output to the second input of the first OR gate, to the control output of the apparatus [2].

 The disadvantage of a device that implements a decentralized code control system for access to the trunk, which allows building high reliability systems, is the high time required to arbitrate the channel requirements, where each bit of the priority code is issued by subscribers to the trunk during the doubled time of signal propagation along the trunk.

 The aim of the invention is to increase the productivity of the device by reducing the time spent on arbitration requirements.

 The goal is achieved in that, in a multi-channel device for connecting subscribers to a common trunk, containing N (N is the number of subscribers) channels, each of which contains two counters, the first multiplexer, a comparison circuit, four triggers, two AND elements, two OR elements, moreover, in each channel, the S-input of the first trigger is connected to the device request input, the device reset input is connected by the R-inputs of the first and second triggers and to the first input of the first OR element, the second input of which is connected to the overflow output of the first counter and C-input the house of the second trigger, the D-input of which is connected to the direct output of the third trigger and with the first inputs of the second OR element and the first "AND" element, the second input of which is connected to the output of the first multiplexer and the first input of the comparison circuit, the second input of which is connected to the output of the first element And with the device data highway, the bus occupancy of the device highway is connected to the output of the second element And, with the input of the initial installation of the first counter and with the first input of the second element And, the second input of which is connected to the direct output m of the first trigger, and the output is with the C-input of the third trigger, the C-input of which is connected to the direct output of the fourth trigger and with the counting input of the first counter, the group of direct bit outputs of which is connected to the group of address inputs of the first multiplexer, the group of information inputs of which are connected to a group of register outputs, the output of the comparison circuit is connected to the D-input of the third trigger, the R-input of which is connected to the output of the first OR element, the inverse output of the third trigger is connected to the reset input of the second counter and the input of the fourth trigger, the counting input of which is connected to the overflow output of the second counter, the direct output of the second trigger is connected to the second input of the second OR element and to the confirmation output of the device channel, a second multiplexer is added to each channel, the group of information inputs of which are connected to the group of clock inputs devices, the group of address inputs of the second multiplexer is connected to the group of inverse bit outputs of the first counter, and the output is connected to the counting input of the second counter.

 Distinctive features of the device make it possible to implement the following feature of the decentralized code control (DCU) procedure: - if the subscriber’s priority code matches the sequence number code and the priority code is sent to the trunk from the highest level, then each subsequent bit of the priority code can be issued to the trunk for less time than the previous one, which improves the performance of the device.

 The drawing shows a functional diagram of the device.

 The device channel contains counters 1, 2; multiplexers 3, 4; comparison scheme 5; triggers 6, 7, 8, 9; elements And 10, 11; elements OR 12, 13; register 14; request input 15 channel; channel reset input 16; clock input 17 channels; tires 18, 19 of the common highway; output 20 channel confirmation.

 The device operates as follows.

 The request for the capture of the highway, the subscriber enters the trigger 8, giving a signal to the input 15 of the request.

 If the main trunk is unoccupied, when there is no busy signal on line 19, the counter 1 is initialized. If there is “1” in trigger 8, the entry “1” in trigger 6 occurs when the common trunk 19 is released. When “1” is written to trigger 6, though if one channel through the element OR 12 on line 19 is issued a busy signal. Subscribers requiring the capture of the trunk during its busy, enter the requests in the trigger 7, but the rewriting of "1" in the triggers 6 occurs only after the release of the common trunk (removal of the busy signal from line 19). In the zero state of the trigger 6, a signal is set to the input of the installation of the trigger 9, setting it to the zero state, the counter 2 is set on the same signal and its operation is blocked in the counting mode. When installing counter 2, a number can be written into it, at which, in the case of the first pulse entering the input and "1" in trigger 6, a pulse is generated at the transfer output of counter 2. The transfer signal from the output of counter 2 goes to the counting input of trigger 9. To unlock the counting mode of counter 2, “1” is entered in trigger 6. Unlocking the counting mode of the counter 2 is accompanied by the formation of the operating frequency used to organize the arbitration procedure at the output of the counting trigger 9.

 When the operating frequency arrives in all channels that have made requests for trunk capture, a serial connection starts through multiplexer 3 and the And element 11 of the bits of the priority register 4 and common line 18. Moreover, if at least one channel is contained in the discharge of register 4 connected to the line 18 "1", then the signal "1" is formed on line 18. The discharge connected to line 18 through multiplexer 3 is determined by the code supplied from the output of counter 1 to the address input of multiplexer 3. The increase in the contents of counter 1 occurs upon receipt of each new pulse from the output of trigger 9. On the comparison circuits 5, channels are switched that are switched to the line 18 bits of registers 4 of which are "0" in the presence of "1" on line 18.

 When "0" at the output of the comparison circuit 5 at the time of the trailing edge of the signal at the output of trigger 9, the trigger 6 of the corresponding channel is "zeroed". The output of trigger 9 is connected to the C-input of trigger 6, to the D-input of which the output of the comparison circuit is connected.

 When "1" at the output of the comparison circuit on the trailing edge of the signal from the output of the trigger 9, the state of the trigger 6 is saved. When the trigger 6 is “zeroed”, the counter mode of the counter 2 and the formation of the operating frequency at the output of the trigger 9 are blocked. Thus, after the “zeroing” of the trigger 6, its zero state is maintained until the beginning of the next arbitration procedure; when the trigger 6 is in the zero state, the output of the 11 bits of the register 4 of the corresponding channel to the common line 18 through the AND element is blocked.

 According to the transfer signal of counter 1, which is generated at the end of the cycle, all the bits of priority register 14 are output to the line, the contents of trigger 6 are rewritten into trigger 7. When "1" is written to trigger 7 through OR 12, the busy signal is set on line 19, previously set from trigger 6. Moreover, the described arbitration procedure ensures that “1” is written to trigger 7 of only one channel that has placed a request to capture the trunk and has the highest priority code in register 14 among all channels whose subscribers participated in the procedure arbitration. According to the counter transfer signal 1 with a delay on the element OR 13, the trigger 6 is “nullified” and the signals through the And 11 element are blocked from the output of the multiplexer 3 to line 18. When the trigger 6 is in the zero state, the output of the working frequency from the output of trigger 9 is blocked. the subscriber removes the trunk from the output 20. To release the common trunk after transmitting the data channel, the subscriber, by setting a signal to the input 16 of his channel, produces “zeroing” of triggers 6-8. When the trigger 7 is “zeroed”, the busy signal from line 19 is removed.

Claims (1)

 MULTI-CHANNEL DEVICE FOR CONNECTING SUBSCRIBERS TO THE GENERAL HIGHWAY, containing N (N-number of subscribers) channels, each of which contains two counters, the first multiplexer, a comparison circuit, four triggers, two AND elements, two OR elements, and each channel has an S-input the first trigger is connected to the device request input, the device reset input is connected to the R-inputs of the first and second triggers and to the first input of the first OR element, the second input of which is connected to the overflow output of the first counter and to the C-input of the second trigger, D-input which is connected to the direct output of the third trigger and to the first inputs of the second OR element and the first element And, the second input of which is connected to the output of the first multiplexer and to the first input of the comparison circuit, the second input of which is connected to the output of the first element And and to the device data highway, bus the busyness of the device’s trunk is connected to the output of the second OR element, with the initial installation of the first counter and with the first input of the second AND element, the second input of which is connected to the direct output of the first trigger, and the output is from C-in the third trigger, the C-input of which is connected to the direct output of the fourth trigger and to the counting input of the first counter, the group of direct bit outputs of which is connected to the group of address inputs of the first multiplexer, the group of information inputs of which is connected to the group of register outputs, the output of the comparison circuit is connected to D - the input of the third trigger, the R-input of which is connected to the output of the first OR element, the inverse output of the third trigger is connected to the reset input of the second counter and to the installation input of the fourth trigger, with whose even input is connected to the overflow output of the second counter, the direct output of the second trigger is connected to the second input of the second OR element and to the channel confirmation output of the device, characterized in that a second multiplexer is introduced into each channel, the group of information inputs of which is connected to the group of clock inputs of the device, the group of address inputs is with the group of inverse bits of the outputs of the first counter, and the output is with the counting input of the second counter.