RU2007875C1 - Automatic correlation meter of characteristics of pseudorandom phase-manipulated signal - Google Patents

Abstract

FIELD: electric communications. SUBSTANCE: device has seven multiplication units, delay gate, band-pass filter, non-linearity gate, four low-pass filters, tuning rate generator, two frequency meter, five gates, three pulse counters, signal base meter, sample duration meter, arithmetic unit, recording unit, phase shifter, two squarers, three adders, square-root calculation unit, threshold unit, two switches, two envelope detectors, three differentiating circuits, flip-flop, three AND gates, counting pulse surge generator, four dividers, amplifier, clipper, two registers, and NOT gate. EFFECT: increased functional capabilities by determination of law and rate of frequency change. 2 dwg

Description

 The invention relates to radio communications and can be used as a device for processing phase-manipulated (FM) signals in discrete information transmission systems, in combined communication systems and in radar, where pseudorandom FM signals with frequency modulation (FM) are widely used.

 The purpose of the invention is the expansion of functionality by defining laws and the rate of change of instantaneous frequency.

 In FIG. 1 shows a structural electrical diagram of the proposed device; in FIG. 2 - diagrams explaining his work.

 The device comprises a first multiplication unit 1, a delay element 2, a band-pass filter 3, a non-linear element 4, a first low-pass filter 5, a tuning speed generator 6, a second low-pass filter 7, a first frequency meter 8, a second frequency meter 9, and a second multiplication side 10 , the third low-pass filter 11, the first valve 12, the first pulse counter 13, the signal base meter 14, the parcel duration meter 15, the arithmetic block 16, the recording block 17, the phase shifter 18, the third multiplication block 19, the fourth low-pass filter 20, the first 21 and in the second 22 squares, the first adder 23, the square root block 24, the threshold block 25, the first key 26, the first envelope detector 27, the first differential circuit 28, the second valve 29, the trigger 30, the first element And 31, the generator 32 counting pulses, the second pulse counter 33, first divider 34, third multiplier 35, second divider 36, second key 37, second envelope detector 38, second differentiating circuit 39, third valve 40, amplifier 41, limiter 42, third differentiating circuit 43, fourth valve 44, fifth valve 45, the third counter 46 them pulses, the second element And 47, the third divider 48, the first register 49, the third element And 50, the second register 51, the fifth block of multiplication 52, the second adder 53, the element NOT 54, the sixth block of multiplication 55, the third adder 56, the fourth divider 57, seventh multiplication block 58.

 The device operates as follows.

The determination of the law of instantaneous frequency f _i (t) is carried out by measuring the period of high-frequency oscillations T _i (t) as f _i (t) = 1 / T _i (t).

To measure the period T _i (t) of high-frequency oscillations, the input signal (Fig. 2, a) is supplied to the amplifier 41 and the limiter 42. From the output of the limiter 42, the signal (Fig. 2, b) is supplied to the third differentiating circuit 43, at the output of which a sequence of positive and negative pulses (Fig. 2, c) corresponding to positive and negative half-periods of the signal. At the output of the unipolar fourth valve 44, only positive pulses are generated (Fig. 2, d), the repetition period of which is equal to the period T _i (t) of the high-frequency oscillations of the signal. These pulses are fed to the input of the third counter 46, setting it to "0", and to the second element And 47, allowing the contents of the third counter 46 to be transferred to the first register 49 and the third divider 48. Counting pulses from the generator output are received at the other input of the third counter 46 32. In the third counter 46, the value of T _{i is} determined in binary code. In the third divider 48, the law of variation of the instantaneous frequency f _i (t) = 1 / T _{i (} t) is calculated, which is recorded in block 17.

The law of the rate of change of the instantaneous frequency in the FM signal is determined by sequentially measuring two periods T _i (t) and T _i-1 (t) of high-frequency oscillations of the signal.

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В первом регистре 49 хранится в двоичном коде информация о величине T_i(t) (фиг. 2, е). Во втором регистре 51 хранится в двоичном коде информация о величине предыдущего периода Т_i-1(t) (фиг. 2, ж). Информация о T_i-1(t) переписывается во второй регистр 51 в момент действия отрицательных импульсов с выхода однополярного пятого вентиля 45 (фиг. 2, з). Далее в пятом блоке умножения 52 вычисляется величина T_i(t) ˙T_i-1(t), а во втором сумматоре 53 определяется величина суммы T_i(t) + T_i-1(t), которые поступают на входы шестого блока умножения 55. Информация с выхода шестого блока умножения 55 поступает на четвертый делитель 57. В четвертом делителе 57 вычисляется величина

, представляющая собой знаменатель указанной выше формулы.The speed γ _i (t) is determined from the relation
γ _i (t) =

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In the first register 49, information on the value of T _i (t) is stored in binary code (Fig. 2, e). In the second register 51, information about the value of the previous period T _i-1 (t) is stored in binary code (Fig. 2, g). Information about T _i-1 (t) is copied to the second register 51 at the time of the action of negative pulses from the output of the unipolar fifth gate 45 (Fig. 2, h). Then, in the fifth block of multiplication 52, the value T _i (t) ˙ T _i-1 (t) is calculated, and in the second adder 53, the value of the sum T _i (t) + T _i-1 (t), which are received at the inputs of the sixth block, is determined multiplication 55. Information from the output of the sixth multiplication unit 55 is fed to the fourth divider 57. In the fourth divider 57, the value is calculated

representing the denominator of the above formula.

On the third adder 56, the difference T _i (t) -T _i-1 (t) is calculated (Fig. 2, h), which is formed by adding the code T _i (t) from the output of the first register 49 and the reverse code T _i-1 (t) from the output of the element NOT 54. Next, in the seventh multiplication block 58, the quantity γ _i (t) is calculated in accordance with the above formula, which is recorded in block 17. (56) USSR Copyright Certificate No. 1543555, cl. H 04, 3/46, 1990.

Claims (1)

 AUTOCORRELATION MEASUREMENT PERFORMANCE MEASUREMENT PARAMETER OF PHASOMANIPULATED SIGNAL, comprising the first multiplication unit, a bandpass filter, a nonlinear element, a first low-pass filter (LPF), a first frequency meter, a parcel duration meter, a second multiplication unit and a second frequency meter, a serial meter connected to a second block, first key, first envelope detector, first differentiating circuit, first gate, trigger, first element And, first pulse counter, and n the first divider, the second key connected in series, the envelope detector, the differentiator circuit and the gate, the output of which is connected to the second trigger input, the third multiplication block, the second low-pass filter, the first quadrator, the first adder, the square root extractor, the third valve, and the second pulse counter , a signal base meter, an arithmetic unit and a second divider, a phase shifter connected in series, a fourth multiplication unit, a third low-pass filter and a second quadrator, the output of which is connected to the second input the first adder, as well as the delay element, the tuning speed generator, the fourth low-pass filter and the counting pulse generator, the output of which is connected to the second input of the first AND element, the input of the phase shifter, the first input of the second multiplication block, the input of the first multiplication block, the first input of the delay element and the first input the second key are interconnected and are the input of the device, the second input of the second key is connected to the output of the threshold block, the output of the nonlinear element through the fourth low-pass filter is connected to the output of the second frequency meter, the input which is connected to the second input of the first frequency meter connected to each other, the second input of the delay element and the input of the tuning speed generator, the output of the delay element is connected to the second inputs of the third and second multiplication units and the first key connected to each other, the second output of the second frequency meter is connected to the second input the first divider and the second input of the registration unit, the third input of which is connected to the interconnected output of the meter duration of the parcels and the second input of the arithmetic OK, the fourth input of the registration unit is connected to the interconnected output of the base signal meter and the second input of the second divider, the fifth input of the registration unit is connected to the output of the arithmetic unit, the sixth and seventh inputs of the registration unit are connected respectively to the output of the second divider and interconnected to the output of the first divider and the second input of the second multiplication unit, characterized in that, in order to expand the functionality by defining laws and measuring the instantaneous frequency, introduced serially connected amplifier, limiter, third differentiating circuit, fourth gate, third pulse counter, second element And, first register, fifth and sixth multiplication blocks, fourth divider and seventh multiplication block, serially connected fifth valve, third element And, second register, element NOT a second adder, the output of which is connected to the eighth input of the registration unit through the seventh multiplication unit, as well as a third adder and a fourth divider, the input of which is connected to the output of the second AND element, and the output - to the ninth input of the registration unit, the first and second inputs of the third adder are connected respectively to the interconnected first input of the fifth multiplication unit and the second input of the second adder and to the interconnected second input of the fifth multiplication unit and the output of the second register, the second output of the first register is connected to the second input of the third element And, the second input of the second element And is connected to the output of the fourth valve, the pulse input of the third pulse counter is connected to the output of the counter pulse generator, output the third differentiating circuit is connected to the input of the fifth gate, the input of the amplifier is connected to the output of the second key, the output of the third adder is connected to the second input of the sixth multiplication unit.

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