RU2003189C1 - Process of recording reproduction of information - Google Patents

Abstract

Usage: in instrumentation, in the construction of long-term storage devices on a movable medium. SUMMARY OF THE INVENTION: into a known method of recording-reproducing digital information, which consists in recording in parts of digital information, intermediate storing of the reproduced part of digital information, controlling it in parts, recording arrays of parts of digital information on a medium at the same time as storing them and intermittently playing back during which during intermediate memorization the control is carried out by bitwise comparison of the memorized part in the process of recording onto the medium, new operations consisting in the fact that for each mismatch of the reproduced information from the stored control signal, mismatch signals are generated, which, when summed and when the specified maximum permissible value is reached, N generate an alarm signal. the suitability of the controlled medium, and stop the further recording / reproducing process. The goal is to increase reliability. 2 s.p. f-ly. 1 ill.

Description

The invention relates to instrumentation and can be used in the construction of long-term storage devices on a movable medium.

Known methods of recording-reproduction (control of a magnetic recording apparatus), which include recording a code sequence on a moving magnetic medium, reproducing it from a magnetic medium, summing the reproduced pulses, and generating an error signal.

However, they do not provide sufficient reliability for recording-playback of real digital information.

Known methods for recording and reproducing digital information using correction codes, which are formed by adding a number of additional correction bits to information bits, storing information intermediate, generating information bits of the output code with automatic detection and correction of a certain number of errors.

The disadvantage of these methods is also not high enough reliability when recording and reproducing real digital information.

Known methods for recording-reproducing digital information in parts from several sources with control bits for clarity for each of its parts, which produce intermediate storage of the reproduced information and control it in parts, and if an error is detected, e of the controlled part replacement

 The disadvantage of these methods is also not high enough reliability when recording and reproducing real digital information.

The closest in technical essence and the achieved effect is the method of reproducing digital information, which consists in recording part of digital information, intermediate storing of the reproduced part of digital information, controlling its parts, recording arrays of parts of digital information on the media simultaneously with storing them and alternately with intermediate playback, during which during intermittent memorization, control is carried out by bitwise comparison with the memorized one Stu during recording on the medium.

The disadvantage of this method is the insufficiently high reliability, due to the fact that prior to use effective control of the quality of the media is not ensured.

The closest in technical essence and the achieved effect device for implementing the proposed method is the known device for recording and reproducing digital information described in the application for the invention.

A known device for recording and reproducing digital information contains

5 a mobile storage device, a digital information recording and reproducing unit coupled to the storage device, a buffer memory unit, the first, second and third AND elements, the first and second blocks

0 memory, reversible counter, digital information data comparator, address comparator, control unit, address register, trigger, signal selector, pulse shaper, shaper

5 clock pulses, a drive control unit, an input digital information bus, wherein the first, second and third outputs of the recording and reproducing unit are connected respectively to the first input of the second

0 element And, to the first input bus of the signal selector and to the input of the pulse shaper, the output of which is connected to the information input of the buffer memory unit, the digital information output bus in parallel code of which is connected to the second information inputs of the digital information data comparator, the digital input data bus connected to the input bus of digital information of the first memory unit and to the input bus of signal signals of the digital information of the control unit, the first, second and third outputs of control signals speed bus control signals

5 movements of the control unit carrier are connected respectively to the first, second, third input buses and to the input signal line of the digital code of the drive control unit, the command signal bus and the fourth output of the control signal of the control unit are connected respectively to the command signal bus and to the digital shift bus information in the registers of the first memory block, the fifth, sixth, seventh, eighth, fifth, tenth and eleventh outputs of the control signals of the control unit are connected respectively to the second input of the second element and And, to the first, to the second installation inputs of the trigger, to the second input of the first element And, to parallel

the connected installation inputs at 0m of the buffer memory block, the first, second memory blocks and the reverse counter, to the digital information shift signal bus in the registers of the second memory block, to the control input of the buffer memory block, the signal bus of the digital code of the control unit address is connected to the bus of the digital address code of the first address register, the information output bus of which is connected to the second bus of the digital address code of the address comparator, the first and second information inputs of the control unit are connected respectively o to the interconnected output of the clock generator and the counting input of the reverse counter and to the information output of the address comparator, the output of the second element And is connected to the digital information bus of the second memory unit, the information output bus of the reverse counter is connected to the first bus of the digital code of the address of the address comparator, bus output signals of digital information of the first memory unit is connected to a parallel-connected digital information bus from the communication line of the recording and playback unit digital information with a digital information bus from the communication line of the second memory unit, the digital information output signal bus of which is connected to the first input digital data input signal bus of the digital information data comparator, the first and second information outputs of the trigger are connected respectively to the parallel input of the direct account a reverse counter with a second input of the signal selector and to a parallel connected input of the countdown of the reverse counter with a third input of the signal selector, the output of the signal selector is connected to the input of the clock driver.

A disadvantage of the known digital information recording / reproducing device is also a lack of reliability due to the fact that effective media quality control is not preliminarily used before use.

An object of the invention is to increase reliability.

The drawing shows a structural diagram of a device for recording and reproducing digital information that implements the proposed method.

The device for recording and reproducing digital information comprises a storage device 1 on a mobile medium, a unit 2 for recording and reproducing digital information (paired with a storage device 1 on a mobile medium), a buffer memory unit 3, a first AND element 4, a second AND element 5, the third element And 6, block 7 of the first model memory with a limited volume, block 8 of the second model memory with a limited volume, a reverse counter 9, control unit 10, address comparator 11, address register 12, digital data comparator 13 information, trigger 14. selector 15 ignalov, generator 16 pulses, former 18 sinhroimpul

5 owls, drive control unit 18, pulse counter 19, signaling unit 20, input digital control information bus 21.

The input and output of the drive 1 on a mobile medium are connected to the digital information recording and playback unit 2, the first, second and third outputs of which are connected respectively to the first input of the And 5 element, to the first input bus

5 of the signal selector 15 and to the input of the pulse generator 16, the output of which is connected to the first input of the And 4 element, the output of which is connected to the information input of the buffer memory unit 3, the digital information output bus of which is connected in parallel to the second information inputs of the data comparator 13 digital information, the input digital information bus is connected to the digital information input bus5 of the first memory unit 7 and to the digital input signal input bus of the control unit 10, the first, second and third the outputs of the control signals and the bus of the control signals of the speed of movement by the carrier of the control unit 10 are connected respectively to the first, second, third input buses and to the input signal line of the digital code of the drive control unit 18, the command signal bus and the fourth control signal output of the control unit 10 connected respectively to the command signal bus and to the digital information shift bus in the registers of the first memory block 7, the fifth, sixth, seventh, eighth, ninth, tenth and eleventh outputs of the control signals ka 10 controls are connected respectively to the second input of the element And 5, to the first, to

5 to the second installation inputs of the trigger 14. to the second input of the And 4 element, to the parallel connected installation inputs to the O unit 3 of the buffer memory, the first memory unit 7, the second memory unit 8, the reverse counter 9 and the pulse meter 19, to the signal bus shift of digital information in the registers of the second memory block 8, to the control input of the buffer memory block 3, the signal bus of the digital code of the address of the control unit 10 is connected to the digital address bus of the address register 12, the information output bus of which is connected to the second digital bus of the address code of the address comparator 11, the first and second information inputs of the block 10 are connected by controls to the interconnected output of the clock generator 17 and the counting input of the reverse counter 9 and to the information output of the address comparator 11, the output of element 5 is connected to the bus digital information of the second memory unit 8, the bus of the information outputs of the reverse counter 9 is connected to the first bus of the digital code of the address of the address comparator 11. the bus of the output signals of digital information of the first of the memory unit 7 is connected to a parallel-connected digital information bus from the communication line of the recording and reproducing digital information unit 2 from the communication line of the second memory unit 8, the digital information output signal bus of which is connected to the first input the digital input data signal comparator 13 of the digital information data, the first and second information outputs of the trigger 14 are connected respectively to the parallel-connected input of the direct counting of the reverse counter 9 with the second input the signal selector 15 and to the parallel input of the countdown input of the reverse counter 9 with the third input of the signal selector 15, the output of the signal selector 15 is connected to the input of the clock generator 17, the counting input of the pulse counter 19 is connected to the output of the digital information comparator 13, the installation input is O and information outputs of counters of 19 pulses are connected respectively to the ninth output of the control unit to and to the corresponding inputs of the And 6 element, the output of which is connected to the input of the signaling unit 20 and to etemu input control unit 10.

A digital information recording / reproducing apparatus operates as follows.

First, the installation signal in O, coming from the ninth output of the control unit 10, prepares for operation the block 3 of the buffer memory, the reverse counter 9, the counter 19, and the blocks 7, 8 of the first and second model memory with a limited volume, respectively.

The recording and playback intermittent mode is set by signals from the first, second and third outputs of the control unit 10, respectively, supplied to the first, second and third inputs of the drive control unit 18. In this case, also, from the output bus of the digital code signals of the control unit 10, the corresponding signals of the digital code for controlling the speed of the carrier are transferred to the control inputs of the drive control unit 18, and from the seventh and eighth outputs of the control unit 10 are supplied to the first and second installation inputs of the trigger 14 and. respectively, to the inputs of the forward and backward counters of the reverse counter 9 and to the second and third input buses of the signal selector 15, control signals corresponding to the set mode. Digital input control information with tracking signals, set either from the communication line or from a special master. from the input bus 21 is supplied to the input of the block 7 of the first model memory with a limited volume. In this case, tracking signals are supplied to the input bus of the control unit 10. In the memory of the control unit 10, input digital information is being recorded at any given moment. If no cell in the memory of block 7 is filled, then the input digital information (in playback mode) is recorded in the first cell, the next in the second, etc., and in recording mode it passes to the output of block 7. At the initial moment of operation of the device recording mode is in progress. In this case, the input digital control information passes from the input bus 21 through the block 7 of the first model memory in transit (since no cell in the memory of the block 7 is filled) to the input of the recording and reproducing unit 2, from where it is recorded on the drive 1 and on the input of block 8 of the second exemplary memory with a limited volume, where the current digital information is recorded in the recording mode of the device. At the same time, in this mode, the counter clock 9 counts the clock pulses received at its counter input from a clock driver 17 of the clocks connected through the signal selector 15 to the output of the recording and reproducing unit 2. At the same time, the current address of the digital information part is reproduced at the information outputs of the reversible counter 9.

recorded in the drive 1 on a moving medium. Thus, in the recording mode, the input digital information is recorded on the medium and at the same time the same information is recorded in the block 8 of the second model memory with a limited volume. The recording mode is carried out until the equality of the address code from the reverse counter 9 to the address code set from the control unit 10 in the address register 12 is achieved. When the digital address codes from the outputs of the reversible counter 9 and the address register 12 match, the output of the address comparator 11 generates a signal supplied to the second information input of the control unit 10. In this case, the control unit 10 generates a corresponding reverse signal supplied to the corresponding control signal bus of the drive control unit 18, as a result of which the playback mode starts. In addition, from the control unit 10, an address code to which the playback mode is carried out is set in the address register 12. In this mode, the input control digital information is recorded in the block 7 of the first model memory with a limited volume and the information recorded in the drive 1 on a mobile medium is read out, intermediate parts are stored in the block 3 of the buffer memory and using the data comparator 13 digital information - bitwise comparison with identical information read from block 8 of the second model memory with a limited volume. If there is a mismatch at the output of the comparator 13 of the digital information data, signals are generated that are fed to the counting input of the counter T9, where they are added up until a certain predetermined code value is reached. In this case, the value of this code is set by correspondingly connecting the inputs of the And 6 element to the information outputs of the counter 19. In the digits where the input of the And 6 element is connected, the code value is 1, and where it is absent, O.

The playback mode is carried out until the code coincides with the information outputs of the reverse counter 9 with the code set from the control unit 10. At the same time, at the output of the address comparator 11, a signal 5 is generated which is supplied through the control unit 10 to the drive control unit 18. In addition, the control unit 10 sets an address code. In this case, the drive control unit 18 performs reverse and forced operation

0 to rewind the magnetic tape of drive 1 until the code coincides with the reverse counter 9 and the code set from the control unit 10. In this case, according to the signal from the address comparator 11, the control unit 10

5 generates a signal to the drive control unit 18, by which the forced mode of rewinding of the magnetic tape of the drive 1 is stopped and the next cycle of the normal recording of the input digital information to the drive 1 on a mobile medium begins. In this case, the control unit 10 sets the address to which this recording mode is to be carried out. When code equality is reached

5 of the address from the counter 9 and the address code set from the control unit 10, a signal is supplied to the control unit 10 at the output of the address comparator 11. And then similarly

0 described above with the only difference that the input digital control information is recorded in the drive 1 and the block 8 of the second model memory.

If during the recording-playback5, neither the number of non-control signals from the output of the digital information data comparator 13 reaches a predetermined value, then the output of the And 6 element generates an unsuitable media signal, which

0 is supplied to the input of the signaling unit 20 for visual indication and to the third input of the control unit 10. In this case, the control unit 10 generates a corresponding signal to the drive control unit 18, according to

5 to which the device is stopped.

(56) USSR Copyright Certificate No. 1324065, k. G 11 B 27/36. 1992. 0 Copyright certificate of the USSR No. 1721630, cl. G 11 B 27/36. 1992.

11200318912

Claims (2)

The claims of digital information are connected to digital information input bus first 1. A method for recording and reproducing an 8th memory unit; and a digital information signal input bus, which is accompanied by a digital 9th recording information in parts of digital information. 5 and the second and intermediate memorization of playback. The outputs of the control signals and the signal of the data part of the digital information, the control signals of the speed of its movement in parts, the recording of arrays of parts by the control unit 6 are connected to the digital information on the same the first second, third temporarily with their memorization and alternately input buses and to bus signals. but with intermediate reproduction, in SE LOVQ to b) the process of which, when the signals are com- mitted intermediate, the fourth commemoration is controlled by the output of the signal / | and the laziness of the block; bitwise comparison with the same name, respectively, are connected to the memorized part of the bus during recording on the command signals and the Shift bus, a digital medium, characterized in that in each information in the registers of the first block the moment of the mismatch of the signals is reproduced is the fifth sixth, eighth, information management with signals the eleventh and eleventh outputs of the registered memorized (control) control signals of the information control block01 generate information signals that are connected respectively to the second input For the maximum permissible value of the second element, and to the second, the second error and the current accumulation signal to the installation inputs of the trigger, the second error, compare these generated to the input of the first element AND, in parallel, the signals every time at the moment of occurrence of the single installation inputs in the O block of the current an error signal and at the moment of 25 buffer memory, the first, second blocks to achieve the equality of these signals of the form and the counting counter, an overflow signal is generated to the bus, at the time of the signal SD8I digital information arises the buttons of which stop the registers of the second memory block, the recording-playback control and the forming input of the buffer memory block sew the unsuitability of the medium. 30 on the signals of the digital code address block 2. The control recording / reproducing device is connected to a digital digital information bus, containing an address register address code, an informative bus on a movable medium, the memory output unit of which is connected to C and reproducing digitally the second address address code digital code bus, coupled to the drive, 35 a backup comparator, the first and second buffer memory in-block, the first, second information inputs of the control unit, the third AND elements, the first and second blocks are connected respectively to the memory connection, p Eversive counter, comparator between themselves the output of the digital data driver, the address of the clock pulses and the counting input of the re-comparator, control unit, register of the add-on counter and to the information counter, trigger, signal selector, formative output of the address comparator, pulse exciter output , the former of the element And is connected to the digital clock bus, the control unit for the drive information of the second memory unit, the house is the input digital information bus, the information output bus is reverse the second, third and third output counter are connected to the first bus of the recording and reproducing unit of the digitally-connected code of the address of the address are respectively connected to the first input of the second rotor, the output bus of the digital element And, the first input bus information of the first memory block the signal selector and the input are shaped and connected to parallel-connected l pulses, the output of which is connected to the digital information bus from the line sv - to the first input of the first AND element, the output of the recording and playback unit is connected is related to informational information with a digital input bus of the buffer memory block, the information output bus from the communication line of the second digital information block in parallel to the gg memory, the output signal bus of which digital code is connected to the second information of which is connected to information inputs the comparator, the first input bus of the input signals of digital information data, the bus input-digital information of the comparator of digital information, the first and second information outputs of the trigger are connected respectively to the parallel no direct coupled input of down counter counting to a second input of the selector signals and parallel connected to the down count input of down counter with a third input signal selector, the output of which is connected to the input of the clock, characterized in that the pulse counter has introduced and an alarm unit, while the counting input, the installation input to O, and the information outputs of the pulse counter are connected respectively to the output of the digital information data comparator, the nine output of the control unit and the corresponding inputs of the third AND element, the output of which is connected to the input of the alarm unit and the third input of the unit management.