RU2001516C1 - Former of sinusoidal signals - Google Patents

Abstract

Usage: radio engineering measuring technique shapers of reference signals for phase meters SUMMARY OF THE INVENTION A shaper of sinusoidal signals comprises a binary counter and a read-only memory unit. first digital-to-analog converter (DAC). null-organ shaper of short pulses, delay element, shaper of frequency correction codes, adder, shift register and second DAC. the operation algorithm of which allows to increase the accuracy of synchronization of the output signals with an external synchronizing sinusoidal signal. 2 silt

Description

The invention relates to radio engineering, measuring technology and can be used to generate reference signals for phase meters

The aim of the invention is to improve the accuracy of the synchronization of the output signals by an external clock signal

In FIG. 1 is a structural electrical diagram of a sine wave former; on Fig 2 (a. b, c, d e f e) - diagrams of work

Sinusoidal signal generator controlled pulse generator (UG) 1 binary counter 2, read-only memory unit (BPS) З. first digital-to-analog converter (DAC) 4, zero-organ 5, driver 6 short pulses delay element 7 generator code 8 frequency correction, adder 9, shift register 10, the second DAC 11 which includes the source 12 of a negative bias in a controlled generator (UG) 1 input source 13 positive bias

Shaper sinusoidal signal 1O8 works as follows

R is the moment when the polarity of the external synchronizing sinusoidal signal Ui 1 nxp arriving at the input of the zero-orgzn 5 changes; the zero-organ is switched If UCHHXP 0, then the voltage at the output of the organ 5 is positive and equal to U if Uci / nxp - 0. then - and equal to (-Uj According to this, the voltage at the output of the first DAC 4 will be equal to

SUFFER UD 0 at UCHHXP O

DBMX - -UD 0 at Usynchr O

where D is a coefficient equal to the values of the binary codes corresponding to the discrete values of the positive half-periods of the sine wave that are formed in the BPS 3

Binary counter 2 counts the pulses coming from the output of UG 1 and, in accordance with the binary code at the outputs of binary counter 2, the binary code of the discrete value of the positive half-cycle of the sinusoid at the inputs of the BSC is set. When the polarity is changed, UCKHXP switches the zero-organ 5 and the output of the shaper 6 is formed a short pulse arriving through the delay element 7 to the input reset1 of the binary counter which is reset and the formation of half-periods of the sinusoid begins in this way at the output of the first Apa 4 formed Pvyh both (positive and negative) half-periods of a sinewave out of phase with the external signa

scrap With the help of code generator 8, a frequency drift is determined and a frequency correction code a is generated using adder 9, shift register 10 and second

DAC 11 automatically adjusts the frequency G1G1 to eliminate half-cuts and to exclude pauses between half-periods of the sine wave of the output voltage when zeroing

binary counter 2 Cutting half-periods and pauses between half-periods of a sinusoid are absent if the frequency f of the input voltage Usynchr and the frequency fT of UG 1 are related by the relation

TT f 2N. (1)

where N is the total number of stages of approximation of the half-cycle of a sinusoid formed at the output of the first DAC 4

At the output of the generator of codes 8 for calculating the frequency drift, binary codes are generated, the value of which is equal to

Nflp NC4-N,

where NC4 are the values of binary codes at the output of binary counter 2

At the outputs of adder 9, binary codes will be set, with values equal to

Nt Nt 1 MDR, where Nt 1 - value of the contents of the register

shift 10 until the formation of the expected short pulse at the output of the shaper 6

Since the input Record shift register 10 is connected to the output of the shaper b

directly, then the value of Nt is fixed in the shift register 10 until the binary counter 2 is reset. Thus, the value of the contents of the shift register 10 at the end of the half-cycle of the input voltage Usync is adjusted by an amount equal to the value

MDR t Dream - N.

where MSCh t is the number of pulses received at the input of the binary counter 2 from the output

 for one half-period of voltage and async, the positive value of Мдр t corresponds to the direct code of the positive difference (Мдр t) of binary numbers equal Sword i and N, and the negative value

Nflp t corresponds to the inverted code of this difference, increased by one.

Therefore, with N, np t 0, the binary code Nt Nt 1 is established at the moment of writing to the shift register 10 at the outputs of adder 9.

at Udr t 0 binary code Nt - Nt 1

At the output of the second DAC 1, a positive voltage equal to

ICDP KI, - P,

where K is a scale factor, Ur is the boundary permissible voltage value 1)

F value. determined by the ratio

fr - fo - Kg Csdp fo - Kg K N, (2) where fc - average frequency,

Kg is the coefficient of regulation of UG 1.

When the relation (1) MDR 0 is satisfied, the value of the LRN does not change, and t remains the same. According to equality (2), for fT f 2N, the value of f decreases, and if the value of f is constant, the relation (1) holds. When fT f 2N f increases , and again equality (1)

Source 12 is intended to set a maximum value of 1) cdp Ur. source 13 is designed to set the average frequency fc UG 1

The timing diagram of the sinusoidal signal driver is shown in Fig. 2, where the following designations are introduced: UCHHX external voltage of the industrial frequency without distortion and distortion, Fig. 26 shows the UHO voltage at the output of the zero-organ 5. Fig. 2c - U3an - voltage input shift register 10,

Fig.2d - Usb input voltage Reset binary counter 2 ke Fig.2d - NC4 - binary code value at the outputs of binary counter 2. Fig.2e Ninv value of the binary code at the outputs of the BPS; not fig 2g - iveh - output voltage of the sinusoidal signal driver, in fig 2z - MCAP - voltage at the output of the DAC 11

Timing diagrams at ft f 2N

are shown by dashed lines 1, and time diagrams at ft f 2N are shown by dashed lines 2

The null-organ 5 switches when the polarity of the Usynhr changes, regardless of the shape and amplitude (Lynchr. Therefore, the sine wave shaper can be used as a converter of non-sinusoidal signals with the same

the half-periods into sinusoidal ones, i.e., as an ideal filter of the fundamental harmonic.

The above algorithm for the operation of the auto-loop allows

improve synchronization accuracy with an external clock signal

thirty

(56) Copyright certificate of the USSR No. 1129282 cl. H 03 B 19/00 1986

Claims (1)

The claims SINUSOID SIGNALS FORMER, comprising a controlled clock, a binary counter, serially connected constant memory unit and the first digital-to-analogue converter, the output of which is the output of a sinusoidal signal generator, characterized in that, in order to increase the accuracy of synchronization of the output signals, an external synchronizing signal is provided by an external synchronizing signal serially connected null organ, short-pulse shaper and delay element, in series Connections generator frequency correction codes, adder, and shift register of the second digital to analog converter whose output is connected to a control input controlled a clock generator, the binary counter being connected between the output of the controlled clock and the input of the read-only memory, the output of the delay element is connected to input Binary counter reset The input of the correction code generator is connected to the output of the binary counter, the other adder input is connected to the shift register output, the input of which is connected to the output of the short pulse generator, multiplying the input of the first digital-to-analog converter connected to the output of the zero-organ, the input of which is the input of the external synchronizing sinusoidal signal of the sine wave forger e ln . Figs