RU186349U1 - SYMMETRIC MULTIPLEXOR ON COMPLETE METAL-OXIDES-SEMICONDUCTOR (CMOS) TRANSISTORS - Google Patents

Abstract

The utility model relates to the field of microelectronics. The technical result of the utility model is the creation of a symmetric multiplexer for complementary metal-oxide-semiconductor (CMOS) transistors, which has two signal inputs, one control input, one output and made as an element of a library of standard digital elements (SCE), with higher signal switching quality due to a higher degree of identity of the propagation delays of the signals from the signal inputs to the output, due to the symmetry of the topological layers, which ensures the identity of the pair capacitive capacitances and resistances and their presence in the same electrical modes; due to the installation of additional buffer stages at the control input of the multiplexer, in order to ensure independence of signal propagation delays from the parameters of the control input driver; and also due to the increase in the size of transistors, in order to reduce the influence of local intra-crystal variations on the identity of the propagation delays of the signals. 1 n.p. f-ly; 6 ill.

Description

The utility model relates to the field of microelectronics, to asynchronous circuits, the functioning of which depends on the symmetry of the signal through digital elements, namely multiplexers on complementary metal-oxide-semiconductor (CMOS) transistors, and can be used in computer-aided design systems of digital ultra-large integrated circuits (VLSI) manufactured using CMOS bulk silicon technologies and containing circuits whose functioning depends on the symmetry of signal transmission through digital elements.

Closest to the claimed utility model is a multiplexer for complementary metal-oxide-semiconductor (CMOS) transistors (Zimmermann R., Fichtner W. Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic // IEEE journal of solid-state circuits. 1997 V. 32. N. 7. P. 1079-1090) having two signal inputs, one control input and one output. Such a multiplexer has a high speed, takes up a small area on the chip, but has non-identical propagation delays of the signals from the signal inputs to the output. In FIG. 1 and FIG. 2 shows, respectively, the electrical circuit and topology of such a multiplexer. In FIG. 1 shows n-channel and p-channel metal-oxide-semiconductor transistors 1 and 2, bus 3 of zero potential (ground), bus 4 of the supply voltage. In FIG. 2 shows the active region 5, the channel region 6 and the transistor gate region 7, the contact 8 of the active region to the first metallization level, the first metallization level 9, the topological boundary 10 of the element (multiplexer) along which adjacent digital elements are joined, pocket region 11, symbol electrical communications 12. This multiplexer is selected as a prototype of the claimed utility model.

The disadvantage of the prototype multiplexer is the low quality of signal switching, due to the low degree of identity of the propagation delays of signals from signal inputs A and B to output Y.

The technical result of the claimed utility model is the creation of a symmetric multiplexer for complementary metal-oxide-semiconductor (CMOS) transistors with two signal inputs, one control input, one output and made as an element of a library of standard digital elements (SCE), with higher switching quality signals, due to a higher degree of identity of the propagation delays of the signals from the signal inputs to the output, due to the symmetry of the topological layers, which provides an identical the parasitic capacitance and resistance values and their presence in the same electrical modes; due to the installation of additional buffer stages at the control input of the multiplexer, in order to ensure independence of signal propagation delays from the parameters of the control input driver; and also due to the increase in the size of transistors, in order to reduce the influence of local intra-crystal variations on the identity of the propagation delays of the signals.

The stated technical result was achieved by creating a symmetric multiplexer for complementary metal-oxide-semiconductor (CMOS) transistors containing nine p-channel transistors and nine n-channel transistors, and the gates of the first p-channel and first n-channel transistors T7 and T1 are connected to information (signal) input B; the gates of the second p-channel and second n-channel transistors T8 and T2 are connected to the information (signal) input A; the gates of the third p-channel, third n-channel, fourth p-channel and fourth n-channel transistors T12, T11, T18 and T17 are connected to the control input S; the drains of the third p-channel and third n-channel transistors T12 and T11 are combined with the gates of the fifth p-channel, fifth n-channel and seventh p-channel transistors T14, T13 and T5; the drains of the fourth r-channel and fourth n-channel transistors T18 and T17 are combined with the gates of the sixth r-channel, sixth n-channel and eighth n-channel transistors T16, T15 and T4; the drains of the fifth r-channel and fifth n-channel transistors T14 and T13 are connected to the gate of the seventh n-channel transistor T3; the drains of the sixth r-channel and sixth n-channel transistors T16 and T15 are connected to the gate of the eighth r-channel transistor T6; the drains of the first p-channel and first n-channel transistors T7 and T1 are connected respectively to the sources of the seventh p-channel and seventh n-channel transistors T5 and T3; the drains of the second p-channel and second n-channel transistors T8 and T2 are connected respectively to the sources of the eighth p-channel and eighth n-channel transistors T6 and T4; drains of the seventh p-channel, seventh n-channel, eighth p-channel and eighth n-channel transistors T5, T3, T6 and T4 are combined with the gates of the ninth p-channel and ninth n-channel transistors T10 and T9; the drains of the ninth p-channel and ninth n-channel transistors T10 and T9 are connected to the output Y; the sources of the first, second, third, fourth, fifth, sixth and ninth p-channel transistors T7, T8, T12, T18, T14, T16 and T10 are connected to the supply voltage bus; the sources of the first, second, third, fourth, fifth, sixth and ninth n-channel transistors T1, T2, T11, T17, T13, T15 and T9 are connected to the zero potential bus (ground).

For a better understanding of the claimed utility model, the following is a detailed description with the corresponding graphic materials.

FIG. 1. The electrical circuit of the multiplexer on complementary metal-oxide-semiconductor (CMOS) transistors, made according to the prototype.

FIG. 2. The structural and topological circuit of the multiplexer on complementary metal-oxide-semiconductor (CMOS) transistors, made according to the prototype.

FIG. 3. The general electric circuit of the multiplexer on complementary metal-oxide-semiconductor (CMOS) transistors, made according to the utility model.

FIG. 4. General structural and topological scheme of the multiplexer for complementary metal-oxide-semiconductor (CMOS) transistors, made according to the utility model.

FIG. 5. The structural and topological diagram of a multiplexer for complementary metal-oxide-semiconductor (CMOS) transistors, made according to a utility model, which shows the first metallization level and its contacts to the active region and to the second metallization level, as well as the topological boundary of the element (multiplexer) .

FIG. 6. Structural-topological diagram of a multiplexer for complementary metal-oxide-semiconductor (CMOS) transistors, made according to a utility model, which shows the second metallization level and its contacts to the first and third metallization levels, as well as the third metallization level and the topological element boundary ( multiplexer).

Consider in more detail the embodiment of the claimed symmetric multiplexer for complementary metal-oxide-semiconductor (CMOS) transistors (Fig. 3-6).

In FIG. 3 shows n-1 and p-channel 2 metal-oxide-semiconductor transistors, a zero potential bus 3 (ground), a supply voltage bus 4. This multiplexer circuit contains nine p-channel and nine n-channel transistors, and the gates of transistors T7 and T1 are connected to the information (signal) input B; the gates of transistors T8 and T2 are connected to the information (signal) input A; the gates of transistors T12, T11, T18 and T17 are connected to the control input S; the drains of transistors T12 and T11 are combined with the gates of transistors T14, T13 and T5; the drains of transistors T18 and T17 are combined with the gates of transistors T16, T15 and T4; the drains of the transistors T14 and T13 are connected to the gate of the transistor T3; the drains of the transistors T16 and T15 are connected to the gate of the transistor T6; the drains of transistors T7 and T1 are connected respectively to the sources of transistors T5 and T3; the drains of transistors T8 and T2 are connected respectively to the sources of transistors T6 and T4; the drains of transistors T5, T3, T6 and T4 are combined with the gates of transistors T10 and T9; the drains of transistors T10 and T9 are connected to output Y; the sources of transistors T7, T8, T12, T18, T14, T16 and T10 are connected to the supply voltage bus; the sources of transistors T1, T2, T11, T17, T13, T15 and T9 are connected to the zero potential bus (ground).

In the proposed version of the multiplexer, the signal from the control input S is supplied to two parallel inverters T11, T12 and T17, T18, after which the inverse control signal is supplied to the corresponding control transistors T5 and T4 and inverters T13, T14 and T15, T16 connected to the corresponding control transistors T3 and T6. Transistors T3, T5 and T4, T6 block or pass signals coming from the data inputs B and A, respectively, through transistors T1, T7 and T2, T8 depending on the logic level at the control input S. Next, the signal from the drains T3, T5, T4 , T6 enters output Y through the inverting stage T9, T10.

Unlike the prototype, the signal from the control input S is supplied to the control transistors not directly, but through buffering inverters that isolate transistors T5 and T6 from the driver of the control input S, thereby eliminating one of the sources of the delay difference. In addition, in the claimed utility model, the input stage of the inverters at the control input S is duplicated to provide the possibility of a symmetric trace of the signals to the control transistors.

In FIG. 4 shows the active region (ion implantation) 5, the channel region 6 and the transistor gate region 7, the contact of the active region 8 to the first metallization level, the topological boundary 10 of the element, the pocket region 11, the symbol of the electrical connection 12, the regions p + and n + are not shown . In the constructive and topological solution of the claimed multiplexer, transistors and their gates are arranged symmetrically, providing the possibility of symmetrical tracing of metallization lines (Fig. 5 and 6). This arrangement of topological structures ensures the identity of the parasitic parameters of the topology and their electrical modes during signal propagation from inputs A (at a low level at input S) and B (at a high level at input S) to output Y. Also, unlike the existing prototype, the area the transistor channels T1-T8 is increased to reduce the influence of local technological variations on the chip on the parameters of these transistors, and, consequently, on the variance of the delay difference.

In FIG. 5 shows contact 8 of the active region to the first metallization level, first metallization level 9, topological boundary 10 of the element, contact 13 of the first metallization level to the second metallization level.

In FIG. 6. shows the topological boundary 10 of the element, the contact 13 of the first metallization level to the second metallization level, the second metallization level 14, the contact 15 of the second metallization level to the third metallization level, the third metallization level 16. Metallization line 17 connected to zero potential. The presence of this line ensures the independence of the electrical mode of the parasitic parameters of the line combining the drains of the transistors T3-T6 and the gates of the transistors T9, T10, from the signal at the input S.

The results of SPICE modeling of the claimed multiplexer taking into account spurious parameters of the topology and possible technological variations showed that the maximum delay difference decreases by about ten times compared to the prototype.

The claimed utility model can be used to create multiplexers with a large number of inputs. The design of the claimed multiplexer with two signal inputs, one control input and one output allows you to use it as an element of a library of standard digital elements (SCE). The identity of the propagation delays of the signals from the inputs to the output of the claimed multiplexer is achieved due to the following features. The symmetry of the topological layers ensures the identity of parasitic capacitances and resistances and their presence in the same electrical modes. Additional buffer stages are installed at the control input of the multiplexer to ensure independence of delays from the driver parameters of this input. At the same time, the sizes of transistors are increased to reduce the influence of local intracrystalline variations on the identity of delays.

Although the embodiment of the utility model described above was set forth to illustrate the claimed utility model, it is clear to those skilled in the art that various modifications, additions and replacements are possible without departing from the scope and meaning of the claimed utility model disclosed in the attached utility model formula.

Claims (1)

Symmetric multiplexer for complementary metal-oxide-semiconductor (CMOS) transistors containing nine p-channel transistors and nine n-channel transistors, and the gates of the first p-channel and first n-channel transistors T7 and T1 are connected to the information (signal) input B ; the gates of the second p-channel and second n-channel transistors T8 and T2 are connected to the information (signal) input A; the gates of the third p-channel, third n-channel, fourth p-channel and fourth n-channel transistors T12, T11, T18 and T17 are connected to the control input S; the drains of the third p-channel and third n-channel transistors T12 and T11 are combined with the gates of the fifth p-channel, fifth n-channel and seventh p-channel transistors T14, T13 and T5; the drains of the fourth r-channel and fourth n-channel transistors T18 and T17 are combined with the gates of the sixth r-channel, sixth n-channel and eighth n-channel transistors T16, T15 and T4; the drains of the fifth r-channel and fifth n-channel transistors T14 and T13 are connected to the gate of the seventh n-channel transistor T3; the drains of the sixth r-channel and sixth n-channel transistors T16 and T15 are connected to the gate of the eighth r-channel transistor T6; the drains of the first p-channel and first n-channel transistors T7 and T1 are connected respectively to the sources of the seventh p-channel and seventh n-channel transistors T5 and T3; the drains of the second p-channel and second n-channel transistors T8 and T2 are connected respectively to the sources of the eighth p-channel and eighth n-channel transistors T6 and T4; drains of the seventh p-channel, seventh n-channel, eighth p-channel and eighth n-channel transistors T5, T3, T6 and T4 are combined with the gates of the ninth p-channel and ninth n-channel transistors T10 and T9; the drains of the ninth p-channel and ninth n-channel transistors T10 and T9 are connected to the output Y; the sources of the first, second, third, fourth, fifth, sixth and ninth p-channel transistors T7, T8, T12, T18, T14, T16 and T10 are connected to the supply voltage bus; the sources of the first, second, third, fourth, fifth, sixth and ninth n-channel transistors T1, T2, T11, T17, T13, T15 and T9 are connected to the zero potential bus (ground).

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