RU1833957C - Device for discrete control of power - Google Patents

Abstract

Usage: the invention relates to electrical engineering and can be used in devices for controlling power controllers. SUMMARY OF THE INVENTION: A predetermined value of a control parameter is set by an analog switch 19 and a digital switch 10. The code Kt defines the relationship between the duration of the connection of the load 16 to the network using two adjacent connection schemes defined by the code Kg. The time relationship between the durations of connecting the load 16 to the network according to various schemes is adjusted once per cycle Тp by the pulse parameter control unit of the ring counter 8, which controls the operation of the multiplexer 9. The transition algorithm from one load connection circuit 16 to another is stored in a programmable memory 6. With possible load switching circuits of 16 and I Tp / 2l periods of the mains voltage on the control cycle Tp, the circuit provides K IJ stable control stages, due to It achieved the following goal. 1 ill. sl c

Description

00 CJ

from ju s VI

The invention relates to electrical engineering and can be used in devices for controlling power regulators of electrothermal installations connected to an alternating current network.

The purpose of the invention is to improve the accuracy of regulation.

The drawing shows a block diagram of the proposed device.

The device for discrete power control contains a relay control unit for controlling the parameter, two elements 2I 2 and 3, two reversible counters 4 and 5, two programmable memory devices (ROM) 6 and 7, ring counter 8, multiplexer 9, digital sensor 10, shaper of triggering pulses 11, shaper of 12 sync pulses, two shapers 13 and 14 of counting pulses, the executive body 15, the information terminals of which are connected to the outputs of the shaper 11 of the triggering pulses, and the energy leads to conclusions for connecting a three-phase supply network and load terminals 16. The adjustable parameter control unit 1 contains a sensor 18 and an analog control parameter regulator 19, the outputs of which are connected to the corresponding inputs of the adder 20, as well as a threshold element 21, the input of which is connected to the output of the adder 20, and the inverse and direct outputs, which are outputs of the adjustable parameter control unit 1 - with the first inputs of the corresponding elements And 2 and 3. The outputs of the elements And 2 and 3 are connected respectively to the summing and subtracting inputs a reverse counter 4, the parallel loading inputs of which are connected to the outputs of an exactly digital setter 10. The address inputs of the ROM 7 are connected to the outputs of the reverse counter 4, and the outputs are connected to the information inputs of the multiplexer 9, the address inputs of which are connected to the outputs of the ring counter 8. Ring overflow output the counter 8 is connected to the high inputs of the elements And 2 and 3, and the input is connected to one output of the clock generator 12, the inputs connected to the terminals for connecting a three-phase supply network. The direct and inverse outputs of the multiplexer 9 through the counters 13 and 14 are connected respectively to the summing and subtracting inputs of the reversible counter 5, the parallel loading inputs of which are connected to the outputs of the Coarse digital controllers. The address inputs of the ROM b are connected to the outputs of the reversible counter 5, and the outputs are connected to the information inputs of the driver 11 of the trigger pulses, the input of the trigger of which is connected to the other output of the driver 12 of the clock pulses.

 Inputs of parallel loading of reverse counters 4 and 5 are connected to button 22 Record counters.

The device operates as follows.

The operator, using the key digital 10 and analog 19 dials, sets the set value of the control parameter (for example, the temperature in the furnace zone).

The signal from the analog master 19 is fed to the subtracting input of the adder 20, to the summing input of which the signal of the transmitter 18 of the control parameter is received. Differential signal is input

threshold element 21. If the difference signal exceeds the response level of threshold element 21, then a log signal is set at its direct output. 1, and on the inverse output - a log. 0.

The encoded signal Coarsely and Precisely (Kg and Kt) from the digital setter 10 is fed to the inputs of the parallel download of the reverse counters 5 and 4, respectively. When the Record button is pressed, the code fixed at its inputs of parallel loading is recorded in counters 4, 5 and appears at their outputs.

The digital code Kt sets the ratio between the durations of connecting the load 16 to the network according to two adjacent schemes of its connection specified by the Kg code.

The digital code Kt from the outputs of the reverse counter 4 is fed to the address inputs of the ROM 7, the outputs of which are set to 1-bit information stored in the ROM 7. The number of bits I is determined by the number of periods of the supply voltage during the regulation (repeatability) period Tn: I - Tp / 2 w. Specified 1-bit

parallel code

m

P

fifty

10

0)

fed to the information inputs of the multiplexer 9, the address inputs of which

55 are controlled by a ring counter 8. A ring counter 8 counts the pulses from one of the outputs of the clock generator 12 at the moments when the corresponding voltage passes through zero from one

sign area to another to the number I on

segment O, Tn, after which it is zeroed and repeats the count. At the output of the multiplexer 9 with a pulse repetition rate at the input of the ring counter 8, a 1-bit parallel code is converted into a serial one.

When the signal of the first log, 1, appears at the direct output of the multiplexer 9, a pulse appears at the summing input of the reverse counter 5, increasing its content by one. The digital code from the outputs of the reversible counter 5 is fed to the address inputs of the ROM 6. Accordingly to the digital code, the ROM 6 generates at its outputs a combination of logical 1 and O, which is fed to the inputs of the driver 11 of the triggering pulses and provides opening and closing of the corresponding semiconductor keys of the actuator 15 and the specified The switching circuit of load heaters 16 with a power of R Ш for a duration of 20 t ms, where t is the number 1 in a 1-bit ROM code 7.

When a signal appears, the first log. 1, an impulse appears at the inverse output of the multiplexer 9, at the subtracting input of the reverse counter 5, decreasing its contents by one. New digital code from the outputs of the reverse counter

5 arrives at the address inputs of the ROM 6. According to the new digital code ROM

6 forms at its outputs a different combination of logic 1 and O, which enable the opening and closing of the corresponding semiconductor switches of the executive body 15 and another circuit for switching on the load heaters 16 with a power of R w lasting 20 ms, where n is the number of O in the 1-bit ROM code 7.

If the difference between the values of the monitored parameter and its setting exceeds the response level of the threshold element 21, a log signal is set at its direct output. T. At the moment the counter 8 is zeroed, that is, at the moment of the start of the subsequent control cycle Tn, when the log pulse appears at the overflow output of the counter 8. 1, this signal is fed to the subtracting input of the reverse counter 4, reduces its content by one. A new digital code from the inputs of the reverse counter 4 is supplied to the address inputs of the ROM 7, the outputs of which are set to 1-bit information

and

t-1

n + 1

10

which is fed to the information inputs of the multiplexer 9, which controls the operation of the reversible counter 5. As a result, the ROM 6 forms at its outputs one combination of logical G and O, which enable the load heaters 16

with a power of P1 lasting 20 (t-1) ms, and another combination of logical 1 and O, providing the inclusion of a circuit of load heaters 16 with a power of 20 (p + 1) ms,

If, after Tp 20 I ms, the difference between the values of the monitored parameter and its setting will still exceed the level of operation of the threshold element 21, then at the moment of arrival of the overflow from the overflow output of the ring counter 8 pulse log. 1, the contents of the reverse counter 4 will decrease by one. At the outputs of the ROM 7

1-bit information will be set

t-2

n + 2

25

110O

(3)

thirty

35

40

45

fifty

55

As a result, the ROM 6 generates at its outputs one combination of logical 1 and O, providing the inclusion of a circuit of load heaters 16 with a power of Р t lasting 20 (t-2) ms, and another combination of logical 1 and O, providing inclusion of a circuit of load heaters 16 with a power of duration 20 (n + 2) ms.

If, after Tn 20 I ms, the difference between the values of the monitored parameter and its setting is less than the level of operation of the threshold element 21, a log signal is set at its inverse output. 1 and at the moment of arrival of the impulse log. 1 from the overflow output of the ring counter 8, the contents of the reverse counter 4 are increased by one, the code (1) is set at the output of the ROM 7 and the circuit operates as described above.

Thus, the proposed device allows for the regulation period Tp 2 I ms to connect the load to the network with one circuit with a duration of 2-0 (1-1) ms, i O, I, and with another circuit with a duration of 20 i ms, which j possible load switching circuits allows to obtain the number of control steps K Ij, as a result, the accuracy of control of the monitored parameter is improved.

Claims (1)

Brethren Formula Discrete power control device comprising a relay control parameter control unit, digital control parameter controller, first storage device, trigger pulse generator, information inputs of which are connected to the outputs of the storage device, characterized in that, in order to increase the accuracy of regulation, a second memory device, clock generator, multiplexer, ring counter are introduced , two reversible counters, two shaper of counting pulses, two elements And, and the first inputs of elements And are connected to the corresponding by the outputs of the relay block for controlling the regulation parameter, and the second inputs - with the overflow output of the ring counter, the input of which is connected to one output of the clock generator, the inputs connected to the terminals for connecting the three-phase supply network, the outputs of the elements And are connected to the summing and subtracting inputs of the first reversible counter, whose parallel boot inputs are connected to Exactly digital outputs setter, the address inputs of the second storage device are connected to the outputs of the first reversible counter, and the outputs are with the information inputs of the multiplexer, the address inputs of which are connected with the outputs of the ring counter, the summing and subtracting inputs of the second reversible counter are connected via counting pulse generators to the direct and inverse outputs of the multiplexer, respectively, the inputs of the parallel loading of the second reversible counter are connected to the outputs of the Coarse digital master, and its outputs are to the address inputs of the first memory device, the trigger input of the driver of the trigger pulses is connected to another output of the driver of the clock pulses.