RU1833892C - Computational node of device for solving equations in partial derivatives - Google Patents

Abstract

The invention relates to the field of computer engineering and can be used in the construction of specialized and problem-oriented processors for solving elliptic partial differential equations. The device contains a multi-input adder, a shift register, an element AND, four groups of delay elements and a group of elements I. Designed to solve three-dimensional problems of mathematical physics, it differs from the known ones by its high speed and accuracy of solution and allows to reduce the number of nodes of the digital grid. 2 ill.

Description

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The invention relates to the field of computer engineering and can be used in the construction of digital grids and processors for solving problems of mathematical physics.

The purpose of the invention is to increase the accuracy of calculations.

In FIG. 1 shows a diagram of the proposed site.

It contains a multi-input adder 1, shift register 2, element And 3, group of elements And 4, delay elements 5-8, first 9, second 10 and third 11 of the group of information inputs, the first 12, second 13 and third 14 control inputs, parallel 15 and serial 16 outputs the result of the node.

The first group of 9 information inputs of the node is connected to the first group of inputs of the multi-input adder 1, the output of which is connected to the information input of the shift register 2, the information output of which is connected through the AND elements of group 4 with a parallel output. the result of the node 15, the serial output of the result of 16 of which is connected through the And 3 element to the serial output of the shift register 2. The third 14, second 13 and first 12 control inputs of the node are connected respectively to the inputs of the shift register control of the shift 2, the second input of the element I.Z and the second inputs of elements And group 4. The second group of information inputs 10 of the node is connected through elements 5

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s s s s u

delays of the first group with the second group of inputs of the multi-input adder 1 and inputs of elements 6 of the delay of the second group, the outputs of which are connected to the third group of inputs of the multi-input adder 1 and the inputs of elements 7 of the delay of the third group, the outputs of which are connected to the fourth group of inputs of the multi-input adder 1, fifth group the inputs of which are connected to the third group of information inputs of the node 11 and the inputs of the delay elements 8 of the fourth group, the outputs of which are connected to the sixth group of inputs of the multi-input adder 1.

To the first 9 group of information inputs of the node, a sequential code of eight (for the Laplace equation) or nine (for the Poisson equation) numbers of lower order bits is supplied. The second 10 and third 11 groups of information inputs of the node are supplied with a sequential code of six and twelve numbers, respectively, in the lower order bits. Each successive bit of these numbers goes to the inputs of the multi-input adder 1, at the output of which the summation result is generated. The transfers to the next bits are stored on the corresponding memory elements (not shown) of the multi-input adder 1 and are used in the following clock cycles when summing the next (1 + 1, etc.) bit bits. When solving the Poissonan equation, one of the information inputs 9 of the first group is supplied with a serial value code - 60h Fijk, where Fyk is the value of the first part of the equation. The remaining information inputs 9 of the first group are supplied (synchronously with the bits of the right-hand side) the bits of the values (Ui ± 1, J ± i, k ± 1) of the eight nearest corner in two adjacent (i ± 1) layers of the nodes of the three-dimensional grid. The second 10 group of information inputs is supplied with a sequential code of a bit of values (Ui, ± 1, k ± 1: Ui ± 1, j, k ± 1; Ui ± 1. J ± ik) of the twelve nearest diagonally in the i-th layer and two adjacent (I ± 1) layers of the nodes of the three-dimensional grid. The third 11 group of information inputs of the node is supplied with a serial code of a bit of values. (Ui ± 1. j, k; Ui. J ± 1, k; Ui, jk ± O from the sequential outputs of the result of 16 neighboring nodes along layer (i) column 0 ) and row (k) of the 3D digital mesh model (FIG. 2). These numbers pass through delay elements 5-8, which delay by one clock cycle — processing time of one bit. As a result of this number, incoming to the second 10 and third 11 groups of information inputs

nodes are multiplied by fourteen and three factors, respectively. A delay of one clock cycle is equivalent to multiplying by a factor of two, so the numbers coming in

the third group of information inputs 11 are fed to the input groups of the multi-input adder 1 directly with a coefficient of unity and, having passed through the delay elements 8, s. by a factor of two, i.e. the total coefficient is three.

In order to promptly enter the value - 6Qh Fijk into all nodes of the digital grid and increase the speed, this value can be preliminarily entered in parallel code. A register is provided for this purpose, at the output of which, under the influence of control signals, a serial code of the value - 60h Fijk is generated at each iteration of the solution .

The result of the summation of each bit of numbers obtained at the output of the multi-input adder 1 is entered into shift register 2. The code of the value of the desired function Uijk at the previous rth iteration, contained in shift register 2, is shifted at each clock cycle under the control of the signal received The third input 14 is the control input of the node and is output to the serial output 16 of the result via the And 3 element and to the parallel output 15 of the result through the And elements of group 4. - The And 3 element is opened by a signal supplied to the second 13 control input during all fifth kt (where n is the bit depth of numbers). After passing n

the clock element And 3 is closed and in the next seven clock cycles, the shift register 2 is shifted by seven bits in the node. At the same time, seven high order bits of the numbers coming from the serial outputs 16 of the result of neighboring nodes are processed due to their passage for one to seven clock cycles through delay elements 5-8. During (n + 7) clock cycles, a new code is generated in shift register 2

the approximate value of the desired solution:

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which is required to realize the dependence Ј (iX; lx,; iu.

, (СЛХ-1, l, X, l, Л uVCu ,,. ,, k ,,,, k ,.

iH ,,, x. ,, 0 i-i-diC1 nL1 tii (rl «lЈ8 u i l.jii.fcil uin, J4 (,. i., j-i,

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, 1-1l .., 1,), (+ 1- (о (Л- 4

,, i ,,,, () - ih4ik,

which provides an approximation of the Laplace differential operator for the three-dimensional Laplace equation with an error of up to b, and for the Poisson equation with an error of up to h6 or h4, depending on the function of the right-hand side of F ..

Subsequent iterations are carried out similarly and, when comparing the results at the next two iterations, the first 12 control inputs receive a signal that opens a group of 4 elements AND, through which the decision result is output from shift register 2 to parallel output 15 of the node result.

Compared with the prototype, the proposed device provides a higher accuracy of the solution, since the error of approximating the differential operator for the Laplace equation in it is determined by the eighth order of degree of sampling step (h), and in the prototype by the second order (h). Since at pea; If a digital grid device is used to solve the three-dimensional Laplace or Poisson equation, the required number of nodes is 1 / h, then the use of the proposed node for constructing a digital grid reduces the hardware costs of the grid by significantly reducing the number of nodes, since the sampling step (h) for a given the accuracy of the solution can be significantly increased compared to the prototype. So, for example, if you want to obtain a solution of the Laplace equation with accuracy (5 10, then the step for the proposed node is 0.1, and for the prototype 0.0001. Then the digital grid should contain 1000 nodes or 10 nodes for the proposed device - This is due to the fact that the accuracy of the solution in the proposed device is (1 / h) times higher than the accuracy of the prototype.In addition, the number of iterations to achieve a solution is significantly reduced, since the number of iterations is proportional

squared number of nodes, i.e. increases the speed of the device by 1 / h6 times.

Formula (1) approximates the differential operator of the initial Laplace level with the error 0 (h8), which is verified by expanding the differential operator at the nodes of the volume matrix in the Taylor series and summing them with the coefficients by formula (1).

Claims (1)

SUMMARY OF THE INVENTION A computing node of a partial differential equation solving apparatus comprising a multi-input adder, a shift register, an element And, and a tuple of elements And, wherein the first group of information inputs is connected to the first group of inputs of the multi-input adder, the information output of the shift register is connected to the first inputs of AND groups, second inputs and outputs, which are connected respectively with the first control input of the node and with the parallel output of the node result, the serial output of the shift register ha is connected to the first input of AND, the second input and output of which is connected respectively to the second control input of the node and the serial output of the result of the node, the third control input of the node is connected to the shift control input of the shift register, characterized in that, in order to increase the accuracy of calculation , it contains four groups of delay elements, and the second group of information inputs of the node is connected through the delay elements of the first group to the second group of inputs of the multi-input adder and the inputs of the delay elements the second group, the outputs of which are connected to the third group of inputs of the multi-input adder and the inputs of the delay elements of the third group, the outputs. which are connected to the fourth group of inputs of the multi-input adder, the fifth group of inputs of the ketoroid are connected to the third group of information inputs of the node and the inputs of the delay elements of the fourth, group, the outputs of which are connected to the sixth group of inputs of a multi-input adder, the output of which is connected to the information input of the shift register. W5 Inputs fl u VUVVOIu G, sum g / I 7 1 Block Ex. S / jjjK Multiplication TG Registerf X l v c .. 11 - Exit & Fig /   elements, support L 5 Hh & .-hedgehog / „T Multi-way adder I - Register 3-Zlep8nti / J-  WITH.. 11 - Exit l / Group x I elemen yu8 And J J Y Element And Exit 10 eleven f du /4 12 . # / Influenza in Elento &