RU1825433C - Inductance coil - Google Patents

Abstract

Usage: the invention relates to the field of electronic technology and the production of radio-technical products in microelectronic design and can be used in integrated analog devices and other products with enhanced functionality of both special and general industrial applications. SUMMARY OF THE INVENTION: in order to ensure the maximum value of the inductance value for a given geometrical dimensions of the coil, as well as more efficient use of the volume of a semiconductor substrate, the supporting base is made composite, containing a single-crystal semiconductor plate of the first type of conductivity, the working surface of which is oriented in the crystallographic plane (100) formed through hole, the side faces of which are a family of crystallographically (111) planes. 2 ill. (L C

Description

The invention relates to the field of electronic engineering and the production of electronic products in microelectronic performance and can be used in integrated analog, analog-to-digital and digital-to-analog devices and other products with enhanced functionality of both special and general industrial applications.

The aim of the invention is to ensure the maximum value of the inductance at a given geometric

dimensions of inductance, as well as more efficient use of the volume of the semiconductor substrate of the device.

In FIG. 1 is an isometric view of an inductor of a structure according to the invention; in FIG. 2 is a vertical cross-sectional view of the structure of the layers of an inductor in the case of creating a multilayer coil solenoid.

The device includes a first wafer 1 of n-type monocrystalline silicon, a through hole 2 formed in the volume of the wafer material

00

ND SL CO CO

With

single-crystal silicon, vertical cylindrical regions 3 of semiconductor-dicar + -type conductivity,

highly doped contact regions 4 of the p-type semiconductor, dielectric layers 5 formed on the surfaces of the wafer of single-crystal silicon and crystal, contact windows b formed in the dielectric layers, contact pads 7 of conductive material, the second wafer 8 of n- single-crystal silicon conductivity type side faces 9 of plate 8, layers 10 of ferromagnetic material formed on side faces of the through hole, layers

11 ferromagnetic material formed on the side faces of the crystal, layers

12 dielectric on the surface of the ferromagnetic core, horizontal sections 13, 14 of rectangular turns of the solenoid made of conductive material of the first and second level, interlayer dielectric 15, which are used as layers based on silicon dioxide.

The following are examples of the practical implementation of the design of the inductor.

Example 1 In the volume of a semiconductor first wafer 1, which is a single crystal wafer of 100 KEF 4,5 (100e) -480 single crystal, which meets the requirements of ETO.035.314. TU, ETO.035.240 TU or ETO.035.245. STU, a conductivity p-type with a concentration of dopant atoms, which are phosphorus atoms 1015 and a thickness dnn 480 + -20 μm, is formed by anisotropic etching through hole 2. The lateral faces of which are a family of crystallographic planes {111 }, forming with crystallographic planes {100}, serving as the working surfaces of the initial wafer of single-crystal silicon 1, an angle equal to 54, 75 ° due to the use of methods of etching wafers single-crystal of silicon with a crystallographic orientation of the working surface in the direction of the crystallographic {100}.

In addition, in the volume of the material of the wafer 1 of single crystal silicon of p-type conductivity, vertical cylindrical portions 3 of the semiconductor of the second type of conductivity, namely, p-type, are formed. obtained by thermal diffusion or electrothermodiffusion of an aluminum atom. Moreover, region 3 of the semiconductor

The second type of conductivity permeates the entire thickness of the material of single crystal silicon wafer 1, forming on opposite sides of the last rutile region. It follows that the length of regions 3 is exactly equal to the thickness of a single-crystal silicon wafer and this can be expressed by the relation:

10

deepT.o6fl.ad (™

(1).

In this case, the geometric dimensions of region 3 in the plan are determined as 10, OX 10.0 μm, and the concentration of aluminum atoms, in

the aforementioned regions 3 is determined at the level of 1018-1020 and the corresponding volume resistance of these regions 3 does not exceed 6.0 Ohms. The above area 3 semiconductor

of the second type of conductivity are arranged in a row with a spacing in the row, 0 µm, thus forming one of the vertical rows of vertical sections of rectangular inductance coils.

In order to ensure reliable contact of the vertical regions 3 of the semiconductor of the second type of conductivity with the horizontal sections of the rectangular turns of the solenoid of the inductor, highly doped contact regions 4 of the p-type semiconductor with the concentration of dopant atoms, namely boron, are formed on the opposite sides of the single crystal silicon plate , at the level of 10-10 and the depth of the pn junction, 5-2.5 microns. which is significantly less than the thickness of the original plate 1 of single-crystal silicon, this is reflected by the ratio:

.

(2)

Thus, the vertical regions of the 3 p + -type of conductivity seem to connect the highly doped contact regions of the 4 p-type of conductivity, forming a structurally integrated whole with the latter, i.e. vertical section of the rectangular coil of the solenoid of the inductor. In this case, the aforementioned regions 3 and 4 of the p-type semiconductor are separated from the main material of the initial wafer 1 of n-type single crystal silicon by the regions of pn junctions.

On the surface of the formed structure, layers 5 of dielectric material are created, which are used as impurity-silicate glass layers or pure silicon dioxide or composite layers based on silicon dioxide and silicon nitride, silicon dioxide and silicon carbide, silicon dioxide and aluminum oxide, etc. 0.85-1.75 microns thick. In the dielectric layer 5 located on the horizontal surfaces of the wafer 1. of single crystal silicon, contact windows 6 are formed located directly above the highly doped regions of the 4 p type conductivity. Moreover, the topological dimensions of the contact windows 5 are always smaller than the topological dimensions of the high-alloyed regions 4 by a value of 2.0 μm in order to prevent metal shorting on the substrate region. The dielectric layers 5 also protect the side surfaces of the through hole.

On the horizontal surfaces of the dielectric layers 5 directly above the regions of the contact windows 6, contact pads 7 are formed, which are regions of a conductive material, for example aluminum or copper, the surface of which is coated with 1.5- to 1.5-mm thick gold layers to reduce the specific volume resistance. 2.5 μm, which provide ohmic contact of the horizontal sections of the rectangular turns of the solenoid with the vertical sections representing regions 3 of the semiconductor of the second type of conductivity -type. The topological dimensions of the contact pads 7 are 10.0 X 10.0 μm. Thus, on the surface of the layers 5, a series of contact pads are formed with a spacing of 0 microns.

In the through hole 2 of the wafer 1 of n-type monocrystalline silicon, a second wafer 8 of the n-type monocrystalline silicon (100 KEF 4,5 (100) -480), made in the form of a truncated pyramid, the side faces 9 of which are a family of crystallographic planes {111}. made in the form of isosceles trapezoid and forming an angle of 45.75 ° with the base of the pyramid, representing the rectangles oriented in the crystallographic plane (100). It should be noted that the single-crystal silicon wafer 8 conformally reproduces the shape and geometric dimensions of the corresponding through hole 2.

In the volume of the plate material 8, vertical cylindrical

regions 3 of a semiconductor of a p + type of conductivity with corresponding regions 4, which function as doped near-contact regions, used as a second symmetrically arranged series of vertical sections of rectangular turns of a solenoid. Moreover, both the horizontal planes of the second wafer 8, which serve as the bases of the truncated pyramid, and the side faces 9, are protected by dielectric layers 5 having the same parameters as layers 5 formed on the surfaces of the initial wafer 1 of single-crystal silicon.

The vertical cylindrical regions of p + type conductivity formed in the material of the wafer 8 have the same parameters and the same geometric dimensions as the corresponding regions 3 formed in the volume of the material of the wafer 1, single-crystal silicon. In this case, vertical cylindrical regions 3 of the bottom symmetrically located in the volumes of the materials of the plates 1,8 form

vertical sections of rectangular turns of the solenoid.

On the side surfaces of both the through hole 2 of the single crystal silicon wafer 1, and on the side faces x 9

plates 8. located in the through hole 2. layers of ferromagnetic material 10 and 11 are formed, respectively, which, when the plate 8 is mounted in the through hole, form a structurally uniform

whole, i.e. a core made of ferromagnetic material, which is a closed magnetic circuit, partially located in the inter-turn space of the solenoid. The thickness of the layers 10 and 11

ferromagnetic material is in the range of 5.0 to 12.0 microns.

Based on the preparation of the method of both the through hole 2 and the wafer 8 of single-crystal silicon, namely, the method

of anisotropic etching of single-crystal silicon wafers with a crystallographic orientation of (100), we can conclude that when the wafer 8 is mounted in the corresponding hole 2, the side faces

the latter perform the functions of guides, which significantly automate the process of mounting the plates, since the area of the hole is always greater than the area of the lower base of the plate 8.

On the horizontal sections of the layers 10 and 11 of the ferromagnetic material forming the closed core of the solenoid of the inductor, layers 12 are formed

layers of a high molecular weight organic compound, for example, polyimide felts .in 2.5-5.0 microns, are used as the dielectric material. Thus, the vertical cylindrical regions 3 of the semiconductor of the p + type of conduction turned out to be located at the bottom on both sides of the interface between a single-crystal silicon wafer and a single-crystal silicon crystal, i.e. on both sides of the core made of feromagnetic material.

Contact pads 7 formed on opposite rows of vertical cylindrical regions 3. Not pairwise connected by rows of horizontal sections 13 of conductive material, which are used layers of aluminum or copper with a thickness of 1.5-3.0 μm, placed on horizontal sections dielectrics layers 5 and 12 separating the surface of single crystal silicon wafers 1.8, as well as a core of ferromagnetic material.

 Thus, solenoid turns are obtained consisting of vertical regions 3 of the p type conductivity and horizontal sections 13.

The minimum distance between two adjacent vertical parts of the p type conductivity, placed in one row, i.e. the placement step in row I is determined by the operating voltage of the inductance coil (1) slave), and its electric strength. In order to ensure a n-fold margin of electric strength at the operating voltage 1) the slave must have a voltage equal to n Upa6. regions of bulk charges of pn junctions. formed between the material of the vertical regions 3 p + -type of turns of the solenoid, and the material of the original semiconductor wafers 1, 8, did not overlap. It follows from the above condition that the minimum distance between two adjacent vertical regions 3, i.e. turn pitch 1Vit. should be greater than twice the width of the volume charge region (do.o.3) of the aforementioned pn junction, thus the relationship should be satisfied:

l0HT..0.3M JnUpa6,

(3)

where M is the proportionality coefficient determined by the doping levels of the n-type contacting regions of plates 1 and 8 and the p-type of vertical regions 3.

The topographic dimensions of the through hole 2 and the plate 8 are connected by the following relation:

1-Chris 1-through through 4c1diel 5 2 {1f / matU

-2s1f / MZt. 11.

where Cris - linear topological size of the plate 8,

LcKeoa.oTB. linear topological size of the through hole 2,

idiel.b is the thickness of the layer 5 of the dielectric material,

UF / MATU, the thickness of the layer 10 of the ferromagnetic material formed on the side faces of the through hole,

IF / MAT - the thickness of the layer 11 of the ferromagnetic material formed on

side surfaces of plate 8.

Example 2. The design of the inductor is similar to that described in Example 1, except that, in order to save the area occupied by the inductor, the solenoid is multilayer, as shown in FIG. 2. At the same time, at least two p. Are formed in the volume of the substrate material made of mnocrystalline silicon and in the volume of the material of the crystal placed in the through hole 2. and vertical cylindrical regions 3 of a semiconductor of the second type of conductivity, namely a p + type. The inner rows of regions 3 are connected as in Example 1, and the outer rows of regions 3 are connected by horizontal sections 14 of conductive material located on the surface of the interlayer dielectric 15 separating the horizontal sections 13 and 13 from each other.

The inductor operates as follows.

When attached to extreme contact

pads 7 of the solenoid of the inductance coil Upa6 in rectangular coils formed by the vertical regions 3 of the semiconductor of the second type of conductivity, as well as the horizontal regions of the conductive material, a current pulse flows, which leads to the appearance of an electromagnetic induction flux supported by a core made of ferromagnetic material, made of two layers 10 and 11 of ferromagnetic material placed on the side surfaces of the through hole 2 and the plate 8, placed in between kovom space solenoid coil. In this case, an element appears in the rectangular turns of the solenoid of the inductor .-: - the motive force (EMF) of electromagnetic induction, which prevents the current from flowing in the turns of the coil.

The design of the inductor, in the production cycle of which the techniques and methods of plenary technology are widely used, will find wide application in the creation of complex radio-technical devices for electronic equipment (IET) and electronic equipment (REA). as well as units and blocks of electronic products (IET) and radioelectronic equipment (CEA) of an increased complexity group with advanced functional capabilities, in which there is an urgent need to combine the processing of 20 information signals, generate command pulses of actuators and devices that convert the energy of an electrical power source into mechanical energy, such as moving or rotating, in the manufacture of an electromechanical watch as a large about caliber, and wrist, in the production of small-sized stepper motors to create simple and reliable 30 amplifying stages, working according to the amplifier circuit with a transformer output. various controlled channel selectors, in particular, television channel selectors, in the production of 35 power inductors on inductances, in various kinds of electromechanical and electronic toys, where weight and dimensions are important, as well as power consumption40

The design of the inductor will be widely used in radio engineering products, for example, in various types of relays, transformers, formed directly as part of the 45 chip structure of the LSI or UBIS as chokes.

The greatest efficiency in the work of the proposed design of the inductor is achieved in the case when the ratio of the length of the closed loop of the core of the pheromagnetic material to the diameter of the circle into which the cross section of the core fits is less than 10.55

The use of the design of the inductor, compared with the design of the inductor adopted

Proton n provides the following advantages: to increase the maximum value of the inductance rating by using a closed core made of ferromagnetic material partially placed in the inter-turn space of the solenoid of the inductor; significantly expands the functionality of semiconductor devices by combining in the design of one device several functions for processing information signals received from external devices, generating command pulses and converting the energy of an electrical power source directly into mechanical energy of movement or rotation of the actuator; makes it possible to greatly simplify the design of low-frequency amplifiers by using amplifier circuits with a transformer output; to increase the efficiency of using both the area and the volume of the semiconductor substrate by using a composite support base in the structure, as well as by using a multilayer structure of the solenoid; significantly reduce power consumption due to the use in the design of the core of ferromagnetic material, made in the form of a closed loop; to a large extent, the area occupied by the inductor can be reduced by using a core of ferromagnetic material, as well as by using a multi-layer structure of the solenoid; Using the methods of planar technology and the principles of microdesign, it allows creating new classes of devices and devices combining in their design both the functions of processing information signals and the functions of executive bodies, which significantly reduces production costs and leads to a significant reduction in consumption energy, and also provides the shortest time from processing the information signal to the fulfillment of a given function by the executive body, while significantly reducing overall dimensions of IET and CEA; It allows developing a non-waste technology process, and often also utilizing semiconductor production wastes, since monocrystalline silicon wafers rejected at separate stages of the technological cycle of manufacturing LSIs, ICs, and other semiconductor devices are used to form the carrier base crystal. single crystal silicon wafers with a crystallographic orientation of 100 are used.

Claims (2)

1. An inductor containing a carrier base made of a single crystal semiconductor of the first type of conductivity with a thickness of 0Pl and rectangular turns, consisting of at least two parallel rows of vertical cylindrical regions of a semiconductor of the second type of conductivity, penetrating the entire thickness of the material of the carrier base, and two rows of horizontal regions of material located on the surface of the dielectric layer, characterized in that, in order to ensure the maximum value inductance at given geometric dimensions of the inductor, as well as more efficient use of the semiconductor volume the substrate, the supporting base is made of two plates, the working surfaces of which are oriented in the crystallographic plane (100), and the side surfaces are in the plane (111) installed with a gap, a core of ferromagnetic material is placed inside the gap, which is separated from the side surfaces of the plates by a dielectric, and vertical cylindrical regions are placed pore bottom in the volume of the plates and are connected in pairs by horizontal conductors. 2. The coil according to claim 1, characterized in that. in order to reduce the geometric dimensions, at least four rows of vertical cylindrical regions are formed in the volumes of the plate materials, arranged in pairs at different levels, separated by dielectric layers. gt jo / g A M 1L L. JL