RU1817249C - Digital frequency demodulator - Google Patents

Abstract

The inventive digital frequency demodulator contains 1 amplifier-limiter (1), 1 block of allocations, zero transitions (2), 1 driver of clock pulses (3), 1 driver of digital signal (4), 1 memory unit (5), 1 arithmetic unit (6), 1 output trigger (7), 1 pulse distributor (8), 1 phase-locked loop (9), 2 triggers (10, 11), 1 adder modulo two (12), one-shot ( 13), 1 reversible counter (14), 1 decoder (15), 3 I elements (16,17,19), 1 parallel register (18), 1 subtractor (20) / 1 Switch (21), 1 inverter (22 ) 1-2 4-5 21-6-7-9-18-20-16-14-15-17-14-6, 3-2.3-4-21, 3-8-5, 8-21, 8-6, 8-7, 6-18, 9-10-11-12-19-13-17,13-16,22-17,15-16, 9-11,9-19, 10-12.2 silt .

Description

The invention relates to telecommunications, mainly to the transmission of data over communication channels using frequency modulation.

The purpose of the invention is to increase noise immunity.

In FIG. 1 shows a structural electric circuit of the proposed demodulator; FIG. 2 is a diagram of a digital signal driver.

The digital frequency demodulator comprises a limiter amplifier 1, a null-transition allocation unit 2, a clock driver 3, a digital signal generator 4, a memory unit 5, an arithmetic unit 6, an output trigger 7, a pulse distributor 8, a phase locked loop 9 the first, second triggers 10.11, the adder 12 modulo two, a single vibrator 13, a reversible counter 14, a decoder 15, a third, a second element And 16, 17, a parallel register 18, a first element And 19, a subtractor 20, a switch 21, an inverter 22.

The arithmetic block b comprises a buffer memory block 23, an adder 24, and a subtractor 25.

The digital signal generator comprises a measuring counter 26 and a buffer memory unit 27.

Digital frequency demodulator operates as follows.

Immediately after power-up, block 5, parallel register 18, block 23 are reset, and the reverse counter 14 records the value of the initial threshold Nnop at the parallel inputs. The above operations are performed on the installation inputs R and C.

After resetting the device, the reception of frequency modulated signals begins. The reception process can be divided into three simultaneously occurring processes.

The first of these is receiving a signal from the input of the communication channel and converting it into a form convenient for further processing. This operation is performed by amplifier limitation.

00

th

body 1. block 2, shaper 4 and shaper 3.

The second process is the process of demodulating the received signal. This operation is carried out by block 5, switch 21, arithmetic block 6, output trigger 7, former 3 and distributor 8.

Finally, the third process is the process of adjusting the threshold value of the MPor to the changing parameters of the communication channel. This operation is carried out by block 9, triggers 10,11, block 12, one-shot 13, inverter 22, elements I16,17,19, a counter 14, a decoder 15, a parallel register 18 and a subtractor 20.

These processes occur as follows. The input of the amplifier-limiter 1 receives a random FM signal. As is known, all transmitted information in the FM signal is enclosed in zero-junctions; therefore, gain-limitation is the main element of such systems. The amplified and limited FM signal then goes to block 2. This block generates a short strobe pulse at each intersection of the zero input signal. Short strobe pulses from the output of block 2 then go to the shaper 4 of the digital signal. The task of the digital signal generator 4 is to convert the duration of the half-periods of the FM signal to the corresponding binary numbers. By such a conversion, the value of the reception signal is uniquely matched to the value of these binary numbers. So, when the next 1st strobe pulse arrives from the output of block 2, the measuring counter 26 is reset, and its contents are simultaneously written to block 27. Therefore, with the arrival of the 1st strobe pulse in block 27, a binary code combination will be stored, definitely ; corresponding to the half-cycle length between (and the 1st strobe pulses. With the arrival of the (1 + 1) -th strobe pulse, block 27 will store the duration of the half-cycle between the 1st and (1-H) st strobe pulses, etc. To perform such an operation, clock pulses from the output of shaper 3 are received at the clock input of the measuring counter 26, and the counter reset input R and clock input C of block 27 are combined, and short strobe pulses are fed to them.

The second process is the demodulation of the received signal. Suppose that at the first moment of time, a binary combination, indicated by the path N1, comes from the output of the driver 4. The signal N1 simultaneously arrives at the input of block 5 and the second input of the switch 21. Block 5 is

register storage device. Thus, when a clock pulse to arrives from the output of the distributor 9 to the clock input of block 5, the entire contents of this block are shifted by one step toward the output buses. This operation is repeated every time a clock pulse arrives at block 5. Counts of NI numbers are recorded in block 5 so that it always stores M current frequency values (NI numbers).

The value of to and M are selected from the ratio

to-B A, (1)

-

..1

M-to-g (2)

where B is the transmission rate, bit / s;

A - allowable value of edge distortion.

From relation (2) it follows that in block 5, current samples of frequency values are taken, taken over a time interval equal to the duration of a single element.

As indicated above, at the first moment of time, block 5 was reset, at the output of driver 4 a binary digital combination N1, characterizing the received signal, appeared. Then, at the output of block 5, the signal N1 after M clock

1 frequency intervals.

to

. The switch 21 on command from the output of the distributor 8 alternately polls the status of the input and output of block 5. In the first

a moment in time, the switch 21 connects the input of block 5; as indicated above, it was a binary combination of N1. This binary combination N1, passing through the switch 21, is fed to the input of the adder 24. The adder 24 together with the block 23 represents the accumulating adder. Since initially block 23 was also reset, then at the output of adder 24 they have a signal of the form

Nti- Ni + O-Ni ..

The signal N1 is recorded in block 23. At the next time, the switch 21 polls the output of block 5. At this time, the output of the block

5 will be zero. This signal also goes to the input of adder 24. As mentioned above, after the first half of the calculation cycle, block N1 is stored in block 23, which is fed to the second input of adder 24. Therefore, at the output of adder 24, signal N1 remains unchanged and is rewritten to block 23 . After the second clock period to supplied to block 5, a signal equal to N1 + N2 will be stored in block 23.

Similar operations are carried out M times before filling block 5.

Thus, in block 23, a signal equal to (in the j-th clock interval) will be stored

m

N5j X (NJ) l. (3)

I - I

To calculate M4 at the next (J + 1) -th clock interval, you need to enter a new value NJ + I and subtract the previous value Nj-m. This operation is performed by the switch 21 in conjunction with block 5.

So, at the next 0 + 1) -th clock interval to (in its first half), the output of the shaper 4 will have a binary combination equal to Nj + 1, This signal is fed to the input of the adder 24. At the output of the adder 24 there will be a signal equal to

NarVfl-Nfl + Nj + 1. (4)

After that, the signal N / Q + I) is recorded in block 23 by the signal from the output of the distributor 8. B. In the next half of the clock signal to, the switch 21 connects the output of block 5 to the input of the adder 24. The inverse output of block 5 is used. Consequently, the output of block 5 there will be a signal equal to (-Nj-m).

The output of the adder 24 have a signal equal to,

% i + i) N a + iJ-Nj-M. (5)

Therefore, the calculation of the next) signal value is carried out in two steps. In the first step, a new signal value Nj-i is introduced. In a second step, the old NJ-M signal is subtracted. The summation result in both cases is written to block 23.

The signal NЈ -t is then fed to a subtractor 25, where the threshold value Nnop supplied from the output of the reverse counter 14 is subtracted. As indicated above, when the threshold value Nnop is initially included in the reverse counter 14. defined by the relation

N (iep-.M., (6)

Here Nft, Nf2 are binary numbers at the output of driver 4 when receiving, respectively, the first characteristic frequency fi and the second characteristic frequency f2.

The sign bit from the output of the reader 25 is written to the output trigger 7. So, if the value is greater than the value of Nnop, then the output of the subtractor 25 is a logical unit. Otherwise, the output of the subtractor 25 is a logical zero.

This completes the demodulation process.

The adjustment of the Nnop value to the changing parameters of the communication channel is necessary 5, for example, when operating on. radio channel. In this case, the signal from the output of the output trigger 7 goes to the message recipient and simultaneously to block 9.

At the output of block 9, two sync10 sequences are generated. The frequency and phase of the first of them corresponds to the average phase position of the middle of the packets of the received signal. The signal of block 9 from this output simultaneously clocks triggers 10.11.

15 A second synchronization sequence is generated at the second output of block 9. This signal corresponds to the average value of the start of received packets and clocks parallel register 18.

0 Since the clock signal at the first output of block 9 corresponds to the middle of the received packets, demodulated signals are recorded in triggers 10, 11. At the same time, if a demo5 dummy package is stored in trigger 10 on the 1st clock interval, then a (1-1) demodulated package is stored in trigger 11. The value of the 1st and (I) -th packages are added modulo two in the adder 12. If these packages are one

0 sign (either 00 or 11), a logic zero signal appears at the output of adder 12. If the parcels at the lth and (M) -th intervals of different signs, then the output of the adder is a 12-logical unit.

5 The output signal of adder 12 is scanned by the synchronization sequence from the first output of block 9. So, if a logical unit appears in the middle of demodulated packets at the output of adder 12,

0 then there is a coincidence of the signals in the element And 19 and at its output a logical unit is formed. A single vibrator 13 is triggered from the leading edge of this signal, forming a pulse of duration r0 at its output strobe-im5. The signal from the output of the one-shot 13 simultaneously arrives at the elements And 16, 17. These elements And either are either closed, or one of them is open. The operation mode of these elements is controlled

0 inverter 22 and decoder 15.

Elements 16.17 are controlled by a decoder 15. As indicated above, upon initial installation, the value Nnop, previously calculated by formula (6), was recorded in the counter 14. Subtractor 20 at its output generates either a logical zero value or a logical unit value. Let the output of the subtractor be a 20 logical unit. Then the signal from the output of the subtractor 20 prepares the And 16 elements for operation. The inverter 22 inverts the output of the subtracter 20. The output of the inverter 22, which is logic zero, closes the And 17 element. The reversible counter 14 is in the middle of its state, since it is written in it Nnop. Therefore, on. the first and second outputs, the decoder 15 is a logical unit. At the first output of the decoder 15, a logic zero signal will occur when the reverse counter 14 reaches the minimum value. The second output of the decoder 15 will be a logical zero when the counter 14 has reached its maximum value.

In the case of mismatch at the (M) -th and 1st clock intervals of the demodulated packages, a pulse of duration TQ is generated at the output of the single-shot 13. This pulse passes through the element And 16 and enters the (+) input of the reverse counter 14. The latter increases its state by one. Thus, the threshold value stored in the reverse counter 14 will be equal to (Nnop + 1). If a logic zero is generated at the output of the subtractor 20, then the pulse from the output of the one-shot 13 passes through the element And 17 and enters the input (-) of the reverse counter 14. Therefore, the value (Nnop-1) is generated in the latter. Nnop threshold adjustment; only produced when packages of different signs are demodulated. As indicated above, with the beginning of each demodulated transmission, a signal is generated at the second output of block 9, which is clocked for parallel register 18. Therefore, information from the output of block 23 of arithmetic block 6 is recorded in parallel register J8 with the beginning of each demodulated transmission. Therefore, in parallel register 18, at the beginning of each parcel, the value MЈStart (M) is recorded. Let the package corresponding to the reception of the zero symbol be demodulated on the (M) -th clock interval. Information about it is stored in trigger 10. Information about the demodulated (-2) th packet is stored in trigger 11. Let the sending of a zero symbol be also demodulated at the (-2) th clock interval. Then, in the (1-1) th clock interval, the one-shot 13 does not work and the threshold value Nnop is not adjusted. Let a burst corresponding to a single received symbol be received at the 1st clock interval. Then, with the start of the 1st clock interval, a value is written to parallel register 18. i, which at this moment is close to the threshold value. This is explained by the fact that at (1-1) - m and 1 m clock intervals are accepted

parcels of different signs. Hence the value. with the start of the clock interval is close to the value of the threshold Nnop. In the reader 20, the threshold value Nnop is subtracted from the value .1. If the value

If Nnop is greater, then logic unit is generated at the output of subtractor 20. If Nach, T is less than Nnop, a logical zero is formed. The signal from the output of the subtractor 20 is supplied to the element And 16 and

through the inverter 22 to the element 17. Thus, if the output of the subtractor is a 20-logical unit, then the element I16 is prepared for operation. Element I17 is closed at this time. If i is greater than Nnop, then

the Nnop threshold value needs to be increased. On channels with unchanged parameters, Nnop tuning can be omitted. A different process occurs on the radio channels, when, for example, a Doppler frequency shift is observed. In this case, the received frequency spectrum is shifted and a threshold value needs to be adjusted. In this case, in the middle of the 1st clock interval in trigger 10

a demodulated 1-burst is recorded, and (1-1) -the burst is rewritten to trigger 11 from trigger 10. Since they have packages of different signs, the one-shot 13 is triggered. Therefore, at the output

of element And 16, a short strobe pulse appears, which arrives at the reverse counter 14. As a result, the threshold value after this becomes (Nnop + 1), etc. As indicated above, the state of the reversible counter 14 is controlled by the decoder 15. If the reversible counter 14 reaches its maximum value, then at the second output of the decoder 15 a logic zero will occur, which will close the AND 16 element.

the threshold in the direction of increase will no longer be. In the case of a reverse change in the parameters of the communication channel, similar operations occur with a decrease in Nnop.

Claims (2)

When the reversible counter 14 reaches the minimum value, the And element 17 will be closed from the first output of the decoder 15. Strict control over the threshold value with the help of the decoder 15 is necessary so that the element 17 does not respond to random interference of the Communication channel. SUMMARY OF THE INVENTION 1. A digital frequency demodulator comprising serially connected amplifier-limiter, a block of selection of zero transitions, a shaper a digital signal and a memory unit, an arithmetic unit whose output is connected to the first input of the output trigger, a pulse shaper, the first output of which is connected to the input of the pulse distributor, the first, second and third outputs of which are connected respectively to the second input of the memory unit, the first input arithmetic unit and the second input of the output trigger, the second and third outputs of the pulse shaper are connected to the second inputs of the block selection of zero transitions and the shaper of the digital signal, which, in order to increase the noise immunity, a phase-locked loop, a first trigger, a second trigger, an adder modulo two, a first element And, a one-shot, a second element And, a reversible counter, a decoder and a third element And, are connected in series a parallel register, a subtractor and an inverter, as well as a switch, the first and second inputs of which are connected respectively to the outputs of the digital signal driver and the memory unit, the fourth output of the pulse distributor with connected to the third input of the switch, the output of which is connected to the second input of the arithmetic unit, the third input of which and the second input of the subtractor are connected to the output of the reversible counter, the second output the arithmetic unit is connected to the first input of the parallel register, the second input of which is connected to the second output of the phase locked loop, the input of which is connected to the output of the output trigger, also connected to the second input of the first trigger, the output of which is connected to the second input of the adder modulo two, the output of the one-shot is connected to the second input of the third element And, the third input of which is connected to the output of the subtractor, the second output of the decoder is connected to the second input of the second element And, the third input of which is connected to the output of the inverter, the first output of the frequency control unit is connected to the second inputs of the second trigger and the first element And, the output the third element And is connected to the second input of the reversible counter. 2. The demodulator according to claim 1, characterized in that the arithmetic unit comprises a series-connected adder, a buffer memory unit and a subtractor, an output the buffer memory unit is connected to the second input of the adder, the input of the adder, the second input of the buffer memory block and the second input of the subtractor are the second, first and third inputs of the arithmetic block, the first and second outputs of which are the output of the subtractor and the output of the buffer memory block tee. Thebes. 1 2