RU1817210C - Device for controlling power switch built up of parallel-connected power transistors - Google Patents

Abstract

A transistor collector voltage sensor, a delay element, a first NAND gate 2, a NAND gate 2, an RS trigger, a 2 N gate, a controlled key, are introduced into the device. The control voltage is connected to the first input of element 2I. The second input is connected to the RS output of the trigger. The output of element 2I is connected to the control input of the controlled key and the delay element. The latter by its output is connected to the first input of the first logical element 2I-NOT, the second input of which is connected to the output of the second element 2I-NOT. The first input of the latter is connected to the output of the collector voltage sensor, and the second input with the output of the first 2I-NOT element and trigger input R. 2 ill.

Description

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The present invention relates to electrical engineering and can be used to create high current protected transistor switches.

The aim of the invention is to simplify the structure of the power switch and expand the functionality when setting up protection.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a diagram of a device; in FIG. 2 is a timing diagram of a device.

The device contains an element 2I1. delay element 2, controlled key 3, collector voltage sensor of power switch 4, logic elements 2I-NOT 5 and b, RS trigger 7, adjustable resistors 8.9,

power transistors 10,11 and a stabilized voltage source 12, and the output of the element 1 is connected to the input of the delay element 2 and the controlled key 3, which is connected to the plus of the stabilized voltage source 12 and adjustable resistors 8,9, which are connected to the bases with other terminals power transistors 1Q, 11 connected in parallel. The output of the delay element 2 is connected to the input 1 of the element 2I-NOT b, the second input of which is connected to the output of the element 2I-NOT 5. which receives a signal from the output of the collector voltage sensor 4, the input of which is connected to the collector power transistor, and 2 input element 2 AND NOT 5 connected to the output

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element 2I-NOT 6 and output 2 of the RS-trigger 7, the output of the latter is connected to the 2 input of element 2I 1,

This device operates as follows (Fig. 2) when a control voltage is applied to 1 input of element I1 (time tf), a logical unit appears from its output, since a logical unit signal from RS- output is present at the second input of this element trigger 7, which is automatically set to the indicated state at input S when the power is turned on.

From the output of element I1, the signal is supplied to a controlled switch 3 to supply a stabilized voltage from source 12 to the bases of transistors 10, 11 through individual resistors 8, 9, respectively, to limit the permissible collector current and a delay element 2, the output of which is a logic unit after a delay time of 13 aac, necessary to turn on the transistor (time ts), at the time ta, a logic 1 appeared at the output of the collector voltage sensor 4, indicating that the power transistors are turned on and lowering the voltage Uka below the threshold set by the sensor of the collector voltage of the power switch 4. The appearance of the logic unit of the collector voltage transmitter earlier than the unit from the output of the delay element 2 leads to the blocking of the element 2I-HE.6 at input 2, because at the output of element 2I-NOT 5, a signal of a logical zero appears, because at the input 2 of the 2I-NOT 5 element connected to the output of the 2I-NOT 6 element, the signal of the logical unit is set, which is installed at the output of the 2I-NOT 6 element when the circuit power is turned on. Thus, the appearance of the logical unit of the collector voltage transmitter earlier than the unit from the output of the delay element 2 testifies to the normal process of switching on the power transistors and the logical unit is stored at the output of the 2N-NOT element. If the signal of the logical unit is s, the output of the delay element is higher than the signal of the logical unit from the collector voltage sensor 4 (which means exceeding the specified collector voltage level in the presence of unlocking signals in the bases of power transistors, which leads to an accident) (time point, then at the output 2 of the 2I-NOT 6 element, a logic zero signal appears that acts on the input R of the RS flip-flop 7, which blocks the control voltage through the logic zero signal from its output

element 2Y 1. At the last output, a logic zero signal appears, which leads to the appearance of a logical zero at the output of delay element 2 and a logical 1 at the output of element 2AND-NOT b (time instant ts).

In this case, the blocking of the element 2I 1 at the input is maintained, since the RS flip-flop 7 is a memory element.

The circuit is restored to its initial state automatically when a voltage is applied or forcedly input S of the RS flip-flop 7.

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Claims (1)

The claims A device for controlling a power switch from parallel connected power transistors, comprising a stabilized voltage source, the negative terminal of which is intended to be connected to emitters of power transistors, a controlled key and adjustable resistors according to the number of power transistors, characterized in that, for the purpose of To simplify the structure of the power switch and expand the functionality when setting up protection, it is equipped with an RS trigger, element 2I, the first and second elements 2I-NOT, a delay element and a sensor of the collector voltage of the power switch, the input of which is intended to be connected to the collectors of power transistors, and the output is connected to the first input of the 2I-NOT element. whose second input together with the R-input of the RS-flip-flop connected to the output of the second 2I-NOT element, the first input of which is connected to the output of the first 2I-NOT element, and the second input to the output of the delay element, the input of which together with the control input of the controlled key is connected to the output of the 2I element, the first input of which is connected to the source of the control voltage, and the second to the output of the RS-trigger, moreover, the positive-output The stabilized source is still connected to one power terminal of the controlled key, the other power terminal of which is designed to be connected to the bases of power transistors through appropriate adjustable resistors.  N I 2-H.8if 44Ј & //: Ј Editor Compiled by S. Chirskov Tehred M. Morgenthal 4 4g Proofreader A. Obruchar