RU1815639C - Device for testing central processing unit - Google Patents

Abstract

The invention relates to computer technology and can be used in the construction of computers and other devices of computer technology. The purpose of the invention is to reduce hardware costs and expand the functionality of the device by controlling both arithmetic and logical operations. The goal is achieved. that the device contains a comparison circuit 21, adder 2, multiplexer 16. adder 18, block of elements AND 3, block of elements OR 14, shifter 5, controlled inverters 6, 7, four multiplexers 8, 15, 17, 19. 1 il ., 1 tab.

Description

all operations performed in ALU. Monitoring the correct functioning of the ALU units by replacing operations. The functioning of the device is based on two identities.

X + Y (X VY) + (X&Y) (1) CFC (X VY) 0 (X & Y) (2)

based on expression (2), we derive an expression for controlling the following operations.

XVY (X0Y) ® (X&Y) (3)

X & Y (X0Y) 0 (X VY) (4)

Consider the operation of the controlling part of the device. It consists of multiplexers 15, 16, 17, 19, a controlled adder 18 and a comparison circuit 21.

Addition operation control.

The terms X and Y arrive simultaneously at the inputs of the adder 2, blocks 3 and 4, as a result of which the values (X + Y + Pvc) are generated. (X V Y). (X & Y). The values (X V Y) and (X V Y) through the multiplexers 15, 16 are fed to the inputs of the controlled adder 18. Through the multiplexer 19, the Pvc value is received. The controlled adder 18 operates in the arithmetic adder mode, at the input - 20 - O. In the comparison circuit 21, the result of the adder 2 is compared, which is fed to the input of the comparison circuit 21, through the multiplexer 17. to the input 25 - 10. To the second input of the comparison circuit 21, the value comes from the output of adder 18, when the values of (X + Y + Pvc) and (XVY) + (X & Y) + Pvc coincide, the value O appears at the output 22, if the values do not match, the value 1 appears. Thus, to perform the operation of summing with control on the inputs of the device, it is necessary to The following signals: 9-X, 11-Y, 10-О, 13-Pakh, 20 - О, 23 - 00. 24 - 01, 25 - 10, 26 - 00, 27 - О.

Subtraction control.

Control is carried out similarly. The terms X and Y, Y go through controlled inverters 6 and 7. go to the inputs of the adder 2 and blocks 3 and 4. As a result, the values (X + Y + pvc) - (X - Y - + Pvc) are formed at the outputs of these blocks ) (X V Y), (X & Y). The results from the outputs of blocks 4 and 3, through the multiplexers 15 and 16 are fed to the inputs of the adder 18. In the comparison circuit 21, the values are compared

0

5

0

5

0

5

0

adders 2 and 18. In order to perform the subtraction control operation, the following values must be supplied to the device inputs: 9 - X, 11 -Y, 1 ,,, 13-Pvc,. 24 - 01, 25 - 10, 26, 27 - O.

Control operation summation modulo two. Control is carried out on the basis of expression (2). The terms X and Y are fed to the inputs of adder 2, blocks 3 and 4. Adders 2 and 18 operate in a summation mode modulo two. The inputs of adder 18 via multiplexers 15 and 16 receive the values (X V Y) and (X & Y). The values of the adders 2 and 18 are compared in comparison circuit 21. At the inputs of the device: 9 - X, 11-Y,,, 13-Z.rfleZ - any value 0, 1, 20 - 1, 23 - 00. 24 - 01.. 27-H.

Control operation summation modulo two with inversion. It is carried out similarly to the previous operation. The inputs of adder 2 receive the values X and Y, ii the value X 0Y X 0Y is generated in the adder. At the input of the device: 9 - X, 11 - Y,. . 13-H,, 23-I00,.,.

Operation control logical addition.

Based on the expression

(3). At the inputs of the device: 9 - X, 11 - Y, 10 - 14,. 13- H, ... 24,,.

Control operations logical multiplication.

Based on the expression

(4). At the inputs of the device: 9-X, 11 -4, 10 - 1,, 13-N,,, 24-10,,.

Shift operation control.

Control is based on the expression

R1 (X) + R1 (X) + PBT X X & X where Pwt is the value of the discharge ejected during the shift.

R1 (X) is the result of the shift operation X one bit to the right.

In the shifter, X is shifted one bit with pushing of the highest Pvc bit; in adder 18, the value of R1 (X) is shifted one bit to the left; by doubling the result at the output of block 5. with the addition of Pt in the low order. as a result, the value of X is generated at the output of the adder 18, which is compared in the comparison circuit 21 with the result at the output of block B when both values are supplied with an X value. To implement the above, the following signals should be present at the device inputs: 9 - X, 11 - X, 10 - H, 12 - O, 13 - Pvc, 20 - O, 23 - 10, 24 - 00, 25 - 01, 26, 27 - 1.

Based on the foregoing, the input / output values of the device are summarized in the table.

The device can be implemented in serial production of BIS ALU, as well as in the manufacture of ALU based on base matrix crystals (BMC).

Compare the technical characteristics of the proposed device and the prototype. The prototype allows control of arithmetic operations. In the proposed device, it is possible to control both arithmetic / logical and logical operations.

Claims (1)

The claims ALU control device. comprising a comparison circuit, an adder, three multiplexers, the outputs of the first and second multiplexers respectively connected to the first and second information inputs of the adder, the output of which is connected to the first input of the comparison circuit, the output of which is the output of the device, the first mode input of which is connected to the address input of the third multiplexer, characterized in that, in order to reduce hardware costs and expand 5 0 5 0 nor functionality by controlling arithmetic and logical operations, it contains a fourth multiplexer, the information inputs of which are connected to the inputs of the device for connecting to the outputs of the results of arithmetic addition, disjunction and conjunction of the controlled ALU, the information inputs of the third multiplexer are connected respectively to the information input of the device and the input of the device for connecting to the high-order output of the shift of the controlled ALU, the output of the third multiplex sora is connected to the third information input of the adder, the control input of which is connected to the second input of the device mode, from the third to fifth inputs of the device mode are connected to the address inputs of the second, first and fourth multiplexers, respectively, the information inputs of the first multiplexer are connected to the device inputs to connect to the outputs the results of respectively arithmetic addition, disjunction and shift controlled ALU, the information inputs of the second multiplexer are connected to the inputs of the device To connect and output the results of conjunction, disjunction, and shift, respectively, of the controlled ALU, the output of the fourth multiplexer is connected to the second input of the comparison circuit. Device I / O Values