RU1810943C - Digital adaptive antenna system - Google Patents

Abstract

Usage: in radio engineering, in particular in radar and sonar systems. The inventive digital adaptive antenna system comprises a buffer memory, an antenna array, a diagram-forming circuit, an adaptive processor consisting of N adaptation units, N filtering units, a reciprocal value calculator, a vector processor, a control unit consisting of a microprogram control unit, an operational storage device, descriptors, incremental and buffer registers, data multiplexer, decoder, comparison unit. 2 s.p., f-ly, 5 ill.

Description

The invention relates to radio engineering, in particular to radar and sonar systems.

The purpose of the invention is to increase noise immunity by direction finding of interference carriers.

In the process of adaptation, the system provides direction finding of interference carriers up to the angular direction of the DOS, as well as a qualitative assessment of the power of interference carriers.

The system is based on the orthogonalization of a covariance matrix using the Gram-Schmidt procedure. In this case, first of all, compensation is made for beams having a maximum interference power. At the same time, the interference power in other channels is monitored, and when it falls below a predetermined threshold, the corresponding channels are excluded from consideration as compensation channels.

The adaptation processor hardware contains separate adaptation and filtering units. Moreover, the adaptation blocks are based on vector processors that provide linear transformations of matrix rows. The control unit contains descriptor RAM with a set of three control counters, which allows to avoid sending large amounts of information when sorting matrix rows, bypassing only descriptor conversions.

Figure 1 shows the structural diagram of the system; figure 2 is a structural diagram of an adaptation unit; Fig. 3 is a structural diagram of one section of a vector processor; Fig. 4 is a block diagram of a control unit; figure 5 is a structural diagram of a filtering unit.

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The system (Fig. 1) contains a HEADLIGHT 1 connected to a diagram-forming circuit (DOS) 2, the outputs of which, in turn, are connected to the inputs 3 of an adaptive processor, consisting of adaptation units (BA) 4 and filtering units 8. Data buses 6 of each of the adaptation blocks 4 are associated with the first inputs of the corresponding filtering units (BF) 8, the second inputs of which are connected to the outputs 7 of the buffer storage device (BZU) 5. Each of the adaptation blocks 4 (Fig. 2) contains an inverse value calculator 9, data bus 6 connected to vector processor 10, input which controls 11 are connected to the inputs of the control unit 12. The outputs of the latter are a microcommand bus 13, connected to all the main blocks of the vector processor 10, and an address bus 14, connected to the vector processor 10, the input bus 3 of which1 is the DOS outputs 2.

Vector processor 10 consists of sections of the same type, the number of which is equal to M - the number of DOS channels 2.

Each section of the vector processor 10 (FIG. 3) contains a switch 15 in four directions, the first and second groups of inputs and outputs of which are connected respectively to the bits of the real 3-1 and imaginary 3-2 parts of the input bus 3 of the corresponding DOS channel 2, and with the first group of inputs and outputs of the first 17-1 and second 17-2 bus Shapers, respectively, and the inputs and outputs of RAM data of actual 16-1 and imaginary 16-2 parts, the address inputs of which are connected to address bus 14. The third and fourth groups of inputs are outputs of the switch 15 is connected with the inputs and outputs of the multipliers 18-1, 18-2 of the real and imaginary parts, respectively, as well as with the data inputs and outputs of the super-operative memory unit 19, the outputs of which are connected to the control bus 11, and the control input 20 is connected to the control input of the first 17 -1 and a second 17-2 bus formers, the second group of data input-output of which is connected to the data bus 6.

The control unit 12 comprises a microprogram control unit (BMU) 21, the output of which is a microcommand bus 13, and the inputs are connected to the outputs of a digital comparator 22, the first group of inputs of which is connected to the outputs of the maximum registers 23 and noise 24; the second group of inputs together with the inputs of the data of the maximum register 24 is connected to the control bus 11. In addition, block 12 contains RAM of the descriptors 25, the outputs of which

connected to the inputs of the first incremental 26 and buffer 27 registers. The outputs of the first incremental register 26 are connected to the address bus 14, with inputs

the second incremental register 28 and with the first group of inputs of the data multiplexer 29, the second group of inputs of which are connected to the outputs of the buffer register 27, the third group of inputs - with the outputs of the second

0 of the incremental register 28, and the outputs are with the data bus of RAM descriptors 26, the address inputs of which are connected to the outputs of the address multiplexer 30, the first group of data inputs of which are connected to the outputs of the counter of the initial value 31, the second and third of the group of inputs are connected to the outputs of the counters of the current 32 and maximum 33 values, as well as with the first and second groups of inputs of the comparison circuit

0 34, the output of which is connected to the input of the firmware control unit 21. The outputs of the second incremental register 28 are connected to the inputs of the decoder 35, the outputs of which are the control outputs

5 to 20, and the outputs of the initial value counter 31 are associated with the data inputs of the current value counter 32. In addition, a second group of inputs of the decoder 35 is associated with the address bus .14. The filtering unit 8 (Fig. 5) contains an input switch block 36, the inputs of which 7 are connected to the outputs of the BZU 5, and the outputs - to the first inputs of the multiplier unit 37, the second group of inputs of which is connected to the outputs of the second block of registers 38, b 5 connected to the data bus 6 through the first block of registers 39. In this case, the outputs of the block of multipliers 37 are connected to the inputs of the b / Current of adders 40, the outputs of which are connected to the first inputs of the subtracting adder 41, the second inputs of which are connected to the corresponding bits of the outputs of the BZU 5 and the outputs are system outputs.

The number of adaptation blocks 4 (N) in the adaptive processor is determined by the required

5 system performance. Their resolution, i.e. the number of sections is determined by the number of channels in the system. The number of BZU 5 sections is also equal to M, and the capacity is determined by the maximum v clock interval length

0 radar. The number of filter units 8 (N) in the adaptive processor is determined by the number of signal beams in which interference cancellation is performed. The number of sections is determined by the maximum number of interference carriers.

The system operates as follows. The signals from the output of the PHAR 1 through DOS 2. in the form of digital samples of data are fed to the inputs of the BZU 5 and adaptive processor and. in particular, on adaptation blocks 4. All

the samples from all channels of DOS 2 are stored in the BZU 5. In this case, the samples of the initial period of the clock interval, which form the training sample, entering one of the adaptation blocks 4, are stored in its internal RAM 16. This sample carries information about the noise situation in the angular direction x scanned headlights 1. The objective of the system is to suppress interference penetrating through the side lobes of the radiation pattern into the signal channels. For this, from the obtained training sample, adaptation unit 4 calculates a sample covariance matrix, and from it the weighting coefficients for the compensation channels. The calculated values of the weighting coefficients are transmitted to BF 8. Simultaneously, samples of input signals begin to arrive at BF 8, delayed in BZU 5 during the calculation of weighting coefficients in BA 4. The signals are filtered in BF 8 in real time and fed to the outputs system.

Let us consider in more detail the process of calculating weight coefficients in BA4.

The operation of all nodes of BA 4 is controlled by BMU 21. BMU generates control signals, as well as all addresses on address bus 14, except for addresses generated by RAM descriptors 25 and the first incremental register 26. Counts of the training sample of each channel from outputs 3 DOS 2 enter the corresponding section of the vector processor 10. BA 4. In addition, each of the samples is a complex value that comes in the form of two quantities - the real (Re) 3-1 and imaginary (Im) 3-2, for remembering which designed two separate RAM 16-1.16 - 2. One belt with a filling in the RAM 16 a count value received via the switch 15 to the multiplier-accumulators 18-1,18- 2, each of which is carried out the accumulation of the sum of squares of values of co-responsible of the real and imaginary parts of the training sample readings. After receiving the training sample, the contents of the storage multiplier of the imaginary part 18-2 are sent through the switch 15 to the storage multiplier of the real part 18-1, where their values are added. Thus, the training sample for a given channel is stored in the memory 16 of each section, and the rms value of the interference power in this channel is stored in the storage multiplier 18-1 (the value is always valid). The specified value is sent to one of the registers of super-memory 19.

Before calculating the covariance matrix, the threshold value, which is hereinafter referred to as the noise threshold, is entered into the noise register 24 of the control unit 12.

The maximum register 23 is cleared. If during further transformations the calculated interference power in any compensation channel becomes lower than the noise threshold, then this channel is considered insignificant and its information is not used in the future.

The coefficients of the covariance matrix are calculated under the control of the incremental register 26, which forms a sequence of addresses on address bus 14, each of which corresponds to one row of the matrix. The address of the training sample line is supplied to the address inputs 14 of the RAM 16 of each section of the vector processor 10. Data from the RAM 16 is read into the storage multipliers 18. The second incremental register 28 is reset, and a control signal from one of the buses 20 is received from the corresponding output of the decoder 35 to the first section of the vector processor 10. In the section to which the control signal is supplied, data is also provided through the bus drivers 17 to the data bus 6. Through the data bus 6, information is transmitted to all sections of the vector processor 10. two cycle realized incoming complex multiplication value by the value read in this section. The complex value of the result is accumulated in the registers of the storage multipliers 18 / As the addresses are searched, the above operations are performed for all rows of the training sample matrix. At the end of the calculations, the values of the correlation coefficients between the channels are formed in the multiplier x-drives x 18. The calculated values are sent to RAM 16 as a row of the covariance matrix. The sequence is then repeated for the second and subsequent rows of the covariance matrix; In this case, before each sequence, the contents of register 28 are increased by one.

In parallel with the process of calculating the rows of coefficients of the covariance matrix, there is a process of evaluating the significance of its rows and sorting them.

The section block 19, to which the signal from the outputs 20 arrives, provides the stored value of the interference power in this channel in a per-cycle basis to the control bus 11. The indicated value is sent to the control unit 12, to the comparator 22. where it is compared with the contents of the noise register 24. If the power is below the noise threshold level, the contents of the final value counter 33 are increased by one and the further calculations of the current row of the covariance matrix are stopped. If the power is above the noise threshold, then the channel number from the output of the register 28 through the multiplexer 29 is entered in the memory 26 at the address formed by the counter of the current value 32. In the next step, the interference power supplied to the comparator 22 is compared with the contents of the maximum register 23. If the power less, the contents of counter 32 are incremented by one; if more, the current power value from the bus 11 is loaded into the register 23. The contents of the initial value counter are switched to the address inputs of the memory 26. At this address, the line descriptor with the old maximum value is read from the memory 26 and is written to the buffer register 27, and the value of the new maximum is entered into the memory from the output of the register 28. Then, the contents of the counter 32 are again switched to the address inputs of the memory 26 and a descriptor is written to the memory 26 from the outputs of the register 27. Then, the contents of the counter 32 are increased by one.

Thus, after calculating the coefficients of the covariance matrix at the zero address of the memory of descriptors 25, the row number of the covariance matrix with the maximum diagonal element is contained, and the contents of the counter of the final value 33 are equal to the number of significant rows in the matrix. After that, the process of bringing the covariance matrix to the upper triangular shape begins. To do this, the elements of the matrix columns located below the diagonal are alternately reset to zero.

Consider the process of zeroing one column of a matrix. The contents of register 23 are reset. The contents of the initial value counter 31 are overwritten into the current value counter 32, and the line number with the maximum diagonal element is read from the memory 25 at this address. The line number is written to the first and second incremental registers 26, 28. The contents of the counter in the form of an address on bus 14 are sent to the sections of the vector processor 10. In each section, at the specified address from RAM 16, the values of the coefficients of this line are read through the multiplexer 15 into the registers of the storage multipliers 18. The value of the diagonal element from the section selected by the signal on the corresponding bit section 20 is also supplied via the data bus 6 to the inverse value calculator 9. In block 9, the inverse coefficient value is calculated. The calculated inverse value is transmitted via the data bus 6 to the sections of the vector processor 10 and multiplied into the x-storage multiplier x 18 with the corresponding row coefficients. In this case, the value

0 of the diagonal element becomes unity, the remaining elements are normalized with respect to it. All values are written back to RAM 16 and, in addition, are recorded in the registers of multipliers by 5 accumulators 18. At the same time, the contents of counter 32 are increased by one. The next line number is read from memory 25 to register 26 and to address bus 14. The specified address, arriving at RAM 16 of the vector processor 10, selects from them the coefficients of the next row of the matrix, which are rewritten in the accumulator registers of the storage multipliers 18. Simultaneously, adder 5 from the register 28 and the selected coefficient value from the corresponding section of the vector processor 10 are fed arrives via data bus 6 to all sections. The indicated value is sent to the storage multipliers.

0 18 is multiplied by the normalized row coefficients stored in the buffer registers of the storage multipliers 18, and the results are subtracted from the contents of the storage register. The new learned coefficients of the row are rewritten back to RAM 16. In this case, the coefficient corresponding to the nullable column will be equal to zero. At the same time, the address from bus 14 is supplied to

0, the second group of inputs of the decoder 35, which forms a gate on the bit of bus 20, corresponding to the diagonal element of the current line. In the section selected in this way, the indicated coefficient

5 is fixed in block 19 (as the value of the interference power in the channel) and is output via control bus 11 to control block 12, where on comparator 22 it is compared with the contents of noise register 24. If the value is less than the noise threshold, then from memory 25 at the counter 33 is read into the register 27 line number, which is recorded at the address received from the counter 32, and the contents of the counter 33 is reduced by one.

5 Thus, the line is excluded from the list of significant. If the value exceeds the noise threshold, then a comparison is made with the current contents of the maximum register 23. If the value is less than the current maximum, the contents of the counter 32

increases by one. If the content is larger, the contents of the current maximum, addressed by the counter 31, are read into register 27. A new value is written in its place in the memory 25 and in the register 23. The previous maximum value is overwritten from register 27 to the address specified by counter 32. After that, the contents of the counter are increased by one. The indicated sequence of operations is also carried out for subsequent lines until the comparison circuit 34 fixes the equality of the contents of counters 32, 33. Thus, at the end of the procedure zeroing a column one column of the matrix will be zeroed, all rows that become insignificant after compensation for one channel will be excluded from it, and a row (channel) with maximum power will be highlighted uncompensated interference. After this, zeroing of the next column begins. To this end, the contents of counter 31 are rewritten to counter 32, and the whole sequence is repeated.

At the end of zeroing all columns, the matrix will be reduced to the upper triangular shape, and on the diagonal there will be unit values.

The final step in calculating weights is to bring the matrix to a diagonal view. To do this, the columns above the diagonal are zeroed. In this case, the matrix is zeroed in the reverse order, starting with the rows with the highest numbers.

The counter 33 is reset, the counters 31. 32 are counted in the opposite direction (in the subtraction mode), rows are not sorted during the calculation. Otherwise, the process of zeroing the columns is similar to the above.

At the end of the reduction, the matrix has unit diagonal elements, and in the significant rows of the columns corresponding to the signal channels are the desired weighting coefficients.

. The weights are sent to the registers 39 of the corresponding filtering units 8. After filling the registers 39, by the time the signals corresponding to the required clock interval arrive at the inputs of the multiplexers 36, the weights are transferred from the registers 39 to the registers 38. The multiplexers 36 provide the required compensation to the multipliers 37 channels, for which all significant channels are used. The number of sections of the block of multiplexers 36 and multipliers 37 should

be no less than the number of significant channels. In each section of the block of multipliers 37, the current values of the samples of the given channels are multiplied by the weight coefficient 5 calculated for this channel. The adder block 40 provides an addition of the products obtained for the compensation channels. Subtractor 41 provides subtraction from sample values

0 signal channel compensation compensation values.

The angular bearings for interference carriers are determined by the numbers of the compensation channels, and the information about their power is not 5 days of the value of the weight coefficients. These data are read from memory 16.

As indicated above, the number of adaptation units 4 (N) is determined by the performance of the system. If during the time interval the adaptation unit does not manage to calculate the weighting factors, two or more (N) blocks are introduced into the system, each of which will process the Mth time interval.

5 The number of filtering units 8 is determined by the maximum number of signal channels, i.e. the maximum number of simultaneously tracked targets. The use of the invention allows

0 to improve the estimation of the interference situation by obtaining bearings in the process of adaptation of interference carriers as a by-product that does not separately consume computing resources.

5 The adaptation process itself is also carried out by the system with great efficiency, due to the ranking of the compensation channels by the interference power, which in most real situations, when

Claims (3)

A limited number of noise carriers leads to a sharp reduction in the volume of calculations. In addition, the algorithm is designed so that operations are always performed only with matrix rows, which allows using a vector processor with maximum efficiency. SUMMARY OF THE INVENTION 1. A digital adaptive antenna system comprising a buffer locking device (BZU), an antenna array, the outputs of which are connected to the inputs of a diagram-forming circuit (DOS), the outputs of which are connected to the corresponding inputs of an adaptive processor, consisting of 5 adaptation blocks and N filtering units, the first inputs of which are connected to the corresponding outputs of N adaptation units, each of which contains a control unit and a vector processor, the inputs of which are the inputs of the adaptive processor, In order to increase the noise immunity by detecting interference carriers, the second inputs of N filtering units are connected to the outputs of the buffer memory, the inputs of which are connected to the corresponding inputs of the adaptive processor, an inverse value calculator is introduced, the data inputs of which are connected to the data inputs of the vector processor, the control outputs of which are connected to the control inputs of the control unit, the address outputs of which are connected to the address inputs of the vector processor, the control unit Laziness consists of a microprogram control unit, the micro-command bus of which is connected to the micro-bus of a vector processor, random access memory (RAM) descriptors, the outputs of which are connected to the inputs of the first incremental register and buffer register, the outputs of which are connected to the first inputs of the data multiplexer, the second inputs of which are connected with the inputs of the second incremental register, the first inputs of the decoder and the address outputs of the first incremental register, which are addressable in by the steps of the comparison unit, the outputs of the second incremental register are connected to the second inputs of the decoder and the third inputs of the data multiplexer, the outputs of which are connected to the data inputs of the RAM descriptors, the address inputs of which are connected to the outputs of the address multiplexer, the first inputs of which are connected to the outputs of the initial value counter and the counter setting inputs the current value, the outputs of which are connected to the first inputs of the comparison circuit and the second inputs of the address multiplexer, the third inputs of which are connected to the outputs of the final value counter and the second inputs of the comparison circuit, the outputs of which are connected to the inputs of the microprogram control unit and the outputs of the digital comparator, the first inputs of which are connected to the outputs of the noise register and the maximum register, whose inputs are connected to the second inputs of the digital comparator and are the control inputs of the block management when the outputs of the decoder are control outputs of the control unit. 2. The system of claim 1, wherein the vector processor comprises M sections, each of which consists of a four-channel switch, RAM of the real and imaginary parts, storage multipliers of the real and imaginary parts, a superoperative unit memory, the first and second bus drivers, the address inputs of the vector processor are the address inputs of RAM of the real and imaginary parts, the corresponding inputs of which are the inputs of the vector processor and are connected respectively to the first inputs - the outputs of the first and second bus drivers the first and second inputs - the outputs of the four-channel switch, the third inputs - the outputs of which are connected to the inputs - the outputs of the multiplier-accumulator of the real part and the first inputs - Exit scratchpad memory block minute, second inputs - the outputs of which are connected to the fourth inputs - the outputs of the four-channel switch and inputs - outputs of the multiplier-accumulator of the imaginary part, while the second inputs of the first and the second bus formers are data inputs of the vector processor, and the third inputs of which and the third inputs of the super-memory block are control inputs, the outputs of the super-memory block are the control outputs of the vector processor. 3. The system according to claim 1, characterized in that the filtering unit contains a block of switches, the outputs of which are connected to the first inputs of the block of multipliers, the outputs of which are connected to the inputs of the block of adders, the outputs of which are connected to the first inputs of the subtracting adder, the second inputs of which and the inputs of the switch block are the second inputs of the filtering block, the outputs of which are the outputs of the subtracting adder, the second inputs of the block of multipliers are connected to the output of the first block of buffer registers, whose input is connected to the output of the second block of buffer registers, the input of which is the data input of the filtering unit. figure 1 Fi g. 2 Fig.Z Fig L