RU1807550C - Pulse frequency-phase detector - Google Patents

Abstract

Usage: radio engineering phase-locked loop. SUMMARY OF THE INVENTION; the pulse frequency-phase detector contains the first and second D-flip-flops of the first channel, the first and second D-flip-flops of the second channel, OR elements and the first and second channels, respectively, an integrator-adder, 2I-2 OR-NOT element, as well as an additional OR element, LED and register. In the device, the level of impulse noise in the output signal is reduced, since only one of the D-flip-flops is generated, which forms an information signal, in addition, a small number of elements allows to increase the speed. 1 ill.

Description

The invention relates to radio engineering and can be used in phase locked loop systems.

The purpose of the invention is to reduce the level of impulse noise in the output signal, as well as to increase the speed while simplifying the device.

The drawing shows a structural electrical circuit of the detector.

The pulse frequency-phase detector contains the first and second D-flip-flops 1 and 3 of the first channel, the first and second D-flip-flops 2 and 4 of the second channel, an OR element. 5 of the first channel, the OR element 6 of the second channel, the integrator-adder 7 and the element 2 AND-2 OR-NOT 8, as well as an additional element OR 9, LED 10 and resistor 11.

We will consider the principle of operation of the device by the example of its implementation on TTL-series microcircuits.

Pulse frequency-phase detector (ICHFD) works as follows.

In the initial state, at the direct outputs of all D-flip-flops, the voltage levels correspond to logical O. Let on C-. the input of the first D-flip-flop 1 of the first channel receives the reference frequency pulses FO, and the input of the first D-flip-flop 2 of the second channel receives pulses of the controlled frequency FL In this case, pulses of both short and long (arbitrary) duration can be received at the indicated inputs.

In ICPD, frequency comparison modes are possible when Fo Fi or FO FI, or a phase comparison mode when Fo Fi, but D / 0 or DN. 0, where D p is the phase difference between the reference and controlled frequencies. Let Fo Fi and element 2I-2OR-NOT 8 not be involved in the operation, while at the output of the first D-flip-flop 2 of the second channel, pulse-width modulated pulses are generated, the duration of which is proportional to the phase difference between the frequencies FO and FI. After a certain time (in the worst case, after a time of 1) Fo-Fi, when the duet becomes larger

ate

with

with

o VI ate o

2p, between pulses of frequency FI two pulses of higher frequency appear. In this situation, the first frequency pulse FI switches the first D-trigger 2 of the second channel to logic 1, and the second frequency pulse Fi writes a logical Г from the first D-trigger 2 of the second channel to the second D-trigger 4.

With each subsequent pulse of frequency FI, the state of the second D-flip-flop 4 of the second channel is confirmed, since logical 1 from its direct output through the IL element AND 6 goes to the D-input of the second D-flip-flop 4 of the second channel. Thus, at the output of the second D-flip-flop 4 of the second channel, a constant logic level 1 is fixed, which means a negative sign of the frequency detuning: Fp-Fi 0. At the same time, the voltage of logic 1 from the output of the OR element 6 of the second channel in the form of a constant level is input integrator-adder 7, while the voltage at the output of the integrator-adder 7 increases at maximum speed, thereby reducing the frequency detuning at the inputs of the ICPD until the sign of the phase difference of the frequencies Fo and FI changes. After changing the sign of the difference the phases of the frequencies Fo and FI, the pulses of the frequency Fo begin to outstrip the phase of the pulses of the frequency FL As a result, the first leading pulse of the frequency FO switches the first D-trigger 1 of the first channel to a single state, and the first D-trigger 4 of the second channel is reset to O at the reset input voltage from the inverse output of the first b-trigger 1 of the first channel. Thus, the second D-trigger .4 of the second channel at) 2 l: off, turns off and at the outputs of the D-triggers Z and 4 the logical O levels are fixed, which mean the phase comparison mode of the input frequencies. In this mode, the output of the IL AND 6 element the second channel, pulses are observed with a duration proportional to the phase mismatch of the input frequencies Fo and FL At the output of the integrator-adder 7, an increase in voltage is proportional to the duration of the pulses supplied to the input of the integrator-adder 7, which reduces the phase mismatch of the input gnalov. At a zero phase shift between the input signals at the outputs of the elements OR 5 of the first channel and OR 6 of the second channel, there are no pulses, keeping the integrator-adder. 7 in the closed state.

Due to the symmetry of the ICHPD scheme, its operation in the case of Fo FI is similar to that for Fo FI, with the only difference being that

logical state 1 switches the second D-trigger 3 of the first channel, the voltage from which through the OR element 5 of the first channel acts on the integrator-adder 7, decreasing the voltage at its output at maximum speed until the phase mismatch sign, while the second D trigger 3 of the first channel is reset to zero

0 state after switching the first D-flip-flop 2 of the second channel to the single state by the first frequency pulse FI after the indicated situation. Next comes the phase comparison phase of the input frequencies, at

5 which, at the output of the first D-trigger 1 of the first channel, pulses are generated with a duration proportional to the phase mismatch of the frequencies FO and Fa, FL The presence of the element 2I-.2 OR NOT 8

0 allows you to work with input pulse signals of longer duration. At the same time, the operation algorithm of D-triggers 1 and 2 is somewhat different. So, if the phase signal is ahead of the frequency signal FO, the relative

5 but the signal of frequency FI by the first pulse on a positive edge, the first D-flip-flop 1 of the first channel is brought into a single state. Logic 1 from the output of the first D-trigger 1 of the first channel is fed to

0 the first input of the logic element 2I-2OR-NOT 8 (in this case, before the input pulses at the output of the element 2I-2OR- NOT 8 there is a logical 1), from the inverse output of the first D-trigger 1 is logical

5 O, entering the D-input of the second D-trigger 2 of the second channel, blocks its switching to the single state. Logic 1, coming from the direct output of the first D-trigger 1 to the first input of the element 2I0 2OR-NOT 8, thereby allows the passage of the input pulse to the dump inputs of the D-flip-flops 1 and 2. Therefore, at the time of the arrival of the pulse FI at the output of the element 2И- 2 OR NOT 8 an impulse appears,

5 which resets the first D-trigger 1. the first channel. In this case, the duration of the reset pulse is determined by the delay time of the elements 2I-2OR-NOT. 8 and the switching time of the D-flip-flop, and therefore does not depend on the pulse width of the input signal, thereby allowing operation with pulses of longer duration. Since only one of the D-flip-flops is cocked in the device, which generates an information signal, there is no pulse noise in the input signal.

Claims (1)

Additional advantages include the possibility of a reliable indication of the synchronism mode (capture of the phase-locked loop (PAN) system, which is realized, for example, by connecting the outputs of the second D-flip-flops of each channel to the inputs of the actuator OR 9. Moreover, in the synchronism mode at the output of the additional element OR 9 there is a logical O, in the frequency mode - logic 1. Connection to the output of an additional element OR 9, LED 10 with resistor R 11 provides a visual indication of the capture of the system An AP using the considered pulse frequency-phase detector 1. The invention A pulse-frequency frequency detector made in the form of two channels, each of which contains the first and second D-flip-flops.The synchronization inputs of which are the input of the corresponding channel, and the OR element, the inputs of which are connected to the direct outputs of the D-trigger, and the output is connected to the 0-input of the second D-trigger, characterized in that, in order to reduce the level of impulse noise in the output signal, as well as increase speed while simplifying device, the integrator-adder is introduced into it, the inputs of which are connected to the outputs of the OR elements of each channel, and the 2I-2 OR-NOT element, the first and second inputs of which are connected to the direct output of the first D-trigger of the second channel and the synchronization input of the first D- of the first channel trigger, the third and fourth inputs are connected respectively to the synchronization input of the first D-trigger of the second channel and the output of the first D-trigger of the first channel, and the output is connected to the reset inputs of the first D-triggers of 5 channels, D-input and inverse output of the first D -trigg One of the channels is connected respectively to the inverse output and D-input of the first D-flip-flop of the other channel, the inverse output of the first D-flip-flop of one channel is connected to the reset input of the second D-flip-flop of the other channel, and the integrator-adder output is a pulse frequency output phase detector.