RU1798793C - Device for connecting two computers - Google Patents

Abstract

The invention relates to computer technology and can be used to create multi-machine computing systems. An object of the invention is to increase the reliability of information transfer between computers. The goal is achieved in that the device comprises two decoders, two communication nodes, two switches, two receiving nodes, two transmission nodes, two receiving synchronization nodes, two transmission synchronization nodes. 4 s.p. f-ly, 18 ill.

Description

The invention relates to computer technology and can be used for sequential synchronous data transfer between computers on four-wire communication lines. It provides data transmission in duplex and half duplex ways.

The aim of the invention is to increase the reliability of the operation of the device.

Structural diagram of the device shown in figure 1; figure 2 - diagram of the receiving node; Fig. 3 is a diagram of a transmission unit; figure 4 - diagram of the node synchronization transmission; 5 is a diagram of a receiving synchronization unit; figure 6 is a diagram of the switching node; on Fig, 7 is a diagram of a signal receiver; on Fig is a diagram of a signal detector; Fig. 9 is a diagram of a programmable switch for the duration of a received signal; in FIG. 10 is a diagram of the reception synchronization; 11 is a diagram of the transmitter: in FIG. 12 is a diagram of a phasing signal driver; Fig. 1317 is a flow chart of a device; Fig. 18 is a timing chart.

A device for coupling two computers (Fig. 1) comprises a first electronic computer 1, a second electronic computer 2, a first signal converting unit 3, a second signal converting unit 4, a decoder 5, a programmable serial communication interface 6, node 7 Transmission, node 8; 9 receiving synchronization, receiving unit 10, switching unit 11.

The receiving unit 10 (Fig. 1) comprises a receiving synchronization circuit 12, a programmable comparator 13 of the duration of the received signal, a signal receiver 14, and a signal detector 15.

The transmission unit 7 (FIG. 3) comprises a transmitter 16, a phasing signal shaper 17.

Node 8 transmission synchronization (figure 4). contains 18 frequency divider, progromiel

WITH

th

00

-h

H)

with

adjustable frequency divider 19, 20 pulse generator.

The receiving synchronization unit 9 (Fig. 5) contains counters 21.22 pulses, triggers 23, 24, 31, 32, elements 25-30, 33, 34 And, decoders 35, 36, adder 37 modulo two, delay element 38.

The node 1.1 switching (Fig. B) contains a register 39, relay 40, -41, contacts 42, 43 of relay 40, contacts 4, 45 of relay 41.

The signal receiver 14 (Fig. 7) contains resistors 46. 47, 48, 51, 53.54, 55, 56, diode 49, operational amplifiers 50, 52.

The signal detector 15 (Fig. 8) contains resistors 57,58,59, 67, 69,70,71,72, diodes 60, 62, 63, operational amplifiers 61, 65, 66, capacity 64.,

The programmable comparator 13 of the duration of the received signal (Fig. 9) contains triggers 73, 82, a programmable frequency divider 74., adder 75 modulo two, elements 76, 77, 78, 79 I, elements of equivalence 80, 81.

The reception synchronization circuit 12 (FIG. 10) contains triggers 83, 84, 87, AND elements 85, HE elements 86, 88.

The transmitter 16 (11) contains. Elements 89, 92, 95 NOT, elements 90, 91, 93, 94 And, transistors 96, 97, 98, 99, resistors 100, 101, 102, 103.

The phasing signal generator 17 (FIG. 12) comprises an AND element, a pulse counter 105, an HE element 106, an AND element 107, a trigger 108.

The operation algorithm of the device is shown in Figs. 13-17.

A timing diagram of the signals generated in the signal conversion blocks 3 (4) is shown in Fig. 18.

The external address bus 40 of the first electronic computer 1 is connected to the decoder 5, the external control bus 39 of the electronic computer 1 is connected to the control input of the switching unit 11, the external data bus 38 of the electronic computer 1 is connected to the information input-output of the programmable interface 6 serial communications. The outputs of the decoder 5 are connected to the address inputs of the programmable serial communication interface 6, the transmission synchronization unit 8, the reception unit 10, the switching unit 11. The external control bus 39 of the electronic computer 1 is connected to the control input of the programmable serial communication interface 6, the reception unit 10, the transmission synchronization unit 8, the transmission unit 7, The external data bus 39 of the electronic computer 1 is connected to the information input-outputs of the node 10 receiving node 8 synchronization transmission node 11 switching. The first and second input of the programmable serial communication interface 6 is connected to the first and second output of the receiving unit 10, the first output is to the first input of the receiving unit 10, the third input is to the first output of the receiving synchronization unit 9, the fourth input is from the first output of the synchronizing unit 8 transmission, the fifth input is with the first output of the transmission unit 7, the second and third outputs, respectively, with the first second input of the transmission unit 7. Second and

5 the third outputs of the node 7 are connected respectively with the fourth and third input of the node

11 switching, and the third input is with the first output of the transmission synchronization unit 8, the second output of which is connected to the fourth input of the reception unit 10, the third output is with the first input of the reception synchronization unit 9, the first output of which is connected to the second input of the reception unit 10, the second output - with the third input of the receiving node 10,

5 the third input is with the third output of the receiving unit 10, the fifth and sixth inputs of which are connected to the first and second output of the switching unit 11, the third and fourth inputs of which are connected to the first and second

0 to the output of the second signal conversion unit 4, and the third and fourth outputs to the first and second / input of the second signal conversion unit 4, the address input of which is via an external address bus 40

5 is connected to the address output of the second electronic computer 2. The control input is through an external control bus 39 with the control output of the second electronic computer 2.

0 Information input - through an external bi-directional data bus 38 with the information output of the second electronic computer 2.

Block 3 (4) signal conversion

5 provides the conversion of the parallel code into serial bipolar signals during transmission and the inverse transformation upon receipt and includes:

0 is a programmable serial communication interface 6 that converts parallel binary code to serial binary code. It can be built on BIS 580VV51A;

5 - transmission synchronization unit 8 provides the output of a serial binary code from the programmable serial communication interface 6 to the transmission unit 7 at a rate determined by the operating program. As node 8 can

one of the BIS 580VI53 channels and a frequency divider forming synchronization pulses should be used;

- t-transmission unit 7 provides the formation and transmission of a signal generating sequence, which is necessary for setting up the reception synchronization unit 9 at the receiving side of the device, and then the transmission of binary data coming from the serial communication programming interface 6 and their conversion into bipolar transmissions;

- the receiving synchronization unit 9 provides automatic phase tuning of the frequency of the transmission synchronizing unit 8 with respect to the received signals and generating receiving synchronizing pulses by comparing the data signals with the phase of the signals of the transmission synchronizing unit 8. Node 9 includes (figure 5) decimal counters 21, 22 pulses, decoders 35, 36 are designed to break the clock transmission pulses into 40 clocks, triggers 23, 24 and elements 25, 26 And designed to generate phase-ahead signals (from 0 up to 19 cycles), normal phase (from 19 to 21 cycles) and phase lag (from 21 to 40 tatoks). The OR element 27, the elements 29, 30, 33, 34, the triggers 31, 32 are designed to control the passage of the 39th, 40th or 41st strobe clock. The 39th clock — to accelerate, the 41st clock — to lengthen, or to leave unchanged the period of synchronizing reception pulses generated by the triggers 23, 24. Elements 33, 34 And, delay element 38, unequality element 37 are used to isolate strobe pulses of positive polarity on each edge of the input signal and switching gates to the S input of the trigger 31 when the phase is ahead, R the input of the trigger 32 when the phase lags or the switching is disabled during normal phasing;

- the receiving unit 10 (Fig. 2) provides reception of bipolar packages, converting them into binary code and writing to the programmable serial communication interface 6. The signal receiver 14 (Fig. 7), which is part of the receiving unit 10, provides reception of a bipolar signal, its amplification, and conversion to a bipolar binary sequence. The signal detector 15 (Fig. 8), which is part of the receiving unit 10, detects the positive and negative polarity of the input signal and compares the rectified positive voltage with the reference voltage + Uon and. signal output

a positive polarity to the output 48 when exceeding + goes over + Uon- Programmable comparator 13 of the duration of the received signal (Fig. 9) included in the receiving unit 10 provides filtering in the input signal of pulsed noise with a duration of less than a predetermined and determined software , by writing the corresponding code to the programmable frequency divider.

The reception synchronization circuit 12 (Fig. 10), which is part of the reception unit 10, provides an exchange of receiver readiness signals with the LSI 580BA51B (programmable interface 6) and storing the received bit in the trigger 83.

- the switching unit 11 (Fig. 6) provides switching of the transmitted signal to the communication line or to the input of the receiving unit and

0 switching a signal from a communication line, or from one of its transmitting units to a receiving unit.

The device operates as follows.

Electronic computers

5 1.2, the device is tuned to the required data rate and allowable duration of impulse noise by writing the corresponding codes to the programmable frequency divider 19 of the node 8

0 synchronization of transmission to the programmable frequency divider 74 of the programmable comparator 13 of the duration of the received signal. Start-stop means of the generator 20 of the assembly 8 are not required. The generator 5 starts to work when the power is turned on.

Then, the electronic computers 1, 2 output a Reset signal to the external control buses to bring the memory elements to the initial state and

0, the serial communication interface 6 is programmed to transmit and receive data by writing the corresponding code.

After that, the programmable serial interface 6 generates transmission request and reception request signals arriving at inputs 2 of transmission unit 7 and input 5 of reception unit 10, respectively.

0 In the transmission node 7, the signal from input 2 goes to the input of the element 95 NOT and then to the second inputs of the elements 93, 94 AND, allowing the passage of the phasing sequence and the transmitted data to the output

5 transmitters 16.

In addition, the signal from the output of the element 95 does NOT go to the output 52 and from the negon the first input of the elements 104,107 of the Phasing signal 17 of the phasing signals, Fig. 12). They allow the passage of pulses of phasing

sequence equal to the pulse width of the transmitted data generated by the trigger 108, by dividing the repetition rate of the transmission clock by half.

The pulses of the phasing sequence, the passage through the element 107 And go to the output 53 and from it to the second input of the element 91 And (11), prepared for opening by a signal removed from the element 90 I.

From the output of the element 91 AND, the pulses of the phasing sequence are supplied to the first input of the element 98 AND, and through the element 92 NOT, to the first input of the element 94 I.

The signals taken from the outputs of the elements 93, 94 control the operation of transistors 96, 97, 98, 99. With their help and with the help of resistors 100, 101, 102, 103, a directional current is generated at control points 17 and 18,

At the same time, the pulses of the phasing sequence arrive through the third input of the AND element 104 (Fig. 12) to the C input of the pulse counter 105, which serves to count the number of incoming pulses of the phasing sequence. After passing twenty pulses of the phasing sequence, a signal equivalent to logical zero appears at its output.

He enters:

- from the output 51 of the shaper 17 to the second input of the element 90 AND of the transmitter 16 (Fig.11) and allowing the passage of data from input 1;

- to the second inputs of the elements 107, 104 (FIG. 12), through the element 106 NOT and prohibiting the passage of pulses of the phasing sequence to the transmitter 16 and to the pulse counter 105, and also goes to output 3 in the form of a signal, which is called Free to transmit, in programmable serial communication interface 6. This signal indicates the readiness of the transmitter of the transmission nodes 7 and the reception 1.0 is exchanging data.

The generated impulses of the phasing sequence from the outputs 17, 18 of the transmission unit are sent to the switching unit 11. In which, through the normally closed contacts 42, 43, the relays 40 go to the outputs 34, 35, and from them to the communication line and to the inputs 36, 37 of the switching unit 11 of the second signal conversion unit 4, where through the normally closed contacts 44, 45 of the relay 41 on the circuit 23, 24, 21, 22 they enter the signal receiving unit of this block. .

In this node (Fig.7), the signal is supplied to the amplifier of the received signal collected on the operational amplifier 52 and resistors 51, 53, 56, 54, 55. providing the required signal amplification and input resistance of the node.

From the output of the operational amplifier 52, the signal enters the output 44, and from it to the signal detector 15 and to the inverse input of the operational amplifier 50. It provides the formation of a unipolar binary sequence at the output, together with resistors 47, 48, 46 and diode 49 from bipolar input signals. From the output of the operational amplifier 50, a unipolar binary signal is fed through a circuit of 43–45 to the input of a programmable comparator 6 of the duration of the received signal.

The input signal in the detector 15 is supplied to the voltage divider, which is performed on the resistors 69, 72 (Fig. 8) from the voltage divider, the signal is fed to the positive polarity detector, which is assembled on the operational amplifier 66, resistors 70, 71, diode 63 and to the detector

5 of the operating polarity, assembled on the operational amplifier 65, resistors 67, 68, diode 62. They serve to detect the input signal by the amplitude level and generate a voltage level of positive polarity on the capacitor 64 (11 children);

when a signal appears at the input of the device.

Formed voltage on capacitance

64 is compared using a comparator,

assembled on an operational amplifier 61,

5 resistors 58, 59, 57, diode 60, with voltage + Ucn supplied to the inverted input of the comparator 61. When exceeding goes Uon, the comparator generates a signal of positive polarity, which comes

0 through circuits 48-46, 48-49 to the second input of the programmable comparator 13 of the duration of the received signal and to the input of the reception synchronization circuit 12, respectively. This signal indicates the presence of data at the input of the device.

In a programmable comparator 13, the duration of the received signal from the detector 15 enters the second input of the element 76 AND (Fig. 9) and resolves the passage of the input

0 signals from the first input of element 76 And to the second input of the element of disambiguation 75. The signal from the inverse output of trigger 73 is received at its first input. When the signal level at the input of element 75 matches

5 there is no signal at its output, thereby permitting the counting of pulses of the reference frequency by the programmed frequency divider 74. After passing N reference frequency pulses determined programmatically, by preliminary recording the corresponding code at 74 at the output of the programmable frequency divider 74, a signal equivalent to a logical unit will appear. He goes on. With the input of the trigger 73, transferring it to a single state, the signal taken from the inverse output of the trigger 73, in this case, does not coincide with the signal present at the other input and the element 75 generates a signal supplied to the R input 74 to bring it to its original - standing

The operation of element 75 is controlled by comparison elements 81, 82. In the event of the appearance of the same signals at the output of the comparison element 80, a signal is generated by it, by which the trigger 82 is switched to a single state. A single state of this trigger indicates a malfunction or accidental failure in the elements 75, 81, 80. In order to determine the state of the trigger 82, it is periodically polled (at the end of the transmit-receive cycle).

When a signal appears on the second input of element 75 with a duration shorter than the counting time N of the reference frequency pulses, the signal at the output 74 does not appear and the trigger 73 does not change state.

The input / output 27 of FIG. 2 and FIG. 9 is a data bus of a computer operating for writing and reading data.

In the process of input / output 27, data is written to 74 and read from element 78 (Fig. 9) and being various computer addresses (subscribers),

Thus, the programmable comparator 13 duration provides the selection of pulsed interference. As a programmable frequency divider 74, LSI type 580VI53 can be used.

The extracted useful signal from the programmable duration comparator 13 is supplied via a 16-50 circuit to the first input of the reception synchronization circuit 12. At its second input, there is a signal from detector 15. It enters the D-input of trigger 87 (Fig. 10), and through element 88 NOT to S the input of trigger 84. Upon arrival of the clock pulses to the C-input of trigger 87, it is generated at its output the signal supplied to the second input of element 85 I. The trigger 84 is reset to the zero state and a low-level signal is removed from its output, which is called Ready to receive receive synchronization in the absence of electrical communication between the signals at inputs 4 and 6 is carried out programmatically through a programmable interface 6 after communication link. When information appears and if there is a request for a programmable interface 6 o

reception, issued on the circuit 5, the node 1.2 generates a signal in response The reception readiness issued on the programmable interface 6. Thus, by the presence of a signal at the output 6, the programmable interface will know about the presence in the circuit 4 of the node 12 of the transmitted data, i.e. In this way, the moment (synchronization) of the availability of data in circuit 4 is determined by the signal in circuit 6. The signal Readiness of reception is received in the programmable interface 6.

The electronic computer analyzes this signal and starts reading the data that enters the programmable interface 6 of output 4, to which trigger 83 is connected.

A timing diagram of the operation of the signal conversion unit is shown in Fig. 18.

Information transmission by electronic computers is carried out in a duplex manner and is carried out as follows. Electronic computers issue a Reset signal, configure the device nodes (by writing the appropriate code) to the required data rate and the expected duration of the impulse noise,

Thereafter. Figures 1 and 2 send out the Transmission Request and the Receive Request signals and analyze the occurrence of the signals. Ready for transmission. And Ready for reception, generated by the signal conversion blocks 3, 4 by reading and analyzing the phrases of the programmable interface.

When the device is ready for transmission, the electronic computer transmits an array of the transmitted data and, when the data appears, provides for reading the data array from the signal conversion unit and writing to its random access memory.

A received data array is a set of code combinations from correction codes and containing a checksum of the received array. The electronic computer scans the received array for the purpose of detecting the code combinations received with the error and corrects them. Then it calculates the checksum of the received array and compares the calculated checksum of the PODS. With the data contained in the data array transmitted by the CONTROL SUM Sc before.

When S subs.1.1 2zh in front, the electronic computer transmits a message about this abnormality in S, Device

it organizes a retransmission of the same data array, correction of the code combinations received with errors, calculation of the checksum of the received array of heights, and comparison with the transmitted sum 2 "before .. When the second Lc heats. 2 before, the data exchange is stopped and a transition to the fault locator and localization program is automatically performed.

According to the program for troubleshooting, the electronic computer 1 connects the output of the transmitter 16 to the input of its own signal receiver 14 by way of a signal to its own receiver 14 by turning on the relay 41 in the switching unit 11. This is done by writing the corresponding code to the register 39 of block 3. The electronic computer 2 connects the output of the transmitter 16 to the input of its own receiver 14 in block 4. This is done by turning on the relay 40 in the switching unit 11 by writing the corresponding code to register 39 block 4.

Then 1 and 2 simultaneously check the functioning of their blocks 3, 4 by transmitting, receiving and comparing the received and transmitted test sequence.

In case of a malfunction of the received and transmitted test sequence 1 (2) gives information about the malfunction of its signal conversion unit 3 (4),

 When comparing the transmitted and received test sequences, 1 proceeds to an additional check of the normally closed contacts of the relay 41 of block 3. This is accomplished by connecting the output of the transmitter to the input of its own receiver. This is achieved by turning on the relay 40 and turning off the relay 41, i.e. by writing the corresponding code to register 39. The electronic computer 2, at the same time, goes on to check the unverified normally closed contacts of the relay 40 of block 4, by connecting the input of the receiver to the output of the transmitter, as well as turning on the relay 41 and disconnecting the relay 40, 1 and 2, while transmitting, receiving and comparing the transmitted test sequence.

If the received and transmitted test sequences are not compared, the electronic computer. Provides information about the malfunction of its signal conversion unit.

When comparing the transmitted and received test sequences, the electronic computer provides information about the health of its blocks

signal conversion that. indicates a malfunction of the communication line between the signal conversion units.

The transmission of information between 1 and 2 half-duplex method is as follows:

The electronic computer 1, which starts the transmission of information, generates a Reset signal, adjusts the device nodes to the required data exchange rate and the expected duration of the impulse noise, and also connects the input of the signal receiver to the output of the transmitter. This is for the purpose of monitoring the output information. To do this, the relay 41 of the switching unit 11 is turned on.

The electronic computer 2, simultaneously with 1, performs similar preparatory operations.

After that, 1 issues the signal Transmission Request and the Request for Reception to the signal conversion unit 3 and analyzes the signal appearance. The readiness of the transmission of the signals generated by the signal conversion unit by reading and analyzing the word length of the programmable interface.

When the device is ready for transmission, the electronic computer transmits a set of code combinations to the communication line and, with the aid of its receiver, receives the signals of the same code combinations from the communication line and compares the transmitted and received each code combination in real time.

If the transmitted and received code patterns are not compared, 1 organizes a retransmission of the same code pattern. When retransmitting the code pattern, it is also read from the line using its receiver and 1 re-compares the transmitted and read code pattern. In case of repeated non-comparison - 1 stops the data transmission and gives a message about the malfunction of its signal conversion unit 3. When all code combinations are transmitted to the communication line, 1 switches to the mode of receiving information from 2 by connecting to the receiver input line of the receiver / by disconnecting the relay 41 from the transmitter output.

The electronic computer 2 receives the transmitted information 1, scans for the purpose of detecting the code combinations received with an error and correcting them,

Then. 2 calculates the checksum of the received information (S sub.) And

comparison with the transmitted checksum (Sc before) is similar to that described above.

The received message is compared with the transmitted one and, in case of non-comparison 2, it analyzes the type of message and when the message is abnormal, the electronic computer 2 stops the exchange and gives a message about the malfunction of the signal conversion unit 4, and when the message is NORMAL 2, it organizes the message again and controls the correctness of its issuance . When the comparison of the transmitted and received message is repeated, NORMA 2 stops the exchange and gives a message about the malfunction of block 4,

If the delivery of message 2 is correct, it analyzes the form of the transmitted message and, in the case of NORMAL exchange, it proceeds to the execution of the following programs in accordance with the functioning algorithm 2.

When transmitting a message, NENORMA 2 analyzes the number (N) of retransmissions of the data array and, when N 2, the electronic computer 2 switches to re-receiving the data array. With NJ2, it switches to the block 4 health check program, similar to the check program for the duplex data exchange method and described above.

At the same time, 2 receives a message sent to 2 about the NORMAL or NORMAL rate of transmitting the data array. At NORMAL 1 it analyzes the number N of retransmissions of the data array and at N 2 the electronic computer 1 switches to retransmitting the data array, At N 2 it goes to the verification program the health of unit 3, similar to the program with the duplex method of data exchange and described above.

The reliability of the operation of the device in duplex mode is ensured by the use of correction codes used to encode the transmitted information. When operating in half-duplex mode, the reliability increases due to the fact that we transfer the transmitted data from the computer1 and the computer2 back to the computer1 from the communication line by connecting the computer1 receiver (the receiver in half-duplex mode is free) and byte-by-bit control of the transmitted data from the point of the communication line . Thus, we ensure the reliability of the transmission of data transmitted by computer1 to the line.

When transferring data from computer2 to computer1, it does the same, ensuring the reliability of the transmission of data to the line of transmitted computer2.

The reliability of information transmission is increased with respect to failures of the Failure type due to the use of correcting codes and the failure of technical means that currently provide data transmission due to the control of the transmitted data.

The algorithm of the device shown in Fig.13-17 ..

The advantage of the developed system is:

- increasing the reliability of the operation of the device by an amount proportional to the probability of a malfunction in the receiving unit when operating in half-duplex mode due to a change in the configuration of the device. This is achieved by using the receiver, in transmitting data, as a monitoring device. It is connected to the output of the transmission node in order to control it in real time;

- increasing the noise immunity of the device by introducing a programmable digital pulse duration comparator. It provides pulse noise selection, the duration of which is less than the programmed response time of the comparator;

- reducing the time to search and localize a malfunction in the device due to the operational monitoring of the transmitted information in half duplex mode;

- increase the controllability of the device by reducing the time of localization of the malfunction. This is achieved by automatically switching, in the event of a malfunction, to the program for finding and localizing a malfunction in the data transmission mode in duplex mode .-.

Claims (5)

SUMMARY OF THE INVENTION 1. A device for connecting two computers, comprising a first decoder, a first communication node and a first switch, the information inputs of the first group of devices for connecting the first computer being connected to the information inputs of the first decoder, the first control input of the peo group of the device for connecting to the first computer is connected to the first control input of the first switch, the information input-output of the first group of devices for connecting to the information bus of the first computer is connected to the information input -output of the first node communication on t l and h and w o f e c the fact that, in order to increase the reliability of information transfer between computers, the first and second reception nodes, the first and second transmission nodes, the first and second reception synchronization nodes, the first and second transmission synchronization nodes, the second decoder, the second switch and the second node are introduced into it communication, and from the second fifth control inputs of the first group of devices for connecting to the control bus of the first computer are connected respectively to the installation input in the initial state of the first transmission node, to the installation input in the initial state the first transmission synchronization node, to the first control input of the first reception node and to the first control input of the first communication node, the first, second and third information inputs / outputs of the first group of devices for connecting to the information. the bus is connected respectively to the second control input of the receiving node, to the first input of the mode of the first transmission synchronization node and to the second control input of the first switch, from the first to the fourth outputs. the first decoder are connected respectively to the second control input of the first communication node, to the third control input of the first reception node, to the second input of the mode of the first transmission synchronization node and to the third control input of the first switch, the first to fourth outputs of which are connected respectively to the first and second information inputs of the first receiving node, to the first and second information inputs of the second switch, the first to fourth information inputs of the first switch are connected respectively to the first and second outputs of the second switch, to the first and second outputs of the first transmission node, the third output of which is connected to the first information input of the first communication node, the first and second outputs of which are connected to the first and second information inputs of the first transmission node, respectively the first and second outputs of the first receiving node are connected respectively to the second and third information inputs of the first transmission node, the first and second outputs of the first receiving node are connected to the second and third, respectively the information inputs of the first communication node, the third output of which is connected to the third information input of the first receiving node, the third output of which is connected to the installation input in the initial state of the first receiving synchronization node, the first the output of which is connected to the first synchronization input of the first reception node and to the first synchronization input of the first transmission node and to the second synchronization input of the first communication node, the second and third outputs of the transmission synchronization node are connected respectively to the second synchronization input of the first reception node to the second input of the first node mode receiving synchronization, the second output of which is connected to the third synchronization input of the first receiving node, the information inputs of the second device group are connected to the information inputs of the second of the first decoder, the first to fifth control inputs of the second group of the device for connecting to the control bus of the second computer are connected respectively to the first control input of the second communication node, the first control input of the second receiving node, to the input of the initial installation of the second transmission synchronizing node , to the input of the initial installation of the second transmission node and to the first control input of the second switch, from the first to the third information inputs and outputs of the second group of the device for connecting to the information bus of the second M are connected to the first, second and third information inputs and outputs of the second communication node, to the second control input of the second receiving node, to the first mode input of the second transmission synchronization node and to the second control input of the second switch, information inputs and outputs from the fourth according to the K-second group of the device for connecting to the information bus the second computers are connected respectively to the information inputs-outputs from the fourth to the K-th (where K is the bit size of the data of the second communication node), from the first to the fourth outputs of the second about the decoder are connected respectively to the second control input of the second communication node, to the third control input of the second reception node, to the second input of the second transmission synchronization node and to the third control input of the second switch, the first and second outputs of the second communication node are connected respectively to the first and second information inputs of the second transmission node, the first and second outputs of which are connected respectively to the third and fourth information inputs of the second switch, the third and fourth output which is connected respectively to the first and second information inputs of the second receiving node, the third output of the second transmission node is connected to the first information input of the second communication node, the third output of which is connected to the third information input of the second receiving node, the first and second outputs of which are excluded respectively second and third information inputs of the second communication node, the third output of the second receiving node is connected to the first input of the second receiving synchronization node, the first output of which is connected to to the first synchronization inputs of the second communication node and the second reception node, the first output of the second transmission synchronization node is connected to the second synchronization input of the second communication node and to the synchronization input of the second transmission node, the second and third outputs of the second transmission synchronization node are connected respectively to the second synchronization input the second receiving node and to the second mode input of the second receiving synchronization node, the second output of which is connected to the third synchronization input of the second receiving node. 2. The device according to p. 1, with the exception that the receiving unit comprises a synchronization unit, a signal duration comparator, a receiver and a detector, the first, second, third information inputs, the first, second, the third synchronization inputs, the first, second, third control inputs of the receiving node are connected respectively to the first information input and the second information input of the receiver, to the reset input of the synchronization unit, the first clock input of the synchronization unit, to the synchronization input of the comparator of the signal duration, to the second mute clock input of the synchronization unit, to the first, second and third inputs of the comparator mode of the signal duration, the first and second outputs of the synchronization unit are connected respectively to the first and second outputs of the receiving unit, the output of the comparator of the signal duration is connected to the first input of the start of the synchronization unit and to the third output of the node the reception, the first and second outputs of the receiver are connected respectively to the first information input of the comparator of the signal duration and to the input of the detector, the output of which is connected to the second the information input of the comparator of the signal duration and to the second input of the start of the synchronization unit, while the synchronization unit contains three triggers, two elements NOT and the AND element, and the first and second clock inputs and the reset input of the synchronization unit are connected respectively to the synchronization input of the first and second triggers and to the input of the first element is NOT, the output of which is connected to the first the input of the And element, the output of which is connected to the installation input in O of the third trigger, the first trigger input of the synchronization block is connected to the information 5 input of the second trigger, the output of which is the first output of the synchronization block, the second trigger input of which is connected to the information input of the first trigger and to the input of the second element 0 NOT, the output of which is connected to the installation input in 1 of the third trigger, the output of which is connected to the second output of the synchronization unit, the output of the first trigger is connected to the second input of element I. 5 3. The device according to claim 1, with the proviso that the transmission unit comprises a transmitter and a phasing signal generator, the first and second information inputs, the synchronization input, and the input of the initial installation of the transmission unit respectively, to the first and second information inputs of the transmitter, to the synchronization input, and to the input of the initial installation of the phase shifter, the first, second, and third outputs of the transmitter are connected respectively to the first and second outputs of the transmission unit and to the information input of phasing signal world, first, 0 the second and third outputs of which are connected respectively to the first, second inputs of the transmitter and to the third output of the transmission node. 4. The device according to claim 1, with the exception of 5, wherein the transmission synchronization unit comprises a frequency divider, a programmable frequency divider, a clock generator, the first and second transmission synchronization nodes, the second and third mode inputs of each transmission synchronization unit are connected respectively to the first, second and third inputs of the programmable frequency divider mode, the first output of the pulse transmission synchronization unit 5 is connected to the information input of the frequency divider and to the third output of the sync node ronizatsii transmission, 5. The device according to claim 1, with the exception of 0 so that the receiving synchronization unit contains two counters, two decoders, four triggers, an adder modulo two, a delay element and eight AND elements, in the first and second synchronization nodes; receiving the first input of the receiving synchronization node mode is connected to the input of the delay element and to the first information input of the adder modulo two, the output of which is connected to the first inputs of the first and second elements AND, the output of which is connected accordingly to the input of the installation in the first trigger and to the input, the installation in 1 of the second trigger, the output of which is connected respectively to the first inputs of the third and fourth elements And, the output of which is connected respectively to the first and second inputs of the fifth element And, the output of the delay element is connected to the second information input of the adder modulo two , the second input of the reception synchronization node mode is connected to the counting input of the first counter, the information inputs of which are connected respectively to the information inputs of the first decoder, the first output of which is connected the second input of the third element And, the second output of the first decoder is connected to the first input of the sixth element And and to the first input of the seventh element And, the output of which is connected to the installation input in 1 of the third trigger, the output of which is connected to the first output of the receiving synchronization unit and to the second input of the first element And, the third output of the first decoder is connected to the second input the fourth element And and to the first input of the eighth element I. the output of which is connected to the installation input in O of the fourth trigger, the output of which is connected to the second input of the second element And, the transfer output of the first counter is connected to the counting input of the second counter, the information outputs of which are connected respectively to the information the inputs of the second decoder, the first, second and third outputs of which are connected respectively to the second input of the seventh element And, to the second input of the eighth element And and to the third input of the fourth of the And element, the fourth output of the second decoder is connected to the third input of the third And element and to the second input of the sixth And element, the output of which is connected to the third input of the fifth And element, the output of which is connected to the installation input to O of the second and third triggers, to the installation input to 1st of the first and fourth triggers, to the input of the installation in O of the first and second counters and to the second output of the synchronization node. . /. +% l / mg. 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