RU1795477C - Device for union of lexical sets - Google Patents

Abstract

The invention relates to the field of computer engineering and is intended for the definition of lexical sets, the construction of dictionaries, as well as for the hardware implementation of the microcommand combining lexical sets. The purpose of the invention is to enhance functionality. The device contains gating inputs, control and information inputs and outputs, decoders, AND, OR, NOT, AND-NOT elements, multiplexers, triggers, a memory unit, counters, word frequency analysis units, a delay element. Depending on the given operating mode, the device allows combining lexical sets, forming a dictionary, selecting the most common vocabulary. The operation of the device consists of three stages: the formation of intermediate results, determining the rank and number of identical words, writing values to random access memory, and issuing information. 2 ill.

Description

The invention relates to the field of computer engineering and is intended to combine vocabulary sets, build dictionaries, and also implement a macro to combine lexical sets.

A device for calculating the combination of sets containing information inputs, the first, second and third binary counters, the first comparison circuit, the first and second decoders, random access memory, input Reset, signaling output, the first, second, third elements And, the first and second elements OR, pulse generator, delay element, synchronization output, the output of the first AND element

connected to the first vhrd of the first element OR.

A disadvantage of the known device is limited functionality, since it does not allow the processing of lexical sets.

A device for combining lexical sets containing information outputs, first, second and third binary counters, a first comparison circuit, first and second decoders, random access memory, input Reset, signaling output, first, second and third elements And, the first and second elements OR. pulse generator, delay element, synchronization output, and the output of the first ele

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The AND gate is connected to the first input of the first OR element, contains the first, second, and third control inputs, the operation mode input, information inputs, unique code value inputs, the first decoder with inverse outputs, the first, second, and third triggers, analyzers, the AND element -NOT, the first and second multiplexers, the first and second elements NOT, the second comparison circuit, outputs the number of words, inputs the values of the final address, and the Reset input is connected to the Reset inputs of the analyzers, the first, second binary counters, the first o, of the second and third triggers and with the first input of the second OR element, the output of the pulse generator is connected to the synchronization output, with the first input of the AND element, with the first input of the first AND element, the first input of the second AND element, the first control input is connected to the second the input of the AND gate, the second control input is connected to the second input of the second OR element, the third control input is connected to the first inverse input of the third AND element, with the read enable input of random access memory and with the second input of the first element And, the input of the operating mode reference is connected to the inputs of the analyzer operating mode, the inputs of the unique code value are connected to the first group of inputs of the first comparison circuit, the information inputs are connected to the corresponding inputs of the first decoder, the information outputs are connected to the corresponding outputs of the random access memory, the output of the element And - NOT connected to the synchronization input of the first decoder, the 1st output of the first decoder is connected to the control input of the i-oro analyzer, i 1, m, m + 2nd output of the first the decoder is connected through the first element NOT to the counting input of the first binary counter, the outputs of which are connected to the corresponding inputs of the second decoder, m + the second output of the first decoder is connected through the second element of the HEC with a single input of the first trigger, the output of which is connected to the third inverse input of the And NO and with the second input of the second element AND, the outputs of the second decoder are connected to the corresponding information inputs of all analyzers, the information outputs of the analyzers are connected to the corresponding inputs odes of the first multiplexer, the outputs of the value of the sign of activity of the analyzers are connected to the corresponding information inputs of the second multiplexer,

the outputs of the second binary counter are connected to the address inputs of the first and second multiplexers, with the first group. information inputs of random access memory and with the second group of inputs of the first comparison circuit, the outputs of the first multiplexer are connected to the corresponding inputs of the second group of information inputs of the operational

0 of the storage device, the output of the second multiplexer is connected to the second input of the first OR element and through the delay element to the second input of the third AND element, the output of which is connected to the recording resolution input of the random access memory, the output of the first AND AND element is connected to the counting input of the third binary counter , the output of the first comparison circuit is connected to a single input of the second

0 trigger, the output of which is connected to the signaling output and the third inverse input of the second element And, the output of the second element And is connected to the counting input of the second binary counter, the outputs of the third

5 binary counters are connected to the address inputs of random access memory, the outputs of the -, words, and the first group of inputs of the second comparison circuit, the inputs of the final address value are connected to the second group of inputs of the second comparison circuit, the output of which is connected to the single input of the third trigger, the output of the third the trigger is connected to the third inverse input of the first element AND, the output of the second element OR is connected to the reset input of the third binary counter, the analyzer contains the reset input, the task input ma operation, a control input, data inputs,

0 information outputs, activity attribute value output, element NOT, h element AND, h triggers, h differentiating circuits, first and second binary counters, OR element, threshold element with unit weights of inputs and threshold 2, and the control input through the element NOT connected to the counting input of the first binary counter and the first inputs of the elements I. input Reset connected to the inputs Reset

0 triggers, the first and second binary counters, the information input is connected to the second input of the i-ro element And, the output of which is connected to the unit input of the 1st trigger, the output of the 1st trigger is connected through 5 through the i-th differentiating circuit with {- the input inputs of the OR element and the threshold element, 1 1, h, the input of the operation mode setting is connected to the h + 1-st input of the threshold element, the output of which is connected to the output of the value of the activity indicator, the output of the OR element is connected to the counting input of the binary counter, the outputs of the first and second binary image counters are data outputs of the analyzer.

A disadvantage of the known device is limited functionality, since it does not allow the formation of dictionaries of the most common words.

The purpose of the invention is to enhance functionality.

This goal is achieved by the fact that the input of the cutoff frequency value of the device is connected to the inputs of the same name as the word frequency analysis unit, and the comparison circuit and the element And, the input of the cutoff frequency value of the word frequency analysis unit connected to the first input of the comparison circuit, the second information input of which is connected to the information output of the first counter, and the output of the result is connected to the first input of the element And, the second input of which is connected nn with the output of the threshold element, and the output with the output of the value of the attribute of the frequency analysis block of the occurrence of words.

In FIG. 1 shows a block diagram of a device; in FIG. 2 is a block diagram of a word analysis frequency analysis unit.

The device comprises a device reset input 1, a first gating input 2, a second gating input 3, a third gating input 4, an operation mode setting input 5, information inputs 6, a given word value input 7, an information output 8 of the device, a comparison circuit 9, decoders 10, 11, counters 12, 13, 14, triggers 15, 16, word frequency analysis blocks 17, comparison circuit 18, OR element 19, OR element 20, AND-NOT element 21, AND elements 22, 23, 24, multiplexers 25 , 26, delay element27, memory unit 28, output 29 having a given device word, output 30 count word counts, inputs 31 of the end address value, trigger 32.

The word occurrence analysis unit 17 contains information inputs 33, AND elements 34, triggers 35, differentiating circuits 36, counter 37, inputs 38 of the word boundary frequency values, comparison circuit 39, OR element 40, threshold element 41, counter 42, element 43 And, information outputs of block 44, output 45 of the attribute value, sample input 46.

When describing the device, the following notation was introduced: n is the maximum word length, i.e. maximum number of characters in it, m - maximum number of possible words, p - maximum number of texts.

The circuit elements of the device are interconnected as follows. 5 Input 1 of the device reset is connected to the inputs Reset counters 12,14, blocks of frequency analysis of occurrences of words, triggers 15, 16, 32, with the first input of the OR element 20. The first gating input 2 is connected to the second input of the AND-NOT element 21. A second gating input 3 is connected to a second input of the OR element 20. The third gate input 4 is connected to the first input of the AND element 24, the enable input

5 to read the memory unit 28 and the second input of the element 23 I. The input 5 of the operation mode setting is connected to the inputs of the word analysis frequency analysis units 17. Information inputs 6 are connected to the corresponding

0 inputs of the decoder 10. Input 7 of the value of the given word is connected to the comparison circuit 18. The information output 8 of the device is connected to the outputs of the memory unit 28. The synchronization input 30 is connected to the first

5 by the input of the element 21 AND-NOT, with the first input of the element 22 AND and with the first input of the element 23 I. The synchronization input of the decoder 10 is connected to the output of the element 21 AND-NOT, the -th output of the decoder 10 is connected to the control 0 by the powerful input of the i-ro block 171 of frequency analysis of occurrences of words, the m + 1st output of the decoder 10 is connected to the counting input of the binary counter 14, the m + 2nd output of the decoder 10 is connected to the single input of the trigger 16.

5 The output of the trigger 16 is connected to the second input of the element 22 AND and the third input of the element 21 AND-NOT. The outputs of the binary counter 14 are connected to the corresponding inputs of the decoder 11, the outputs of which are connected to the information inputs of the word analysis blocks 17. The information outputs of the word occurrence analysis unit 17i are connected to the i-th group of inputs of the multiplexer 25. The value output

5 of the activity indicator of the occurrence frequency analysis unit 17i is connected to the lth information input of the multiplexer 26 1t. The outputs of the binary counter are connected to the address inputs of the multiplexers

0 25 and 26, the first group of information inputs of the memory unit 28 and the second group of inputs of the comparison circuit 18. The outputs of the multiplexer 25 are connected to the second group of information inputs of the memory unit 28.

5 The output of the multiplexer 26 is connected to the second input of the OR element 19 and through the delay element 27 to the second input of the AND element 24, the output of which is connected to the write enable input of the memory unit 28. The output of the OR element 19 is connected to the counting input of the binary counter 13. The output of the element 20 OR connected to the input. Reset of the binary counter 13, the outputs of which are connected to the address inputs of the memory unit 28, the outputs 30 of the number of words, the first group of inputs of the circuit is equal to none 9. The inputs of the value of the final address are connected to the second group of inputs of the comparison circuit 9, outputs d which is connected with a unit input latch 32. The output of comparison circuit 18 is connected to the trigger input unit 15, whose output is connected to the third (inverted) input member 22 and output device 29, the presence of a predetermined word. The output of the element 22 AND is connected to the counting input of the binary counter 12.. The output of the element 23 AND is connected to the first input of the element 19 OR. The output of the trigger 32 is connected to the third (inverse) input of the element 23 I.

The inputs 38 of the word boundary frequency values are connected to the corresponding inputs of the word occurrence analysis units 17. The elements of the frequency occurrence analysis unit 17 of the words are connected as follows. The control input 46 of the sample is connected to the counting input of the binary counter

37 and with the first inputs of the elements 34 I.

the i-th information input included in the group of information inputs 33 is connected to the second input of the AND element 341, the output of which is connected to the single input of the trigger 351, the output of which through differentiating circuits 36 is connected to the i-th input of the OR element 40 and the threshold element 41 where: I s, p. Input 1 Reset is connected to inputs. Reset of binary counter 37, 42, triggers 35. Input 5 of the operating mode reference is connected to p + 1-m input of threshold element 41. The output of element 40 OR is connected to the counting input of binary counter 42. Outputs of binary counters 37 and 42 form the information outputs of block 44. The outputs of the counter 37 and the inputs 38 of the word boundary frequency values are connected to the corresponding inputs of the comparison circuit 39, the output of which and the output of the threshold element 41 are connected to the inputs of the AND element 43, the output of which is connected to the output of the attribute value 45.

The device operates as follows.

If there is no need to select the most common words, then the inputs

38 values of the word boundary frequency are given a binary word with ... o, and if necessary, a binary code of the word boundary frequency value. Comparison circuit 39 generates a signal 1 at its output only if the number on

the outputs of counter 37 are greater than the limit value.

Signal O is sent to control inputs 2,3,4 of gating, signal 1 is sent to input 1 of the device Reset, and all memory elements are triggers 15,16,35 and binary counters 12,13,14,37,42, input which are part of the device, are brought into the O state. At the input 5 mode settings

At operation 0, signal 1 is given if it is necessary to determine the union of the sets and O if it is necessary to form a dictionary. The code 1 ... 1 is supplied to the inputs 31 of the value of the final address. The value 7 is supplied to the input 7

5 given words. The device is ready to go.

The process of forming a union of sets consists of three stages:

- the formation of intermediate results,

- recording the meanings and characteristics of words in random access memory,

- output of results to external devices.

5 Initial information - words that are part of lexical sets are entered sequentially, word by word. First, the words of the first text are entered sequentially, then a unique code corresponding to the text separator. Each word is represented as a collection of character codes included in the word. The word is assigned n characters, not less than the maximum possible word length in the processed lexical sets. If the word length is less than n, then all the positions on the right are filled with Space characters. The encoding of the symbols is carried out in such a way that a lower alphabetical value would correspond to a symbol earlier in the alphabet (for example, in accordance with GOST 1976-54). At the end of entering the last text, the code End of Entry is entered,

5 This device allows, depending on the specified operating mode, which is determined by the value of the signal at the control input 5, to combine lexical sets or form a dictionary.

In the first case, which is set to 1 at the control input 5 of the operation mode setting, the lexical sets are combined and the characteristics of the words — rank and repeatability — are determined. The rank of a word is the number of texts; in which it occurs. Repeatability of a word refers to its number in all texts or text. According to the picture said by example.

Suppose there are three lexical sets (some three texts).

T1 - {A, A, B, A}

T2 {B, G. A. V, D}

TK {B, B, A, C, E, E}

where A, B, C, D, D, E are some abstract words.

As a result of combining the indicated lexical sets, we obtain a set T in which all the elements are arranged in alphabetical order, occur only once and have the characteristic of a word: rank and index, which in this example are separated by a period.

T {A.3.4, B.T. 1. B.2.4. D.1.1. D.2.2, E.1.3},

that is, the word A occurs in three texts 4 times, the word B in one text and once, etc.

In order to build a dictionary, it is necessary to remove elements of rank 1 from the set T, i.e. random words occurring in only one text. To do this, at the beginning of the operation of the device, it is necessary to send an O signal to the input of the Operation mode setting 5 and the threshold element 41 is adjusted to the value of threshold 2 and an activity indicator equal to 1 will be generated only for those words that have a rank of two or more.

For the example in question, the dictionary has the form:

TS {A.5.4, B.2.4, D.2.2}

Characterization of words is performed by a word occurrence analysis unit 17. The functional diagram of which is shown in FIG. 2.

The analyzed words are transmitted through the information inputs 8 of the device to the inputs of the decoder 10, at the output of which an inverse unitary code is generated. Each word corresponds to the value of the signal O in a strictly defined position, which is input 46 of the corresponding block 17. Depending on the text number, which is determined by the number of separators, the state of the binary counter 14 changes. In this case, the corresponding unitary code is generated at the outputs of the decoder 11 . For example, for the first text, signal 1 is at the first output of the decoder 11, for the second, at the second, etc. The signals about the output of the decoder 11 are received in all blocks 17 at their information inputs. Each block 17 corresponds to a certain input word and if signal 1 is supplied at its input 46, then this indicates the occurrence of the corresponding word at the outputs 8 of the device. Signal 1 through element 40 of the corresponding block 17 is fed to the counting input of the binary counter 3.7, which counts the frequency of the word and opens elements 34 I. At the inputs 33 of block 17 there is a binary unitary code corresponding to the processed 5 secret text. A single signal puts the corresponding trigger 35 into state 1. If the trigger has already been entered into this state, this indicates that the word being processed is already considered and the word has already been noted in the corresponding trigger 35, therefore, the state change trigger 35 does not occur. This process is repeated for all words of the text. If a new one follows

5 text, a unique text separator code is entered. In this case, at the rn + 1st output of the decoder 10, a value of 1 appears, which arrives at the counting input of the binary counter 14, increasing its content

0 per unit. At the same time, at the outputs of the decoder 11, the unit value is shifted to the next, upward, outputs. In the general case, when processing i-ro text, signal 1 is present at the i-th input of input group 33 and elements 34i, 35i, differentiating circuits 36i take part in determining the presence of j-ro words in i-pm text. 17j. Differentiating chains record the transition of the trigger to states 0 and 1.

0 Counter 37 counts the number of words, and counter 42 counts the number of texts in which the word appears. Signal value of the characteristic 45 is formed only if the signal at the output of the comparison circuit 39

5 is 1 and the signal at the output of the threshold element 41 is 1.

To form the dictionaries, as in the prototype, it is necessary to set the corresponding signal to input 5, to inputs 38 of the code

0 o ... o, to form the most common words on inputs 38, you need to submit a binary code of the value of the boundary frequency of words, with the corresponding value of the signal at input 5.

5

If the text entered is the last text, a unique code is entered at the end of the input. In this case, the rn + 2nd output of the decoder 10 shows the signal 1. Which transfers the trigger 16 to state 1. Since the output of the trigger 16 is signal 1. the element 21 is NAND NOT fixed and the pulses from the output of the pulse generator do not pass t to the output of element 21 AND NOT, but the element

5 22 And it is opened. This ends the first stage of the operation of the device - characterization of words and the next stage begins.

II. Writing the meanings and characteristics of words to a memory unit.

T; c. element 22 And is open, then the pulses from input 30 through element 22 And are fed to the input of binary counter 12, which generates a binary code corresponding to the codes of possible words at its outputs. Depending on the value of the address code, a word characteristic is transmitted to the outputs of the multiplexer 25, i.e. rank and repeatability, and the output of the multiplexer 26 receives the value of the sign of activity. words. If the sign of the word activity is equal to 1, then the signal 1 from the output of the multiplexer 26 enters through the OR element 19 to the input of the binary counter 13, which generates the address of the cell of the memory unit 28, into which the word and its characteristic are recorded, and through the delay element 27 ( the delay amount is determined by the transient time in the counter 13) and the AND element 24 generates a recording enable signal. The word from the output of the binary counter 12 and its characteristics from the output of the multiplexer 25 are recorded in the corresponding memory cell. If the output of the multiplexer 26 is a signal O, then this means that the word in question is absent in the combined sets or when compiling the dictionary it turned out to be random, that is, it was found only in one text and its rank is 1. This process is repeated until until all the words have been analyzed and the state of the binary counter 12 becomes equal to the value of the unique code applied at the beginning of the work to the first group of inputs of the comparison circuit 18 at the inputs 7 of the uni value. code. In this case, at the output of the comparison circuit 18, a signal 1 is formed, which puts the trigger 15 in state 1. which closes the And element 22 for passing pulses from input 30 and simultaneously generates a signal 1 on

signaling output 29, indicating the readiness of the result and writing it to memory. At the outputs 30, the value of the number of words recorded in

memory unit 28. At this point, the second stage of operation of the device ends.

III. Output of results to external devices.

In order to output the results to information outputs 8, it is necessary to apply to the inputs 31 the value of the number of words that was generated at the outputs 30 in the previous operation stage of the device, apply signal 1 (pulse) to the input 3 of the device,

in this case, the counter 13 is set to O, apply signal 1 to input 4 — a read enable signal, which opens the AND element 23 and the pulses from the input 30 through the AND element 23, the OR element 19 enters the counting input of the counter 13, which sequentially generates addresses and outputs 8 generate words and their characteristics. To synchronize external devices that can be connected

to information outputs 8, synchronization output 30 may be used. When the counter 13 reaches a value corresponding to the value of the final address, the outputs of the comparison circuit 9 are formed

signal 1, which sets trigger 32 to state 1 and closes element 23 I. The process of issuing information is completed.

The device allows combining arbitrary character sets, like digital ones. and textual ones, to determine the characteristics of words and form a dictionary, as well as form dictionaries of the most common words. Therefore, the claimed technical solution has wider functionality than the prototype and its application will have a positive effect.

Claims (1)

SUMMARY OF THE INVENTION A device for combining lexical sets containing two decoders, three counters, three triggers, M word frequency analysis blocks (where M is the maximum number of possible words), two comparison schemes, two OR elements, an NAND element, three elements And, two multiplexers, a delay element, a memory unit, an element NOT, with the first inputs of the element NAND, the first and second elements AND connected to the synchronization input of the device, the first and second gating inputs of the device connected respectively to the second input m-NO element 1L and the first input of the first OR gate, the third input of the gating device is connected to a first input of the third AND gate, an input read-resolution block and the second memory .The inputs of the second AND gate, a reset input the device is connected to the inputs of the first and third counters of the same name, frequency analysis blocks for the occurrence of words from the first to the Mth, first, second and third triggers and to the second input of the first OR element, the output of the first trigger is connected to the second input of the first And element, to the output of the presence of the given word of the device, the output of the second trigger is connected to the third input of the first And element and the inverse input of the AND element, the output of which is connected to the sample input of the first decoder, the outputs of which from the first to the Mth are connected to . to the sampling inputs of the corresponding frequency analysis blocks by the occurrence of words, the (M + 1) -th output of the first decoder is connected to the counting input of the third counter, the (M + 2) -th output of the first decoder is connected to the clock input of the second trigger, the output of the third counter is inen with the information input of the second decoder, the output of which is connected to the information inputs from the first through the Mth blocks of frequency analysis of the occurrences of words, the input of the task of the device mode is connected to the same inputs of the frequency analysis blocks of the occurrence of words from the first through the Mth, the information output and the output of the value of the sign of Kth, (K 1, .... M) of the frequency analysis block, the occurrences of words are connected respectively to Km and the information inputs of the first and second multiplexers, and the output of the second multiplexer is connected to the first input of the second element OR OR and through the delay element with the first input of the third AND element, the output of which is connected to the read enable input of the memory blocks, the output of which is the information output of the device, the information output of the first counter is connected to the control inputs of the first and second multiplexers, to the first information input of the first comparison circuit and to the first group of information inputs of the memory unit, the second group of information inputs of which are connected to the corresponding outputs of the first multiplexer, the counting input is first of the counter is connected to the output of the first element And, the input of the value of the given word of the device is connected to the second information input of the first comparison circuit, the output of which is connected to the installation input of the first trigger, the output of the third trigger is connected to the third input of the second element And, the output of which is connected to the second input of the second OR element, the output of which is connected to the counting input of the second counter, the information output of which is connected to the address input of the memory unit, the first input of the second circuit comparing and outputting the value of the word quantity of the device, the second information input of the second comparison circuit is connected to the input of the value of the final address of the device, and its output of the comparison result is connected to the installation input of the third trigger, while the word frequency analysis unit contains a group of P elements I. where P is the maximum number of texts, a group of P triggers, a group of P differentiating chains, two counters, an OR element, a threshold element, moreover, in the frequency analysis block by the occurrence of words, the sample input is connected to the even input of the first counter and the first inputs of the AND elements of the group, the second inputs of which are connected to the corresponding bits of the information input of the block, and the outputs to the installation inputs of the corresponding triggers of the group, the outputs of which are connected to the inputs of the corresponding differential chains of the group, the outputs of the differential chains are connected to the corresponding the first by the Pth inputs of the OR element and the threshold element, the (P + 1) -th input of the threshold element is connected to the input of the job mode setting of the unit, the reset input of which is connected h with the same inputs of the first and second counters and group triggers, the output of the OR element is connected to the counting input of the second counter, the information output of which is connected to the first group of information outputs of the block, the second group of information outputs of which is formed by the corresponding bits of the information output of the first counter, characterized in that that, in order to expand the functionality, the input of the value of the cutoff frequency of the device is connected to the inputs of the same frequency analysis of the occurrence of words, and each block of frequency analysis of the occurrence of words is additionally introduced a comparison circuit and an element And, the input of the boundary frequency value of the block of frequency analysis of the occurrence of words is connected to the first input of the comparison circuit, the second information input of which is connected to the information output of the first Counter, and the output of the result is connected to the first the input of the AND element, the second input of which is connected to the output of the threshold element, and the output - with the output of the value of the attribute of the frequency analysis block of the occurrence of words.