RU1795448C - Rank computing device - Google Patents

Abstract

The invention relates to computer technology and can be used in specialized computers. The purpose of the invention is to simplify the device. The device contains a shift register 1, comparators 2, 3,4,5, four-input adder 6, elements NOT 7, 8, 9, 10, delay elements 11,12,13,14,15, comparators 16, 17, 18, 19, three-input adders 20, 21,22,23. The goal is achieved through the use of charge-coupled devices. 1 ill.

Description

The invention relates to computer technology and can be used in specialized computers and data processing devices.

Known calculator rank data of a numerical sequence containing two switches, sets of storage capacitors, comparators, logic circuits AND, counter, clock, frequency divider, shift register with taps, demultiplexer.

The disadvantages of such a device are that it does not provide a high speed of calculating the rank of the data inside the window when sliding this window along the numerical sequence, since at each window shift the ranks are recalculated without taking into account previous comparisons; the device has large dimensions, since each of its elements is made as a separate unit,

The known device for ranking numbers, selected as a prototype, contains a shift register with (2N + 1J cells and tap from each cell, where (2N + 1) is the number of sorted numbers (window size), 6N comparators, one 2N is an input adder, (2N + 1) delay elements and 2N three-input adders This device works as follows: When a new number arrives in the shift register with taps, this number is compared by the first 2N comparators with the rest of the numbers stored in the register, and 2N - the input adder calculates the welt new number . Grades numbers schihs is already in the shift register are modified trehvhodo- Vym adders using 4N second and third comparators comparing these numbers with ranks ranks vivshegos again by the register and out-of register numbers.

The disadvantages of this device are a large number of such relatively complex electronic components, such as comparators, and the large dimensions of the entire device, since each element is made as a separate unit.

The purpose of the invention is to simplify the device.

This goal is achieved in that in a rank calculator containing a shift register, two groups of comparators, a group of delay elements, an adder, a group of three-input adders, the information input of the shift register being an information input of the device, the output of the first bit of the shift register is connected to the first inputs comparators of the first group, the second input of the 1st comparator of the group, where ... (N-1), N is the number of sortable numbers, connected to the output (i + 1) -ro of the shift register bit, the outputs of the comparators of the first group are connected terms to the corresponding inputs of the adder, the output of the first delay element is connected to the first input of the first comparator of the second group, the i-ro output of the three-input adder of the group is connected to the first input of the (i + 1) -ro comparator of the second through the (1 + 1) -th delay element groups, the second inputs of all comparators of the second group are connected to the output of the N-th delay element, the output of the 1st comparator of the second group

5 is connected to the first i-ro input of a three-input group adder, the second input of which is connected to the i-ro output of the delay element, the input clock of the device is connected to the clock inputs of the shift

0 of the register and delay elements of the group, the outputs of the adder and three-input adders of the troupe form the output of the device, a group of elements is NOT entered, and the outputs of the comparators of the first group through 5 corresponding elements are NOT connected to the third inputs of the corresponding three-input adders of the group.

The introduction of a group of elements is NOT obes. Provides a significant simplification of the device, and therefore, the claimed technical solution meets the criterion of existence. vein differences.

The invention is illustrated in the drawing, which shows a block diagram of a wound calculator.

The device contains a shift register 1 With taps from each cell, a first group of comparators 2,3,4 and 5, an adder 6, elements NOT 7, 8, 9, 10, a group of delay elements 11, 12, 13, 14 and 15, a second a group of comparators 16, 17, 18 and 19, three-input adders 20, 21, 22, 23, the information input of the shift register being the information input of the device.

5 The device operates as follows.

The output of the first bit of the shift register T is connected to the first inputs of the comparators 2, 3, 4 and 5 of the first group, the second

0 i-ro input of the group comparator, where ... (N- 1), N is the number of sorted numbers, connected to the output of the (1 + 1) -th bit of the shift register, the outputs of the comparators 2, 3, 4 and 5 of the first group connected to the corresponding 5 inputs of the adder b and through the elements NOT 7, 8, 9, 10 of the group are connected to the third inputs of the corresponding three-input adders 20, 21, 22, 23 of the group. The output of the first delay element 11 is connected to the first input of the first comparator 16

second group. The i-ro output of the three-input group adder through the (1 + 1) th delay element is connected to the first input (i-H) -ro of the second group comparator. The second inputs of all the comparators of the second group 16, 17, 18 and 19 are connected to the output of the N-ro delay element, the output of the first comparator of the second group 16, 17, 18, 19 is connected to the first input of the i-ro three-input group adder (20, 21 , 22, 23), the second input of which is connected to the output of the i-ro delay element. The input 24 clock pulses of the device is connected to the clock inputs of the shift register 1 and delay elements 11, 12, 13, 14, 15 of the group. The outputs of the adder 6 and three-input adders 20, 21, 22, 23 groups form the output of the device.

After the end of the previous calculation cycle, the ranks of the numbers remaining in shift register 1 are compared with the rank in adder 23 and transferred to the next adder (from 22 to 23, from 21 to 22, etc.). The new number entered in shift register 1 is compared by comparators 2-5 with the numbers already in this register; multi-input adder 6

calculates the rank of this new number, and elements NOT 7-10 generate signals for modifying the ranks of old numbers using adders 20-23, Comparator groups 2-5 and 16-19 work independently of each other, so they can work simultaneously, that is, calculate rank all the numbers in one measure.

Offset shift register, block

adders and delay elements are easily implemented in microelectronic execution on devices with a charge coupling, and comparators on MOS transistors, while the block of adders and delay elements is a shift register with additional electrodes for adding and subtracting the contents of register cells with a single charge package.

Compared with the prototype, the proposed rank calculator, in which the group of elements NOT is introduced, is a simpler device, since simple electronic nodes that perform the function NOT (replacing 0 by 1 and vice versa) replace the relatively complex components in the prototype electronic components as comparators.

Claims (1)

SUMMARY OF THE INVENTION A rank calculator comprising a shift register, two groups of comparators, a group of delay elements, an adder, a group of three-input adders, the information of the shift register being the information input of the calculator, the output of the first bit of the shift register connected to the first inputs of the comparators of the first group, the second input 1st comparator of the group, where, ..., N-1; N is the number of sorted numbers, connected to the output (i + 1) -ro of the shift register bit, the outputs of the comparators of the first group are connected to the corresponding inputs of the adder, the output of the first delay element is connected to the first input of the first comparator of the second group, the i-ro output of the three-input adder groups through the (1 + 1) th delay element is connected to the first input of the (1 + 1) th comparator of the second group, the second inputs of all comparators of the second group are connected to the N-ro output delay element, the output of the 1st comparator of the second group is connected to the first input of the 1st three-input adder of the group, the second input of which is connected to the output of the 1st delay element, the input of the clock pulses of the computer is connected to the clock inputs of the shift register and delay elements of the group, the outputs of the adder and three-input adders groups form the output of the computer, characterized in that which, for the sake of simplification, it contains a group of elements NOT. moreover, the outputs of the comparators of the first group through the corresponding elements are NOT groups connected to the third inputs of the corresponding three-input adders group.