RU1793454C - Device for controlling and receiving information - Google Patents

Abstract

The proposed device can be used to transmit short messages, for example, control commands, between a set of geographically distributed radio stations. The aim of the invention is to increase the noise immunity of the device. The information transmitting and receiving device comprises a message input unit, an encoder, a transmitter, an AND element, a receiver, a decoder, a channel occupancy control unit, a looper, a frequency code generator, a priority generator, an invert unit, a control unit, and a code forming unit. 3 s P. f-ly, 7 ill.

Description

The invention relates to a radio communication technique and can be used to transmit short messages, e.g., codograms.

A known data transmission network is provided for transmitting messages between a master station and several slave stations, each of which contains a transmitter, a receiver and a driver of a control signal.

The disadvantage of this device is that the slave stations do not provide independent entry into communication with the main station, and also have low noise immunity.

A device for transmitting and receiving information is known, comprising a series-connected message input unit, an encoder, a transmitter, the control input of which is connected to the output of the match circuit, a series-connected receiver, decoder and channel occupancy control unit, one input of which is connected to

the output of the receiver, another input connected to the output of the chronizer, the third input connected to the output of the decoder, and the output connected to the first input of the matching circuit, the second input of which is connected to the output of the message input unit.

The disadvantage of this device is its low bandwidth and noise immunity.

The closest in technical essence and the achieved positive effect to the claimed device is a device for transmitting and receiving information.

The prototype contains a receiver, the second input of which is connected to the output of the antenna-feeder system, and the output is connected to the input of the decoder, the first output of which is the output of the information transmitting and receiving device, and the second output is connected to the third input of the channel occupancy control unit, the second input of which connected to the output of the receiver, and the output to the second input of the matching circuit, the output

WITH

L Q

s

4 SL

which is connected in parallel to the third inputs of the receiver and transmitter, as well as to the first input of the message input unit, the second input of which is the input of the information transmitting and receiving device. The first output is connected to the input of the encoder, the output connected to the first input of the transmitter, and the second output is connected to the first input of the priority generator, the output of which is connected to the first input of the matching circuit, and the second input is connected to the first output of the chronizer, the third output of which is connected to the first input of the block channel occupancy control, and the second output is connected to the input of the frequency code generator, the second output of which is connected to the first input of the receiver, and the first output is connected to the second input of the transmitter, the output of which union of the input of the antenna feeder system.

The disadvantage of the prototype is the low noise immunity under conditions of multiplicative interference: ri.

It is an object of the invention D to increase the noise immunity of a device.

The goal is achieved in that in the device for transmitting and receiving information; comprising a transmitter, the output of which is connected to the antenna-feeder system, an information input to the encoder, and the frequency tuning input is connected to the first output of the frequency code generator, the second output of which is connected to the frequency tuning input of the receiver, and the input to the output of the time clock cycle, the output of the busy interval of the channel which is connected to the synchronization input of the occupancy control unit, the channel for which the information input is combined with the input of the decoder and through the receiver is connected to the antenna-feeder system, the equalizing input is connected to the output of the structure of the converted information of the decoder, and the output is connected to the second input of the matching circuit, the output of which is connected to the blocking inputs of the transmitter w of the receiver and the read enable input of the message input unit, the priority code of which is connected to the input by the priority generators, in addition the forming unit, the inverting unit, and the control unit, in which the first input is connected to the Wx ode during the time interval before. dacha, the second input with: the control output of the invert unit, the third input with the information output of this unit, the fourth input with the output of the priority driver, the fifth input is combined with the information input of the invert unit and connected to the information

the output of message input unit 5, the sixth input - with the output of the end of the transmission of the formation unit, the seventh input - combined with the synchronization input of the channel occupancy control unit, the first output connected to the encoder input, the second output to the control input of the formation unit, and the third output to the control the input input of the inverting unit, the fourth output to the first input

0 matches, and the fifth output is to the clock input of the driver, in addition, the information output of the decoder is connected to the information input of the forming unit.

5. The shaping unit comprises a clock generator, the second input of which is the second input of the first match circuit, with the input of the delay line, the output of which is connected in parallel with the second input of the second match circuit and the input of the first match, and co. the second input of the pulse counter output connected to the input of the decoder, the output of which is the second output of the block

5 of formation and connected in parallel with the first input of the clock generator, with the first input of the pulse counter and with the input of the Second inverter, the output of which is connected to the first input of the second

0 coincidence circuit, an output parallel connected to the second input of the second register, the first input of which is connected to the output of the third register, inputs with numbers from 3 to n / 2 + 2 are connected to the outputs

5 of the first register with numbers from 1 to n / 2, and the output is the first output of the forming unit, and with the first input of the third register, whose inputs with numbers from 2 to n / 2 + 1 are connected to the outputs of the first register with numbers from n + 1 to 3 / 2p, the inputs of which with numbers from 2 to 2p + 1 are in parallel connected to the output of the first matching circuit, and the first input is the first input of the forming unit.

5 The control unit contains a first reversible counter, which is connected by the first input to the output of the fourth matching circuit, the second input is connected to the output of the fifth matching circuit, and the output

0 is connected to the second input of the first trigger, the first input of which is the second input of the control unit, and the output is the second output of the control unit and is connected in parallel with the first input of the first

5 of the matching circuit, the second input of which is the third input of the control unit, and the output is the first output of the unit. control, with the second input of the fifth matching circuit and with the input of the first inverter, the output of which is connected in parallel with

the first input of the second matching circuit, the second input of which is the fourth input of the control unit, and the output is connected to the first input of the OR circuit, with the first input of the third matching circuit, the second input of which is the fifth input of the control unit, and the output is the first output of the unit control, with the second input of the fourth matching circuit, and with the second input of the sixth matching circuit, the first input of which together with the first inputs of the fourth and fifth matching circuits is the first input of the control unit, and the output is connected to the first input the tenth match circuit, the output of which is the fifth output of the control unit, and the second input is connected to the output of the second inverter, which also connects the second input of the second OR circuit, the output of which is the fourth output of the control unit, and the second input of the eighth match circuit , the first input of which, together with the first input of the ninth match circuit, is the seventh input of the control unit, and the output is connected to the first input of the second reverse counter, the second input of which is connected to the output of the ninth circuit, coincidence, and the output connected to the first input of the second trigger, the second input of which is the sixth input of the control unit, and the output is connected in parallel with the second input of the ninth matching circuit, the input of the second inverter and is also the output of the control unit;

The invert unit contains a clock generator, the first input of which is the second input of the invert unit, and the output is connected in parallel to the input of the delay line connected to the input of the first inverter and to the first input of the second matching circuit, the second input of which is connected to the output of the second inverter, and the output is connected with the first input of the second register, with the first input of the pulse counter, the output of which is connected to the input of the decoder, the output of which is connected to the second input of the clock generator, with the second the pulse counter, and also is the second output of the inverter, and with the first input of the first matching circuit, the second input of which is connected to the output of the first inverter, and the output is connected to the read inputs of the first register, the input of which is the first input of the inverter, and n information outputs of which are connected to n inputs of the second register, the output of which is the first output of the invert unit.

The invention is illustrated in FIG. 1-7. A block diagram of the claimed device is shown in FIG. 1, where the numbers indicate: 1 - message input unit, 2 - encoder, 5 3 - transmitter, 4 - priority shaper, 5 - chronizer, b - frequency code shaper, 7 - element I, 8 - channel busy control unit, 9 - a receiver, 10 - a decoder, 11 - a code generation unit, 12 - a control unit, 13 - an invert unit, 14 - an input of an information transmitting and receiving device, 15 - an output of an information transmitting and receiving device. The pre-5 codogram forming unit 11 is assigned for receiving and storing the codogram, receiving and storing the inverted codograms, forming the combined codogram and transmitting it to the output 15 of the information transmitting and receiving device.

0 is a block diagram of the forming unit 11 shown in FIG. 2, where the numbers indicate: 16 - the first register, 17 - the second register, 18 - the third register, 19 - the first element And, 20 - the first inverter, 21 5 the second matching circuit, 22 - transmission lines, 23 - the second inverter, 24. - decoder, 25 - pulse counter, 26 - clock generator.

The control unit 12 is designed to coordinate the processes of transmission, reception, inversion, and formation of codograms by creating and transmitting corresponding control signals to other blocks. Block diagram of the control unit

5 to 12 are shown in FIG. 3, where the numbers indicate: 27 - the first element And, 28 - the first trigger, 29 - the first inverter, 30 - the second element And, 31 - the first reversible counter, 32 - the third element And, .3.3 - the fourth element And, 34 - fifth element I, 35 - sixth element I, 36 - second trigger, 37 - second inverter, 38 - second reverse counter, 39 - second OR circuit, 40 - eighth element I, 41 - ninth element I, 42

5 - tenth element AND, 53 - first OR circuit,

The invert unit 13 is designed to receive, store, invert and transmit the codogram in the reverse order

0 to the original. The block diagram of the inverter 13 is shown in FIG. 4, where the numbers indicate: 43 — first match circuit, 44 — first register, 45 — first inverter, 4b — second match circuit, 48

5 - second register, 49 - second inverter, 50 - clock generator, 51 - pulse counter, 52-decoder.

In FIG. Figure 5 shows timing diagrams of the operation of an information transmission and reception device.

In FIG. 6 is a timing diagram of a codogram transmission of a prototype, and FIG. 7 is a timing diagram of transmitting a codogram behind an inventive device.

The device operates as follows. From the output of the chronizer 5 to the input of the frequency code generator 6, a periodic sequence of pulses of a time cycle with a period Tc (Fig. 5a) is received.

When signals TC are received, the frequency code generator 6 generates a transmission frequency code, which from the output goes to the input of the transmitter 3, and a reception frequency code, which from the output goes to the input of the receiver 9 (Fig. 5, b). The transmitter 3 and receiver 9 are tuned to the desired frequencies. Upon completion of the transmitter and receiver setup, from the output of the chroniser 5 to the input of the occupancy control unit of channel 8 and in parallel to the input of the control unit 12, three impulse sequences of time intervals for analyzing the occupancy of channel Ata (Fig. 5c) are received, From the output of the accelerator 5 to the input control unit 12 also receives three pulse sequences of time intervals for transmitting AtK codograms (Fig. 5d). The codogram to be transmitted includes an address part, a priority code, and an information part. On the input bus 14, this codogram is fed to the input of the message input unit 1. In the message input unit 1, the priority code is extracted from the codogram and, in accordance with the priority, a queue is organized that determines the time sequence for transmitting the codograms. From the output of the message input unit 1 code the priority of the transmitted codogram is fed to the input of the priority forcer 4, which introduces the time delay of the transmission of the codogram by a certain value An (Fig. 5d), with a lower priority reading A p ...

At the same time, the signal from the output of the receiver 9 enters in parallel to the input of the channel 8 control unit and to the input of the decoder 10. The decoder 10 encodes the sequence of video pulses arriving at it and extracts the message.

The channel 8 occupancy control unit at the Ata time intervals performs statistical control of the structure of the pulse sequence arriving at it from the receiver 9, for example, according to the parameters of the distribution of the pulse duration and the structure of the converted

information entrance arriving at its input from the output of decoder 10. When revealing the structure of random radio interference, the channel 8 occupancy monitoring unit decides on

the channel is idle and from its output to the input of the And element 7 a single signal is supplied. In the case of revealing the structure of the interfering signal, a decision is made on the channel occupancy and a zero signal is issued to the second input of the And 7 element.

The signal from the output of the priority driver 4, indicating the presence of a codogram ready for transmission, is fed to the fourth input of the control unit 12. C

5 of the fourth output of control unit 12, a signal is supplied to the input of element And 7. If the channel is busy, then element And 7 is closed by a zero signal from the output of the control unit of channel 8 and the next coding

0 will be in the queue either until the end of the current codogram transmission cycle or until the communication channel is released. If the communication channel is free, then the element And 7 is open and the receipt of a single signal on it

5 input leads to the appearance of a single signal at its output. The signal from the output of element And 7 is simultaneously fed to the input of the message input unit 1, to the input of the transmitter 3 and to the input of the receiver 8. This signal 0 locks the second input of the receiver 9, the transmitter 3 is turned on by radiation, and from the output of the message input unit 1, the codogram is sent to the input of the invert unit 13 (Fig. 5, e) and the input of the unit

5 of control 12. From the output of control unit 12, the codogram is fed to the input of encoder 2 in the same sequence, i.e., the first. The first bit of the codogram is fed, in which the codogram is fed to the input of the control unit (Fig. 5e). From the output of the encoder, the encoded codegram is input to the transmitter and then transmitted to the correspondent. At the receiving end of the radio lines from the output of the receiver 9, a codogram is received

5 is fed to the input of decoder 10. From the output of decoder 10, the decoded codegram is fed to the input of block 11 and stored in it (Fig. 5g).

The transmitting part of the radio link transmits the inverted codogram as follows. From the output of control unit 1.2, a single signal is fed to the input of invert unit 13. From the output of unit 13, the inverted codogram

5 (Fig. 5f) is fed to the input of the control unit 12. Further, from the output of the control unit 12, the inverted codogram is fed to the input of the encoder 2, where it is encoded and sent to the input of the transmitter 3, which transfers it to the correspondent. On the

the inverted codogram is received at the receiving end of the radio line from the output of the receiver 9, and fed to the input of the decoder 10, From the output of the decoder 10, the decoded inverted codogram is fed to the input of the forming unit 11 and stored in it. From the output of the forming unit 11, a single signal is fed to the input of the control unit 12. From the output of the forming unit 11, the generated codogram is sent to the output 15 of the information transmitting and receiving device. This completes the cycle of transmitting and receiving the codogram.

The forming unit 11 (Fig. 2) operates in such a way that the copies of the codogram recorded in the first register 16 (direct and inverse) are rewritten in the second register 17 and the third register 18 by the signal received at the input of the block 11. The rewriting takes place as follows.

The signal supplied to the input of the forming unit 11 starts the clock generator 26. From the output of the clock generator 26, the first pulse is simultaneously fed to the input of the block 19, to the second input of the pulse counter and to the input of the delay line 22, which delays the signal by one clock cycle . Since there is no inhibitory signal at the input of element And, the pulse goes to the read inputs of the first register 16. Moreover, in order for the sequence of information pulses in the combined codogram to correspond to the original, the first half of the codogram from 1 to p / 2 of the outputs of the first register 16 is received to the inputs from 3 to n / 2 + 2 of the second register 17, respectively, and is stored in it. The second part of the codogram from n + 1 to 3 / 2n outputs of the first pernctpa 16 goes to inputs 2 to n / 2 + + 1 of the third register 18, respectively, and is stored in it. Then, from the output of the delay line 22 through the block 21 with a delay of one clock cycle to the input of the second register 17 and to the input of the third register 18, read pulses start to arrive in parallel and the codegram is sent to the output of the forming unit 11 in the required sequence. In addition, from the output of the delay line 22 through the inverter 20, the pulses are fed to the input of the block 19 and prohibit the passage of the second and subsequent read pulses through it. As soon as the decoder 24 determines that the state of the pulse counter 25 is (n + 1), a signal is generated at the output of the decoder 24, which is simultaneously fed to the input of the clock generator 26. to the input of the pulse counter 25 and through the inverter 23 to the input of block 21, thereby prohibits the operation of the clock generator 26, nullifies the pulse counter 25 and prevents the passage of read pulses through block 21 to the inputs of registers 17 and 18. At this block 11

stops working in this cycle of transmitting the codogram.

The control unit 12 operates (Fig. 3) as follows.

In the initial position, the trigger 28 and

trigger 36 is in the zero state, respectively, the output of the first inverter 29 and the output of the second inverter 37 will be single signals.

At the input of the control unit 12 from the chroniser 5, a pulse sequence of the time interval At is received. Through block 35, opened by a single signal from the output of the inverter 29 and block 42, opened by a single signal from the output

of the inverter 37, the pulse train of the time interval is supplied through the output of the control unit 12 to block 4, through the block 33, opened by a single signal from the output of the inverter 29, this pulse train A tic is fed to the input of the reverse counter 31 and fills it. Upon completion of the reverse counter 31, a single signal from its output is fed to the input of trigger 28 and puts it in a single state. In this case, a zero signal is generated at the output of inverter 29, which closes the passage of signals through block 30, block 32, block 33, and block 35. A single signal from the output of trigger 28

opens block 34, thereby ensuring that the next sequence of pulses AT.K arrives at the input of the reverse counter 31. The next sequence of pulses AtK arriving at the reverse input of the reverse counter 31 resets it.

The input of the control unit 12 receives a single signal from the output of the invert unit 13. This signal is received after

completing the transmission of the inverted codogram. It transfers trigger 28 to its initial zero state, preparing it for the next cycle of work.

The input of the control unit 12 from the unit

13 the inverted codogram arrives. Through the block 27, opened by a single signal from the output of the trigger 28, the inverted codogram is fed through the output of the control unit 12 to block 2,

The control unit 12 receives a signal from the output of the priority driver 4, which carries information that the next codogram is ready for transmission. This signal, passing through block 30, opened by a single signal from the output of inverter 29 and through a second OR circuit, enters through the output of control unit 12 to the block

. : -I-th: -b;: / :: y - l:; - ;:.; -: .. f. L At the input of control unit 12, the next codogram is received from the output of message input unit -1. This codogram, passing through block 32, opened by a single signal 11 from the output of inverter 29, is output to the control unit 12.

At the input of the control unit 12, a single signal is received from the output of the forming unit i1, This signal comes after the generated ncf-codogram steps onto the Bbixojai 15 of the information transmitting and receiving device, It transfers the trigger 36 to: similar to the zero state, his; to the next work cycle. The input of the control unit 12 from block 5

pulse sequence arrives

temporary-interval

open with a single output signal

V invertra: 37;, this after; confidence by impulse: arrives at the reverse

counter 38 and fills it, by filling

- ё: ae; r..sDetc. IC: a -38 /. unit 1 signal s; its EXIT post | t n: a; trigger input

36 and translate e g to a single state.

At the same time, a zero signal is generated from the inverter's

  about xp kdenyyo sygyalov; through the OR 39 scheme and block 42 and leads to the right

 . Ya in Ukhrdy blray control -12. Either (a null signal from the output of trigger 3.6 closes block 46 and opens block 41, ensuring that the next sequence of spools of micropulses arrives at the input of the reverse counter .38. ;; The following pulse sequence Ata entering the reverse input of counter 38 zeroes it. /;.: J .-- - ..;: /.; B ok; inverting .13 (Fig. 4) work-; it is as follows.: - -6:.;, .;::. / - /: b; 1 (od | p. a m) Ts aGpstu: more often from block 1 to the input, it is recorded and stored in register 44. The signal from block 12 to the input of the inverter 13 starts the clock generator 50. From the output of the clock generator 50, the first pulse is simultaneously fed to the input of block 43, to the input of the pulse counter 51 and to the input of the delay line 46, which delays the signal by one clock cycle. there is no inhibitory signal, then the pulse parallnb arrives

and ri is the entrance to the chyvayig, NaMyya from the second to the h-AND entrance, register 44.; J

As a result, the codogram from register 44 enters parallel to register 48. From the output of the delay line 46 through block 47 and

readout delay and one clock cycle, read pulses and a codogram begin to arrive at the input of register 48, starting from the last bit, i.e., in the reverse, inverse order, it enters 5 through the output of invert unit 13 to block 12. In addition, from the output of the delay line 46 through the inverter 45, the pulses are fed to the input of block 43 and prohibit the passage through it of the second and subsequent 0 read pulses. As soon as the decoder 52 determines that the state of the pulse counter 51 is (n + 1), a signal is generated at the output of the decoder 52, which is simultaneously fed to

5 ; the input of the clock generator 50 to the input of the counter is pulsed to 51 and through the inverter 49 to the input of block 47, thereby inhibiting the operation of the clock generator 50, resetting the counter 51 and inhibiting the passage of read pulses through block 47 to the input of register 48. On this unit 13 stops working in this cycle of transmission of the codogram,

To evaluate the increase in technical efficiency; That is, an increase in noise immunity, functioning in conditions

the multiplicative interference of the claimed device in comparison with the prototype can be as follows. ..:

0 The device for transmitting and receiving information 7 uses various radio channels, including those in which: the propagation of the transmitted signals from the transmission point to the receiving point occurs, according to

5 different paths (rays). Different paths have unequal lengths, and therefore the vibrations simultaneously reaching the receiver have different phases. This leads to the appearance of a multiplier of 0 t1 / 1 full. ;:. :; : .-

The known device assumes as a method of dealing with multiplicative noise repeated q-fold transmission of the codogram, up to the end

5 of the transmission cycle of the codogram, A similar algorithm for the operation of the known device is not taken into account, taking into account such a significant feature of the effect of multiplicative noise as the presence of a delay time t3. In that

0 if the transmission time of the codogram Tkdg is in the interval t3 1kdg 2t3, then for successful transmission of the codogram it is sufficient to transmit it twice. In this case, the retransmission of the codogram should

5 is present in such a way that, in the first transfer, if you search, part of the codogram is forward; there is 8 first in time 1 less than time t3. Such an algorithm is the basis for functional operation; go device.

Let us compare both functional algorithms: according to such an indicator as the frequency of erroneous reception of a Roche signal element under conditions of multiplicative noise during the codogram transmission cycle. For a known device that implements the multiple direct transmission mode, we denote this indicator as PI er. For the inventive device that implements the double transmission mode of the codogram with inversion, we denote this indicator as P 2 er. In order to evaluate Rh.o. and P2.o.h., we consider the timing diagrams of the codogram transmission by the known device and the claimed device, which are shown in FIG. 6. The frequency of erroneous reception of a signal element can be estimated by the following expressions:

Ј

i 1

m i

q p

(2)

mi is the number of bits of the codogram affected by the multiplicative noise in 1st gear,

5l € {1 (1) q}

Obviously, Pioiu.s

102. m i

A ROSH.Z Ploui.9 P2osh.e,

(4)

For example, for the case of V 2.4 k bit / s, 15 ta - 3 ms and q - 12, we have 1kdg - 6 ms, n - V x x 1kdg 14 bits,

i

GP |

0

mi m n

t 3-t A P I 1

 7, A ROSH.E

10 -7 12 14

t KDG

q P

 0.42.

P2

m t + m 2 q n

(3)

where q is the number of transmissions of the codogram during one transmission cycle,

p is the volume of the codogram in bits,

Claims (4)

The claims 1. A device for transmitting and receiving information, containing a message input unit, the first input of which is the input of the device, the second input is combined with the first inputs of the transmitter and receiver and connected to the output of the element And, the encoder, the output of which is connected to the second input of the transmitter, the third the input of which is connected to the first output of the frequency code generator, the input of which is connected to the first output of the chronizer, the second output of which is connected to the first input of the channel occupancy monitoring unit, the second input of which is connected It is connected to the output of the receiver and combined with the input of the decoder, the first output of the decoder is connected to the third input of the channel occupancy control unit, the first input of the element And is connected to the output of the channel occupancy control, the first output of the message input unit is connected to the first input of the priority driver, and the second output of the driver the frequency code is connected to the second input of the receiver, the third input of which is connected to the receiving antenna, the output of the transmitter is connected to the transmitting antenna, therefore, the noise immunity of the operation under multiplicative noise of the claimed device becomes higher than the known device, the amount A ROSH.E. which, in order to increase the noise immunity of the device, the codogram forming unit, the control unit and the inverting unit are introduced into it, the first input of which is connected to the second output of the message input unit and combined with the first input of the control unit, the first input of the coding unit is connected to the second output of the decoder, the second input of the control unit is connected to the third output of the chronizer, the third input is connected to the first output of the inverter, the second output of which is connected to the fourth input of the control unit, the fifth input of which is connected to the output of the priority driver, the sixth and seventh inputs of the block controls are connected to the first output of the coding unit and the second output of the chroniser, respectively, the first output of the control unit is connected to the input of the encoder, the second and third outputs of the block the controls are connected to the second inputs of the coding unit and the inverter, respectively, the fourth and fifth outputs of the control unit are connected to the second inputs of the And element and the priority driver, respectively, the second output of the forming unit is the output of the device. 2. The device according to claim 1, the clause that the codogram forming unit comprises first, second and third memory registers, first and second AND elements, first and second inverters, a delay element, a decoder, a pulse counter and a clock generator, the first input of the first memory register is the first input of the coding unit, the first input of the clock is the second input of the coding unit, the second input of the clock is combined with the first input of the pulse counter the house of the second inverter is connected to the output of the decoder and is the first output of the coding unit, the output of the clock generator is connected to the second input of the pulse meter, the first input of the first AND element and the input of the delay element, the output of the pulse counter is connected to the input of the decoder, the output of the second inverter is connected to the first input of the second element And, the second input of which is combined with the input of the first inverter and connected to the output of the delay element, the output of the first inverter is connected to the second input of the first ele ment And, the output of the second element. And. connected to the first inputs of the second and third memory registers, the output of the third memory register is connected to the second input of the second memory register, the output of the first element And is connected to the combined inputs of the group of the first memory register, the first outputs of which are connected to the corresponding inputs of the second group memory register, the second outputs of the group of the first memory register are connected to the corresponding inputs of the groups of the third memory register, the output of the second memory register is the second output of the encoding unit. 3. The device pop. 1, characterized in that the invert unit comprises a clock, pulse counter, decoder, first and second inverters, delay element, first and second elements And, first and second memory registers, the first input of the first memory register is the first input of the block inverting, the first input of the clock is the second input of the inverter, the combined second input of the clock, the first input of the pulse counter and the input of the second inverter are connected to the output of the decoder, which ing is the first output of inverting block clock generator is connected to the output the second input of the pulse counter, with the first input of the first element And and the input of the delay element, the output of which is connected to the first input of the second element And to the input of the first inverter, the output of which is connected to the second input of the first element And, the output of the pulse counter is connected to the input of the decoder, output the second inverter is connected to the second input of the second element And, the output of which is connected to the first input of the second memory register, the output of the first element And is connected to the combined inputs of the group of the first memory register, group outputs s are connected to respective inputs group of the second memory register, the output of which is the second output of the invert unit, 4. The device pop. 1, characterized in that the control unit comprises first and second reversible counters, first and second triggers, first and second inverters, first to tenth AND elements, first and second OR elements, the first input of the third AND element is the first input control unit, the first inputs of the fourth, fifth and sixth elements AND are the second input of the control unit, the first input of the first trigger is the third input of the control unit, the second input of the first trigger is connected to the output of the first reversible counter, the first and second inputs of which are connected respectively to the outputs of the fourth and fifth elements AND, the output of the first inverter is connected to the first inputs of the second and third elements AND and with the second inputs of the fourth and sixth elements AND, the output of the first OR is the output of the control unit, the output of the first trigger is connected to the second input of the fifth element And, the input of the first inverter, the first input of the first element And is the second output of the control unit, the second input of the first element And is the fourth input of the block control, the output of the first AND element is connected to the first input of the first OR element, the second input of which is connected to the output of the third AND element, the second input of the second AND element is the fifth input control unit, the output of the second AND element is connected to the first input of the second OR element, the second input of which is combined with the first input of the ninth element I. the input of the second inverter and is connected to the output of the second trigger, the output of the second trigger is the third output of the control unit, the first input of the second trigger is the sixth input of the control unit, the second input of the second trigger is connected to the output of the second reverse counter, the combined first input of the eighth element And and the second input of the ninth element And is are the seventh input of the control unit, the outputs of the eighth and ninth elements From% And connected to the first and second inputs of the second reversible counter, respectively, the output of the second inverter is connected to the second input of the eighth element and the first input of the tenth element And, the second input of which is connected to the output of the sixth element And, the outputs of the second element And / 1I and the tenth element And are appropriate. fourth and fifth outputs of the control unit. 9ig. 2. Wfreen frswjea ut. 5 Fig 7.