RU1791956C - Voltage oscillator - Google Patents

Abstract

Usage: the invention relates to a pulsed technique and is intended to generate circular scan voltages with or without a displaced center and pedestals and coordinate point voltages and can be used to construct function-oriented control processors for the Electron-beam vector indicator, for example, for weather radar . The inventive device comprises: differential-analog converters 1, 2, digital integrators 3, 4, counter 5 pulses, trigger 6, element NAND 7, registers 8, 9, decoder 10, elements 11-15, buses: 16 -data, 17-address, 18-record, data, 19 and 20 - start and 28 - clock pulses. The description shows the design of digital integrators, as well as timing diagrams that explain the operation of the device and the necessary vector diagrams. 1 s.p. F., 4 yl. (L C

Description

The voltage generator belongs to the pulse technique and is designed to generate circular scan voltages with or without a displaced center and pedestals and coordinate point voltages and can be used to construct a functionally oriented processor (PF) for controlling the electron beam TM vector device indicator Information display (UOI) of complex infarction data (systems like weather radar (MPJrjJJ..:. 1:

In the structure of the modern magnetic resonance arrays, you can / highlight a vector indicator on a CRT tube with two-coordinate electromagnetic control of the position of the CRT beam and its modulation of brightness, a keyboard for controlling the operating modes of the AOI, a marker coordinate sensor, an operator codogram generator and an OTF for communication of the OOI with other subsystems of the SLL and indicator management during the synthesis of the information model of the situation in the Sightseeing Zone of the SSC, and a number of devices can be distinguished as part of the POP, c. these include an input-output device, a character generator: and a voltage generator for controlling the position of the indicator beam, respectively, by two coordinate and two character inputs, a compression device to fill in the primary information as it arrives at the POP and output it to the corresponding video inputs an indicator of compressed primary information with the speed of operation of the OOI, a video signal generator of image constants for outputting video signals indicator, for example, the azimuth-scale scale grid, to the video inputs nd memory device for digital information (MPL antenna azimuth code, operator codograms, secondary information codograms, etc.), a function generator for generating codes of the required constants and sine, cosine, artktangens and arc tangent functions, a microprocessor for performing all the required arithmetic and logical operations , a program control device, a synchronization device and time programs and a data bus (ST), address (ST) and control (ST), by which information is transmitted and processed in the POP, In the process of forming an information model, the pace of the operation of the IOI is organized according to To cycles. each of which consists of periods of forward TPx and reverse Tox moves, with TV .Tnx + Т0х 1 / fo. Where

fo is the pulse repetition rate of the start-up pulse.

The presence of a compression device in the POP allows the display of primary information with the start frequency fa -fa. no more than the frequency f3 of the probing pulses of the SXR with a minimum duration Tx, which does not depend on the range of the SXR and is determined only by the maximum speed of the vector on the UOI screen, which makes it possible to increase the time Tox T0 - Tpx to display secondary information and prepare for the next TLC to display the primary

5 information. In this regard, in order to display combined primary and secondary information in a PDO, a voltage generator is needed to generate stresses or a coordinate point, or a circular scan with an offset center, and the circular scan voltages during the display of the primary information must be formed with pedestals to combine with the required accuracy with coordinate points of secondary information, and when displaying vectors of secondary information without pedestals, for example, when displaying the required lines with arbitrary curvature oh by approximating each line CP0 vokupnostyo vectors so that each vector are programmed for its start, length (distance) and direction (azimuth).

The aim of the invention is the expansion of functionality through

5 to provide the ability to generate sweep voltages with a displaced center and pedestals while simplifying the generator.

In FIG. 1 and 2 are electrical

0 functional diagram of the voltage generator; Fig. 3 is a diagram explaining the principles of displaying information in a VOI with a vector indicator: Fig. 4 is a timing diagram of the operation of a voltage generator 5 when displaying information in a VOI.

The voltage generator contains the first and second digital-to-analog converters 1 and 2, the first and second digital

0 integrators 3 and 4, the outputs of which are connected respectively to the inputs of the first and second digital-to-analog converters 1 and 2, the outputs of which are connected respectively to the first and second output buses 5 mi, 5 pulse counter, trigger b, AND-NOT 7 element, the first and the second storage registers 8 and 9, the decoder 10, the first to fifth elements And 11-15, the data bus 16, the address circuit 17, the data recording bus 18, the first and second buses, 19 and 20 start, with

the first through seventh outputs 21--27 of the decoder 10, the bus 28 clock pulses and the third output bus connected to the output of the trigger bis the first input of the element AND-NOT 7, the second input of which is connected to the bus 28 clock pulses, and the output is connected to the clock inputs of the first and the second digital integrators 3 and 4 and with a subtracting input of the pulse counter 5, the output of which is connected to the clock input of the trigger b, the information input of which is connected to the common bus, the reset input is to the data recording bus 18 and to the decoder synchronization input 10, information whose ion inputs are connected to the address bus 17, the first output 21 of the decoder 10 is connected to the first inputs of the first and second elements And 11 and 12, the outputs of which are connected respectively to the recording input of the first storage register 8 and to the first recording input of the first digital integrator 3, the second output 22 of the decoder is connected to the first inputs of the third and fourth elements And 13 and 14, the outputs of which are connected respectively with the recording input of the second storage register 9 and with the first write-back of the second digital integrator 4, data bus 16 is connected inena with information inputs of the counter 5 pulses, through the first and second storage registers 8 and 9 with the first group of information inputs of the first and second digital integrators 3 and 4, respectively, directly with the second groups of information inputs of the first and second digital integrators 3 and 4, the second recording inputs of which are connected respectively to the third and fourth outputs 23 and 24 of the decoder 10, the fifth, sixth and seventh outputs of which 25, 26 and 27 are connected respectively to the second input of the first element; And 11, with the second input of the third element And 13 and with the recording input of the counter 5 pulses, while the trigger input 6 is connected to the output of the fifth element And 15, the first input of which is connected to the first start bus 19, the second move to the second inputs of the second - horn and the fourth elements And 12 and 14 and with the second launch bus 20.

The digital integrator 3 or 4 comprises a reversible pulse counter 29, an adder 30, first and second storage registers 31 and 32, first and second elements. HE 33 and 34 and the first and second elements AND are NOT 35 and 36.

When describing the work, we denote at the inputs and outputs of the voltage generator and its components through Φ, P or P, I or I and H, respectively, codes that are direct or

potential inverse signals, direct or inverse pulses, and analog voltage so that after each of these letters is the generator bus number, or the component number of the generator, or the output number of its component, for example, Ф16 is the code on the data bus 16, P32 - direct signal at the output of the sign bit of the storage register 32, - inverse signal at the output of the element NOT 33. And 28 - direct pulses on the bus 28 of the current pulses, I18 - inverse pulses on the data recording bus 18, 1419 and I20-inverse pulses on the first and second start buses 19 and 20, respectively Twain, H1 and H2 - analog output voltages respectively at the outputs of the first and second digital to analog converters 1 and 2, etc.

The serial components of the voltage generator operate so that the trigger 6 is installed in О (in 1) directly ГУ18 (according to И15), at the end of the pulse And5 of the borrowed 5-pulse counter, the trigger 6 switches from 1 to. Oh, asynchronous recording (recording) of the corresponding codes (over the slash crossing the code buses of the generator of FIGS. 1 and 2, the parentheses of these buses are shown in parentheses (counter 5, register 8, register 9 and counter 29 of the digital integrator 3 or 4 are made directly during the operation of pulses I27.I11, Ts13 and I12 or 1414, synchronously write code F16 to register 32 and directly set register 31 to state F31 10.,., 5 (i.e., the high-order bit of code F31 has weight 2) the digital integrator 3 or 4 is produced respectively 23 or I24. Synchronous recording of code. FZO of adder 30 to register 31 is performed at the end of each I7, synchronously decrease the contents of the counter 5 pulses at the end of each I7, and synchronously increase or decrease the contents of the reverse counter 29 pulses is performed at the end of each 1435 or accordingly.

Temporary programs for generating input codes and signals of the voltage generator F16, F17, I18-Y20 and I28 determine the time programs for generating its output voltages H1 and H2 so that the following five modes can be distinguished in the generator: the first mode of duration T , 1 - the mode of preparation for the formation of circular-voltage voltages with an offset center and pedestals for displaying primary information: the second mode lasting

T2 — the mode of preparation for the formation of the scan vector voltages with programmable beginning, length (range) and direction (azimuth); the third mode with a length of TK - the mode of preparation for the formation of the vector scan voltages with the beginning being the end of the previous vector and with programmable length and direction; the fourth mode of duration T4 is a mode of generating voltages, sweeps to display either primary information when starting on I20, or a vector of an approximated line when starting on I19; the fifth mode of duration T5 is the mode of generating voltages of the position of the character familiarity (points, numbers, letters or special characters) of secondary information. :.

The alternation of the operating modes of the voltage generator is ensured by the mutual synchronization of its input codes and signals (i.e., by devices of software adjustment, synchronization, and time-dependent phase response functions) and is carried out so that after each first mode there follows a fourth mode according to I20, after every second or of the third mode, the fourth mode follows. I.19. After every fourth mode, any mode can be followed / except for the fourth, and after every fifth mode can be followed by any of the modes except the fourth mode, for example, and figure 4 shows the sequence of modes: T1-T4-T2-T4-TZ-T4-TZ-T4-T5-T5.: ..

The indicated five operating modes of the generator make it possible to display the primary information in TUI during Tx T4 of 1/120 during the formation of a circular scan line on the screen that simulates the position in space of the probing beam of the SRL, and during Toh To - Tpx in 1/120 display secondary information, for example, lines with arbitrary curvature, approximable by vectors with programmable start, length and direction, and the corresponding formulas using jump-like movements of the indicator beam in each familiarity formulas ra consisting of one or more characters - see figure 3,

In the operation process of the UOI, the position of the indicator beam is controlled in two mutually perpendicular directions so that when I1 Н2 О В the beam is in the center of the screen, and in any other case it is at the point of the screen, the position of which is measured from the center along the first (vertical) rectangular coordinate XD cos А and the second (horizontal) rectangular coordinate Y .D sln А are proportional to the voltages Н1 and Н2, respectively, where X and Y are rectangular, and D and А are polar coordinates coordinate system of the indicator,

and the coordinate (azimuthal angle) A

 counted from the axis of the X coordinate in a clockwise direction - see FIG.

0 In this regard, to indicate the codes of the corresponding coordinates, the following symbols are used: Xn and YH are additional codes of rectangular ordinates or the center (beginning) of the scan for

5 displaying primary information, or the familiarity of a secondary information symbol, or the beginning of a vector for displaying secondary information; Xn and Yn - additional codes of pedestals rectangular

0 scan coordinates when displaying primary information; A is the code of the angle A, which determines either the position of the MRL antenna in azimuth or the direction of the secondary information vector; up-code length (range

5 or duration) sweep when displaying / or primary information, or a vector of secondary information .;

In view of the foregoing, let us first consider the functioning of the individual components of the generator, and then its operation as a whole. ; -. -, ..: ..-. ., ..

The decoder 10 on the pulse 1/118 and the code F17 000 produces: when F7 001 they are pulses I21 write the code F16 Xn to register 8 and

5 counter 29 digital integrator 3; Poi F17 010 pulse I22 write code F16 Un to register 9 and counter 29 of digital integrator 4; with an impulse I23 setting registers 31 and 32 of the digital integrator 3

0 in state F31 10 ... I.F16 П32Ф32 КЗК1 ... Кп cos А respectively, where П32 Кз is the digit digit of the sign bit, and Ф32 К1 ... КП are the remaining digit digits of the direct KOjgajiocHHyca of angle А ;

5, at F7 100, pulse I24 of setting registers 31 and 32 of digital integrator 4 in the state Ф31 10.,. 0 0.5 and Ф16 П32Ф 32, СзС1 ... Cs sin А, respectively, where П32 Сз is the digit digit yes, and F32 C1 ... Cn - the remaining bit digits of the direct code of the sine of angle A; when f 1pJ pulse I25 write code F16 register; at Ф7 110, pulse И26 of code recording Ф16 ° Y.H + Yn in

5 register 9; with F7 111, the pulse I27 of the record F1 b Dr - 2 in the counter 5.

From the pulses I19 and 1/120 of the trigger and the pulses I21, I22, I25 and I26 of the decoder 10, the elements 11-15 generate pulses in accordance with the expressions

I11 I21 UI25,

1/112 I21 VH20,

L

I13 I22 VH26,

P)

I14 I22 UI20,

I15 I19 VH20.

Register 8 ylid9 serves either to memorize the code Ф8 Хн + Хп or the code Ф9 YH + Yn on I25 or I26, respectively, for its subsequent transfer to the counter 29 of the digital integrator 3 or 4 by И12 И20 or И14 И20, respectively, or to transmit the code Ф16 AN or F1.6 YH a counter 29 of the digital integrator 3 or 4 according to I12 I21 or I14 I22, respectively.

Counter 5, trigger 6, and the AND-NOT 7 element serves to generate pulses I7 P6 I28, which are the result of the operation of converting the binary code Dp recorded by I27 into counter 5 in the form of the code F16 Dp - in the first, or second, or third mode, into a number-pulse code, representing during T4 (i.e., in the fourth mode) a uniform pulse sequence I7, the number of pulses in which is

Chi7 2p Dr 2

P .

i 1

DG2L (2)

where D | - the digit digit O or 1 of the 1st digit of the codederer I, varying from 1 to n ...;

In this regard, before the beginning of each T4 period, the counter 5 contains the code Ф5 Др - 2, and according to the start pulse I15 И19 V И20, which does not coincide in time with И28, trigger 6 is set to 1 and during Т4 it generates signal П6 .1, with the resolving element И-Нё 7 impulses I7 or I28. During T4, the contents of counter 5 are reduced by 1 at the end of each I7. Therefore the counter

5 according to the last I7 forms the pulse I5 of the loan, at the end of which the trigger

6 is set to 0 cm. FIG. 4 e, g, h, and, k.

The digital integrator 3 or 4 serves either to store an additional code Xn or YH of the rectangular coordinate Xn or YH of the familiarity of the secondary information symbol, or to generate an additional code X or Y of a rectangular coordinate X or Y of a circular scan when

0

5

0

5

un-hen

display or primary information, or a vector of secondary information.

The initial installation of the memory device of the digital integrator Zp24 (or 4) is carried out according to I12 I21 V I20 and I23 (or I14 I22 V I20) and in the state indicated in the description of the operation of the decoder. 10 and register 8 (or 9). Therefore, before the start of the fourth mode, digital tegrarators contain the codes ФЗ Ф31з 0,5, П32Ф32з КзК1 ... Кп, Ф4 Un, Ф314 OV5, П32Ф324 СзС1 ... СП, and at the beginning of the fourth mode, digital integrators generate codes ФЗ Хн + Хн, respectively -L6-I20 and F4 YH + + Yp-Pb I20, where the P6-I20-logical variable is 1, when starting on I20 and equal to O when starting on I19 and stores this value for 74, in which the elements AND-NOT 35 and 36 of the digital integrator 3 or 4 using I7 pulses (during T4, the number of these pulses varies from zero to the number Chit defined by the expression (2)) generate pulses

I35 P32-I7-PZO,

I36-.P32-I7-PZO

(3)

the number of pulses is the code for changing the contents of the integrators 3 and 4, the weight of each pulse of the ISB (or I36) is 2-p (or -2-p), and the number of pulses is determined in accordance with the expressions

Чз5 П32-ёп В-Чд + 0.5, Чзб П32-е В-Чд + 0.5,

(4)

40 where PZO - transfer signal of the adder 30; Gkz for integrator 3;

P32. . .

1C3 for integrator 4;

45

l

AT

ilcos A (- for integrator 3,

sfn A | -for integrator 4;

BH - the current number of pulses I7 during T4;

ent is an operator to select the integer part of a number enclosed in square brackets.

Expressions (4) are the result (number of pulses I35 and I36) of multiplying the binary direct cosine (or sine) code for the digital integrator 3 (or 4) by the binary code D (t) -BH, represented during T4 number-pulse code (i.e., I7 pulses), moreover, the error of the multiplication operation (4) is distributed approximately according to a uniform law with parameters

M 0,, 5 / Uz,

where M and o are respectively the mathematical expectation and the mean square value of the error of the multiplication algorithm (4). Taking into account (4), we find that during T4, digital integrators 3 and 4 generate additional codes of rectangular coordinates X and Y in accordance with the expressions d Л. ФЗ Х Хн + Хп-Пб-И20 +

+ (KZ-Ch35z.- KZ-Ch36z),

Ф4 Y YH + Up-Pb-I20 + + 2 p- (Sz-Ch354 - Sz-Ch3b4), (6)

where ChS35z and 4354 are the number of pulses generated by element 35 of the digital integrator 3 and 4, respectively;

ЧЗбз and 4364 the number of pulses generated by element 36 of the digital integrator 3 and 4, respectively.

Digital-to-analog converters 1 and 2, by codes (6), generate output voltages H1 and H2 of the generator in accordance with the expressions.

H1 Nm-F3 Nm-X;

| H2 Nm-F4 Nm-Y,

where Nm is the voltage amplitude determining the displacement of the indicator beam by the pth coordinate of X or Y by the radius of a unit length - see Fig. Z.

X and Y - modified (2-t-n) - bit additional codes of the rectangular coordinates X and Y of the indicator, which determine the possibility of moving the indicator beam by an amount greater than the radius of a unit length along each of the rectangular coordinates of the indicator.

The formation of voltages Н1 and Н2 in accordance with (7) makes it possible to display the SRL information in the visible part of the screen of the VOI indicator both in a circle with a unit radius and outside it, for example, when displaying service formulas of tori or formulas of coordinate points lying at the end of a distance circular scan - in Fig. 3 shows an eight-character formula p coordinate point lying at the end of the distance.

The voltage generator generally operates as follows.

Before the start of any of the modes, the generator contains information, -

qi, due to the history of its operation, and according to this information (the contents of counters 29 digital integrators 3 and 4), the generator

5 output voltages according to (7).

We will consider the operation of the generator in each of the modes using the time diagram of Fig. 4, and the operation of the device in the first, second, and third modes will be described in parallel.

In the first part of the first, second or third mode, the generator receives sequences of codes F16 and F17, accompanied by a sequence of pulses I18 of data recording, the number of pulses in which is seven in the first mode (a sequence of pulses I21. I22, I23, I24, I25, I26 ,

20 И27), it is equal to five in the second mode (a sequence of pulses И21, И22, И23, И24, И27 is formed) or equal to three in the third mode (a sequence of pulses И23, И24, И27 is formed) -cm.

25 Fig. 4 a, b, c, d, d. In this connection, after the end of the first part of these modes, the generator contains the codes ФЗ Хн, Ф4 YH, Ф5 Др-, Ф31з Ф314, П32Ф32з dКзК1.,. Кп, П32Ф324 СзС1 , .. Cn, F8 Xn +

30 + Xn, Ф9 YH + Yn, where the codes Ф8 and Ф9 are entered only in the first mode, and the values of the ФЗ and Ф4 codes are made only in the first and second modes, since in the third mode these codes are not

35 are changed, and are the result of the execution of the previous fourth mode. ..

40

45

fifty

55

In the second part of the first, second, or third mode, the digital-to-analog converters 1 and 2 generate the voltages N1 Nm-Khn and H2 Nm. The start of scanning, by which the indicator beam is set to the starting point in the first mode during the time of the Lodge, in the second mode during T2zh Ti, and in the third mode during the time TZz, “Ti, since in the third mode the rectangular coordinates Xn and YH are the coordinates of the end of the vector constructed in the previous fourth mode, where Ti is the time of the indicator beam transferring to the diameter accurate to the resolution element, is the waiting time in the i-th mode at j & {1, 2, 3}.

The fourth mode starts on I15 I19 V I20 and at the beginning of this mode (i.e. during I15), digital integrators 3 and 4 generate codes in accordance with the expressions

(ФЗ Хн + Хп-П6-И20,

Ф4 YH + Up-P6-I20,

(8)

those. at И15 И20, the ФЗ and Ф4 codes are changed from stepwise, respectively, to the codes Хп and Yn of the pedestals, which are proportional to the sweep speed (i.e., the pulse repetition rate И28), and, accordingly, the cosine and sine of the angle A.

During T4 (see Fig. 4 e, z, and, k), the NAND NOT 7 element generates a pulse train of range I7, the number of pulses in which is determined by formula (2). With the help of these pulses, the digital codes of integrators 3 and 4 generate the current codes of the rectangular scan coordinates according to expressions (6), and the digital-to-analog converters 1 and 2 of the scan voltage according to expressions (7). ...; ... -.:-.

In the process of performing the fifth mode, two parts of -1 cm can be distinguished. Fig. 4 a, b, c. In the first part of the fifth mode, two pulses I18 of data recording are received from the bus 16 at address F17 to the generator, by which pulses I21 and I22 are generated, and digital integrators 3 and A are written, respectively, the codes ФЗ Хн, Ф4 YH of the rectangular coordinates of the familiarity of the secondary information symbol. In the second part of the fifth mode (its duration is equal to the waiting time T Vozh), the digital-to-analog converters 1 and 2 generate the voltage (7) of the familiarity position of the secondary information symbol, into which the beam of the VOI indicator is set, and then the VOI displays the symbol of secondary information with using the sign generator. After the end of the fifth mode, any of the modes may begin except the fourth.

Thus, the five operating modes of the voltage generator considered allow the primary information and almost any secondary information, including the display of lines with arbitrary curvature, to be displayed in the VOI.

The claims

1. A voltage generator containing the first and second digital-to-analog converters, the outputs of which are connected respectively to the first and second output buses, the inputs - to the outputs of the first and second digital integrators, respectively, whose clock inputs are combined, the first trigger bus and the clock bus, characterized in . what. in order to expand the functionality by providing the possibility of generating the voltage of the sweep 5 with a displaced center and pedestals while simplifying, a pulse counter, an NAND element, first and second storage registers, a decoder, first, second, third, fourth and fifth

0 AND elements, data bus, address bus, data recording bus, second trigger bus, third output bus and trigger, the output of which is connected to the third output cable and to the first input of the AND-NOT element, second

5, the input of which is connected to the clock bus, the output to the clock inputs of digital integrators and the subtracting input of the pulse counter, the loan output of which is connected to the clock input of the trigger, the information input of which is connected to the common bus, the reset input is to the data bus and the synchronization input of the decoder, the information inputs of which are connected to the address bus,

5, the first output is connected to the first inputs of the first and second elements And, the outputs of which are connected respectively to the recording input of the first storage register and to the first input of the recording of the first digital integrator, the second decoder output is connected to the first inputs of the third and fourth elements And, the outputs of which are connected, respectively with the recording input of the second storage register and with the first input 5 of the recording of the second digital integrator, the data bus is connected to the information inputs of the pulse counter, through the first and second register s storage - with a first group of information inputs sootvot0. first and second digital integrators and directly with the second groups of information inputs of the first and second digital integrators, the second recording inputs of which are connected respectively with the third and fourth outputs of the decoder, the fifth, sixth and seventh outputs of which are connected respectively with the second input of the first AND element , with the second input of the third AND element and with the input

0 records of the pulse counter, while the trigger trigger input is connected to the output of the fifth AND element, the first input of which is connected to the first trigger bus, the second input to the second inputs of the second and fourth

5 elements And with the second launch bus.

2. The generator according to claim 1, with the exception that each of the digital integrators contains a reversible pulse counter, the outputs and information input of which are connected respectively to the outputs and

the first group of information inputs. a digital integrator, the first input of the recording of which is connected to the recording input of a reverse pulse counter, the summing and subtracting inputs of which are connected to the outputs of the first and second elements NAND, respectively, whose first inputs are connected to the transfer output of the adder, the information outputs of which are connected to the information inputs of the first storage register, the recording input of which is connected to the clock input of the digital integrator and through the first inverter with the second inputs of the first and second elements NAND, the third inputs are which, respectively, through the second inverter

and directly connected to the high-order output of the second storage register, the information inputs of which are connected to the second group of information

the inputs of the digital integrator, the second recording input of which is connected to the input of the unit to the single state of the senior bit and to the inputs of the installation to the zero state of the least significant bits of the first storage register and to the recording input of the second storage register, the information outputs of which are connected to the first group of information inputs adder, the second group of information inputs of which

connected to the outputs of the first storage register.

i-32-r

gSh

Fig g

V35

ёЗ

zo

7 s

/ Circumference

/ with single / soybean

fig.Z

VroBen Logistic m

CoorAnnatna Point Sforitzl Ron

Lines of circular sweep at - h AI35 ° and .HYCHN - D $

NroVen logical .. {G