RU1786480C - Trigonometric converter - Google Patents

Abstract

The invention relates to automation and computer engineering and can be used in devices for calculating trigonometric functions of arguments presented in analog form. The purpose of the invention - improving performance, expanding the scope and simplification - is achieved by combining in time the procedures of digitizing the argument presented in analog form and calculating the trigonometric functions of this argument. The trigonometric converter contains three adders, five registers, a counter, a ROM, a decoder, a DAC 12, a comparator, two matrix shifters, and a control unit. 2. ill.

Description

The invention relates to automation and computer technology and can be used to implement technical means in these areas.

Linear converters of an analog signal to a digital code are known, operating according to the bitwise algorithm used to obtain the linear conversion.

The disadvantage of this device is the inability to obtain a functional transformation.

A device for calculating trigonometric functions is known which converts digital codes represented in a fixed-point form using the Wolder bitwise algorithm.

By its technical nature and the achieved positive effect, this device is the closest to the proposed.

Its disadvantage is that it cannot perform trigonometric transformations on arguments presented in analog form.

The aim of the invention is to increase speed, expand the scope and simplification of the converter. . The goal is achieved in that a trigonometric converter containing the first and second accumulating adders-subtracters, the third accumulating adder, the first, second and third registers, counter, read-only memory, control unit, synchronization circuit, argument input, trigger input , the input of the initial installation, the first .and the second outputs of the device, the output of the device’s readiness, and the output of the first accumulating adder-subtractor is connected to the input of the first register, the output of the second accumulating sum Ator-subtractor connected to the input DC zaXI 00

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the memory device, the output of which is connected to the input of the third register, the output of which is connected to the information input of the third accumulating adder, the control inputs and outputs of all units are connected to the synchronization circuit, the above control inputs of the device are connected to the corresponding inputs of the control unit, the fourth and fifth registers are entered, a decoder, a digital-to-analog converter, a comparator, the first and second matrix shifters, the decoder output being connected to the device ready output and with the stop input of the control unit, and its input is connected to the output of the counter and the inputs of the number of shifts of the first and second matrix shifters. the information inputs of which are connected to the outputs of the first and second registers, respectively, and the outputs are connected to the inputs of the fourth and fifth registers, respectively, the output of the fourth register is connected to the information input of the second sum of the torus-subtracter, the output of the first register is connected to the information input. of the first adder-subtracter, the output of the third adder is connected to the input of the digital-analog converter, the output of which is connected to the first input of the comparator, in which the second input is connected to the input of the device argument -keeping, the output is connected to the mode setting inputs of the first and second adders-subtractors, whose outputs are connected to first and second output devices, respectively.

In FIG. T, a block diagram of a trigonometric transducer is shown; Fig. 2 is a flowchart of a non-linear transformation algorithm.

The device comprises: accumulating adders, subtractors 1 and 2, accumulating adders 3, registers 4-8, counter 9, read-only memory (ROM) 10, decoder 11, digital-analogue. converter (DAC) 12, comparator 13, matrix shifters 14 and 15, control unit 16,.

The output of the accumulating adder-reader 1 is connected to its first input and the input of the register 4, The output of the adder 2 is connected to its first input and the input of the register 5. The output of the accumulating adder 3 is connected to its main input and to the input of the digital-analog converter 12. The output of the register b connected to the second input of the adder 3, the output of the counter 9 is connected to the input 6m from the storage device 10, the input of the decoder 11 and the inputs of the number of shifts of the shifters 14 and 15

and

The output of the shifter 14 is connected to the input of the register 7, the output of the shifter 15 is connected with the input of the register 8, the output of the register 7 is with the second input of the adder 2, the output of the register 8 is with the second input of the adder 1, the output of the ROM 10 is with the input of the register 6 DAC output | 12

- with the first input of the comparator 13, the second input of which is connected to the input of the device argument, and the output to the mode inputs

10 adders 1 and 2. Decoder output: 11 is connected to the Stop input of the ynpjaelen block and the Ready device output. The first and second outputs of the device are connected to the outputs of the adder blocks 1 and 2.

15 The inputs of the Start and Initial Installation device are connected to the corresponding inputs of the control unit 16. The outputs of block 16 are connected via a synchronization circuit to the corresponding control inputs of units 20-9.

The trigonometric transducer operates as follows .;

. The initial setting signal is reset to control unit 16, and the specified 25 signal is generated only when the device is powered on. On start signal. . block 16 is set up, after: after which it starts to generate signals: controls that provide processing 30 of the argument p, which is input to the input of the device argument, and calculates the values of the functions sin (p and cos (p, which are supplied to the corresponding outputs of the device;).

The operation of 35 trigonometric transducers is described in more detail using the block diagram of the algorithm on

Figure 2,.-..-. .; .-.

The control signals A1-A4, causing the units of the device to perform the required procedures, are generated. block 16 sequentially: the first Btipa- is A1, the last is A4. hc The appearance of a signal at the TCJTOB output of the device indicates | 45 that the results at the first and second outputs are reliable. | .Formula and shade j Trigonometric transducer containing the first and second accumulating subtracting adders, the third ngkaplyayuschaya adder, the first and second and third registers, the counter, the constant firing device , a control unit, a synchronization circuit, an argument input, a start input 55, an initial setup input, a first and second device output, a device ready output, the output of the first accumulating adder-subtractor being connected to the input of the first register,

the second accumulating adder-subtractor is connected to the input of the second register, the output of the counter is connected to the input of the second register, the output of the counter is connected to the input of the permanent storage device, the output of which is connected to the input of the third register, the output of which is connected to the information input of the third accumulating adder , the control inputs and outputs of all blocks are connected to the synchronization circuit, the above control inputs of the device are connected to the corresponding inputs of the control unit, characterized in that oh, in order to improve performance, expand the scope and simplify by calculating trigonometric functions simultaneously with analog-to-digital conversion of the argument, the fourth and fifth registers, a decoder, a digital-to-analog converter, a comparator, the first and second matrix shifters are introduced, and the decoder output connected to the readiness output of the device and to the stop input of the control unit, and its input is connected to the counter output and the inputs of the number of shifts of the first and second matrix shifters, information whose inputs are connected to the outputs of the first and second registers, respectively, and the outputs are connected to the inputs of the fourth and fifth registers, respectively, the output of the fourth register is connected to the information input of the second adder-subtracter, the output of the fifth register is connected to the information input of the first adder subtractor, the output of the third adder is connected to the input of the digital-to-analog converter, the output of which is connected to the first input of the comparator, in which the second input is connected to the input of the device argument, the output One is connected to the installation inputs of the mode of the first and second adders-subtracters, the outputs of which are connected to the first and second outputs of the device, respectively.

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