RU1785043C - Method and device for nuclear fission reactor driving operating control member - Google Patents

Abstract

Usage: drives of regulatory bodies of nuclear reactors with three-phase AC motors and thyristor switches, as well as drives of machines, robots, reloaders, etc. with three-phase AC motors and thyristor switches. SUMMARY OF THE INVENTION: to increase the accuracy of regulation and reduce power consumption at the moment the line voltage of the network passes through zero from the negative and positive regions between the first and second phases, control voltages are applied to a pair of switch thyristors, one of which is in the first phase and the other in second, then repeat these operations with voltages in series between the first and third, second and first, third and first, as well as the third and second phases. A single vibrator, two conversion units, two decoders and logic elements are introduced into the proposed control device, with one conversion unit operating with a variable counting coefficient and the other with a counting coefficient of 6. 6 il. SL C

Description

The invention relates to a drive control system for regulating bodies (RO) of nuclear reactors, it can also be used in three-phase thyristor drives of other mechanisms (machines, robots, manipulators, reloaders, etc.).

It is known to use alternating current motors, in particular asynchronous motors (AM), to drive a nuclear power reactor.

PO drive control systems must ensure the fast introduction of the PO into the reactor core with emergency protection signals, which is most easily and reliably provided by the drive and motor control systems by directly connecting the AD to the network using keys that thyristor switches can perform.

At the same time, in the automatic control (AR) mode of the reactor power, it is necessary to ensure the operation of the PO drive with a sufficiently small displacement, which would not lead to an oscillatory process when working with the reactor power regulator.

Known methods for producing small displacements for drives with AC motors and devices for their implementation. Closest to the proposed method and device is a power circuit and a method of controlling the drive in

00 SL

g

W

step mode, which are selected as a prototype.

With this control method, the stepwise movement of the motor rotor is carried out clockwise due to the abrupt rotation of the stator magnetizing force (NS) vector by 120 el. hourly hand when performing each of the operations.

This control method has the following disadvantages: the minimum amount of movement of the RO in the AP mode is limited by the indicated rotation angle n.s. stator 120 el. degrees (the amount of PO displacements in the AR mode is determined by the angle of rotation of the HELL rotor for one thyristor switching. The smaller the angle, the smaller the amount of PO displacement in the AR mode. This angle is proportional to the angle of rotation of the NS stator corresponding to one switching thyristors): due to the characteristic two-phase switching of the AP by the one-half-wave rectified linear voltage of the network, elevated values of the AM currents, switch thyristors and the current consumed from the network are formed over time t; constant voltage and subharmonics appear in the output voltage of the switch.

The purpose of the invention is to remedy these drawbacks as a result of which the basic characteristics of the electric drive are improved; the magnitude of the displacement of the rotor of the motor per switching thyristors, i.e. the accuracy of regulation is increased, the motor current, the current of the thyristors of the switch and the current consumed by the drive from the network are reduced; there are no constant components or subharmonics in the output voltage of the switch, i.e. reduced power consumption.

The specified goal in the proposed method is achieved by the fact that at the moment of the linear voltage of the network passing through zero from the negative region to the positive region between the first and second phases, a control voltage is applied to a pair of thyristors, one of which is in the first and the other in the second phase. moreover, fixing the moment of the indicated transition through zero

produced K times, where K. somax

maximum drive speed; (o-required drive speed, at the Kth fixation of the zero crossing, control voltages are supplied to a pair of thyristors, one of which is in the first phase and the other in the second, then these operations are repeated with voltages in series between the first and third, second and third,

second and first, third and first, as well as third and second phases.

The goal in the proposed device is achieved by the fact that the device

controlling the drive of the regulatory body of the nuclear reactor, containing an ac motor with phases connected to the star with the beginnings a, b, c of the stator and a switch of six thyristors connected to a three-phase network with phases A, B, C, the cathode of the first thyristor connected to the anode the second and phase a of the motor, the anode of the first thyristor is connected to the cathode of the second and phase A of the network, the cathode of the third thyristor is connected to the anode of the fourth and phase to the motor, the anode of the third thyristor is connected to the cathode of the fourth and phase B of the branch, the cathode is of the thyristor is connected to the anode of the sixth and to the phase from the motor, the anode of the first

0 thyristor is connected to the cathode of the sixth and phase C of the network, a synchronizing transformer, the first to third zero-organs, the first to ninth inverters, the first to twelfth two-input elements And, are introduced

5 a six-input OR element, a single vibrator, the first and second conversion units, the first and second decoders, a switch consisting of fourteen keys and a resistor, the first to sixth two-input OR elements, the first to sixth thyristor triggering device, and the synchronizing transformer is made with one primary and one secondary three-phase windings, the primary winding with the beginnings

5 A, B, C and the ends X, Y, Z are connected in a triangle so that X is connected to B, Y - to C. Z - to A, the phases of the supply network A, B, C and the beginning A, B, C of the primary windings are connected respectively, the ends of the secondary winding X, Y. Z

0 are connected to the common bus, the beginnings of the secondary winding a, b, c are connected respectively through the first, second and third zero-organs with the inputs of the first, second and third inverters and the first inputs

5 of the first, second and third two-input elements AND, the outputs of the first-third inverters are connected respectively to the first inputs of the fourth to sixth two-input elements And, the outputs of the first 0 to sixth two-input elements AND are connected respectively to the first to sixth inputs of the six-input element OR and the first inputs of the seventh of the twelfth two-input element AND, the output of six5 input element OR is connected through a single vibrator to the counting input of the first conversion unit, the first and fourth outputs of which are connected respectively enno bitwise with the first to fourth address input of the first decoder, the first

the output of which is connected to the counting input of the second conversion unit, the first and fourth outputs of which are respectively bit with the first and fourth address inputs of the second decoder, the first and sixth outputs of which are connected respectively through the fourth to ninth inverters with the second inputs of the first, sixth, second, fourth , the third and fifth of the two-input elements AND, the second - the Kth outputs of the first decoder are connected respectively to the first - (K-1) inputs of the switch, the Kth input of which is connected to the fifth output of the first cross block, and the output is to the second inputs of the seventh-eleventh two-input elements AND, the output of the seventh two-input element AND is connected to the first inputs of the first and sixth two-input elements OR, the output of the eighth two-input element AND is connected to the first inputs of the second and third two-input elements OR, the output of the ninth AND element is connected to the first inputs of the fourth and fifth OR elements, the output of the tenth AND element is connected to the second inputs of the third and fourth OR elements, the output of the eleventh AND element is connected to the first inputs of the fifth and sixth OR elements, the output of the twelfth AND element is connected to the second inputs of the first and second OR elements, the outputs of the first to sixth OR elements are connected respectively to the first to sixth thyristor triggering devices, the positive poles of the output voltages of which are connected respectively to the control electrodes of the first, sixth, third, second, fifth and fourth thyristors, and the negative poles of the output voltages - respectively, with the cathodes of the first, sixth, third, second, fifth and even thyristors.

In FIG. 1 shows a power circuit of an electric drive, where 1-6 are thyristors; 7 - AC motor; A, B, C - lines of a three-phase network; a, b, c - the beginning of the motor windings 7 connected to the star.

In FIG. Figure 2 shows the output voltage of the switch for its minimum TW period. 2 (), bold line; in FIG. 3 - output voltage of the switch for its arbitrary period Tsykh.k. (arbitrary K), the bold line, where UAB, UBC, UCA are the line voltages of the network of phases AB, BC, CA, respectively, the bold line indicates the line voltages of the network connected to the phases of the motor 7 (output voltage of the switch); inside the half-waves of the indicated voltages, the open thyristors of the switch are indicated; switch load is accepted active; the origin is the time of zero crossing from the negative region to the positive line voltage UAB. and the time is counted in the angular measure of the network frequency uJc t ((We is the angular frequency of the network, t is time).

The operation of the device is illustrated in FIG. 4-6.

In FIG. 4 shows a block diagram of a device where: 1 - 6-thyristors; 7 - AC motor; 8 - synchronizing transformer; 9.1-9.3 - null organs; 10.1-10.9 - inverters; 11.1-11.12 - two-input elements And; 12 - six-input element OR; 13 - the first conversion unit; 14 - counting input of block 13; 15.1-15.5

- outputs of block 13 (15.1 - low-order output; 15.2,15.3,15.4 - higher-level output, respectively; 15. DC power supply 34 (see Fig. 5); 16, 25 - decoders; 17.1-17.4 ; 26.1-26.4 - address inputs of decoders 16 and 25; 18.0-18.5; 27.0-27.5 - outputs of decoders 16 and 25; 19-switch: 20.1-20.15 - inputs of switch 19; 21 - output of switch 19; 22 - second conversion block; 23 - counting input of block 22; 24.1-24.4

- outputs of block 22 (24.1 - low-order output, 24.4 - high-order output);

28.1-28.6 - two-input elements OR; 29.1-29.6 - thyristor triggering devices; 38 - one-shot.

In FIG. 5 shows a diagram of the first

a conversion block, where: 30 is a four-digit binary counter; 31.1 - counting input of the counter 30; 31.2 - input setting zero counter 30; 32.1-32.4 - outputs of the counter 30 (32.1 - low-order output, 32.4 - high-order output); 33.1-33.4-switches; 34 is a direct current power supply; 35 - four-input element AND NOT. In FIG. 6, representing the circuit of the switch 19, shows: 36.1-36.14 - keys, 37 - resistor.

To describe the proposed control method, we introduce the following conventions: the time passing through zero from the negative region to the positive line voltage of the UAB network is tt-dv, the time passing through zero from the negative region to the positive line voltage of the UBC network is t + bc, the time passing through zero from the negative region to the positive line voltage of the UCA network is t + cA. the travel time through zero from the positive region to the negative line voltage of the UAB network is t-dv. the travel time through zero from the positive region to the negative line voltage of the UBC network is t-bc. the travel time through zero from the positive region to the negative line voltage of the UCA network is t-cA. control voltage of thyristor 1 Ui, control voltage of thyristor 2 U2, control voltage of thyristor 3 Oz. thyristor control voltage 4 1M, thyristor control voltage 5 Us, thyristor control voltage b Ue, the number of half-periods of the line voltage of the network of one polarity from the start of turning on any pair of thyristors to the beginning of turning on the next pair of thyristors - K.

The sequence of cyclag operations defining the proposed control method is described below: fixing t-t-dv, forming U1 and Lto at time t + dv. fixation t + dv (k-1) times, formation of Ui and U at the moment of the last fixation t + dv, fixation of t-cA, formation of Ui and Ue at the moment of t-sd, fixation of t-cA (k-1) times, formation of Ui and Ue at the moment of the last fixation of t-cA, fixation of t + sun, formation of Uz and Ue at the moment of t + BC, fixation of t + Bc (k-1) times, formation of Us and Ob at the moment of the last fixation of t. + sun fixing t-AB. formation of U2 and out at time t-AB. fixation T-AB (k-1) times, formation of U2 and Us at the time of the last fixation t-AB. fixation t + cA, formation of Uz and Us 1 at the moment t + cA, fixation T + CA (k-1) times, formation of Ua and Us at the moment of the last fixation t + CA. fixation t-sun, formation of UA and Us at the time t-sun, fixation t-sun (k-1) times, formation of HA and Us at the time of the last fixation t-sun.

Then the cycle repeats.

The proposed control method is implemented with K S 2 values.

The period of the output voltage of the switch with this drive control method for an arbitrary K is:

Thy (6k-5) -Tc, where Tc is the voltage period of the network.

Let thyristors 1 and 4 be turned on, and two phases of the motor 7 - a and b - connected to the network. Then, when switching the next pair of thyristors 1-6, first all three phases of the network are connected to the motor (thyristors 1, 4, 6 are turned on), while the stator field rotates with the mains frequency, then one thyristor connected to the motor as a result of the previous switching is extinguished ( thyristor 4), and the motor is connected to the network of two phases of the motor (a and c), which ultimately leads to the rotation of the vector N.C. stator at 60 degrees, clockwise with respect to the previous position of the vector N.S. stator. Similarly, processes occur in the drive during switching of the following pairs of thyristors.

With the proposed control method

the rotor of the engine is rotated clockwise due to clockwise rotation of the vector n.s. stator at 60 el. for each switching of the next pair of thyristors (during operation b, 10,14,18,22,2), which is half as much compared to the prototype, where the specified angle is 120 PLN. The angle of rotation of the rotor is-d- for a synchronous motor

Ooh

or will be less than, for an induction motor, where P is the number of pole pairs of the motor.

From FIG. 2 and 3 it is seen that, compared with the prototype, when implementing the proposed method for controlling the drive, the currents of the motor and thyristors decrease, the current consumed by the drive from the network, and in the output

There are no constant components or subharmonics at the switch voltage.

Below is a description of the individual elements of the proposed device.

Timing Transformer 8

converts the three-phase voltage of the network into three single-phase, coordinated in level with the inputs of the zero-organs 9.1-9.3. The connection diagram of the transformer windings is designed so that the voltage at the input 9.1 in phase

coincides with the line voltage of the UAB network, at input 9.2 - with the voltage Use, at input 9.3 - with the voltage UCA.

Zero-organs 9.1-9.3 transform the sinusoidal voltage of the network into a rectangular, in-phase with a sinusoidal. The performance of the null organs is standard.

Setting the required coefficient K of the account of the first conversion unit 13 (Fig. 5) is carried out by connecting using

switches 33.1-33.4 of the inputs of element 35 to those outputs of the counter 32.1-32.4, on which, with a code combination equal to K in the binary code, the signal values will be equal to Log. 1, and the rest of the switches

from 33.1-33.4 connect the inputs of the element 35 to the plus of the source 34.

The position of the switches 33.1-33.4 in FIG. 5 corresponds to either in binary code, i.e. outputs 32.1 and 32.3 are connected by switches 33.1 and 33.3 to the two inputs of element 35, and the other two inputs of element 35 by switches 33.2 and 33.4 are connected to the plus of source 34.

The required K value of 2 to 1 b is pre-set manually. If the initial value of counter 30 corresponds to the code combination 0000 at outputs 32.1- 32.4, then after a K-ro pulse at input 33.1, the code at outputs 32.1-32.4 will become equal to K, and the Log.O signal from output 35 will go to input 35.2 , which will cause counter 30 to be set to code 0000.

By analogy with the scheme of the first conversion unit 13, the second conversion unit 22 is implemented with a counting factor of 6, consisting of a four-bit binary counter and a two-input I-NB element. The outputs of the second and third bits of the four-bit binary counter are connected respectively to the first and second inputs of the two-input AND-NOT element, and the output of this element is connected to the counter zero input. Then, after the sixth pulse at the input 23 of block 22, the code at the outputs 24.1-24.4 will become 0110, which will lead to the appearance of a Log.O signal at the output of the two-input AND element and setting the counter 22 to 0000.

As four-bit binary counters for 13 and 22, K155IE2 chips can be used; the change in the output code of the counters occurs according to negative differences (from Log. 1 to Log. O) of the input signals.

Decoders 16 and 25 are implemented on standard microchips, for example K155IDZ. Upon receipt of any code combination at the address inputs, the decoder transfers one of its outputs corresponding to this combination in the decimal number system to the Log state. at the other outputs, the Log.1 level is preserved. A single-shot 38 is also performed on standard microcircuits. It is designed to generate, under the influence of the input signals, single pulses of Log.1 with a duration of 5-10 el. network frequencies.

The keys 36.1-36.14 of switch 19 (Fig. 6) are open when 3 K 16 connects inputs 20.1 to 20 (K-2) with output 21 as follows: when closed 36.1, when closed 36.1 and 36.2, etc. ., and when keys are closed from 36.1 to 36.14. As with FIG. 5, in FIG. 6, the position of the keys corresponds to the keys 36.1 to 36.3 connect the inputs 20.1 to 20.3 with the output 21.

Thyristor triggering devices 29.1-29.6 generate thyristor control voltages 1-6 of the required duration and amplitude. The outputs of devices 29.1-29.6 are connected to the control electrode-cathode circuits of thyristors 1-6, while the positive poles of the output voltages 29.1-29.6, marked in Fig. 4 by + signs, are connected to the control electrodes of thyristors 1-6, and negative poles - with cathodes of thyristors. The proposed device operates as follows. The three-phase voltage of the network with the help of a synchronizing transformer 8, zero-elements 9.1-9.3 and inverters 1U.1-10.3 is converted so that 0 positive half-wave voltage UAB. UAC, UBC, DBA, UCA, UCB correspond to the positive values of the output voltages of elements 9.1, 10.3, 9.2, 10.1, 9.3 and 10.2, respectively. If the positive 5 values of the output voltages 9.1-9.3, 10.1-10.3 coincide with the corresponding code combinations at the outputs of the second counting unit 22 and there is no prohibition (Log.O), the signals from output 21 of the switch 19 are turned on Log, 1 at the outputs of elements 11.7-11.12 and 28.1-28.6, and triggering circuits 29.1-29.6 form control pulses of thyristors 1-6.

The device diagram (Fig. 4) implements the following 5 algorithms:

Ui Uzi x (0000 x UAB + 0001 x UAC)

Ua U21 x (0100 x UCA + 0011 x UBA)

Us U2ix (0011 x UBA + 001 Ox Use)

U4 U21 x (0000 x UAB + 0101 x UCB) 0 Us U2i x (0101 x UCB + 0100 x UCA)

Ue + U2i x (0010 x UBC + 0001 x UAC) where Ui ... U6 are control pulses respectively on thyristors 1-6;

0000.,. 0101 - code combinations on 5 outputs of the second conversion unit 22;

UAB, UCB, UCA, UBA, UBC, UAC - line voltage of the mains;

U21 signal at the output 21 of the switch 19.

0 Suppose that the initial states of the recalculation blocks 13 and 22 correspond to codes 0000 both at outputs 15.1-15.4 and at outputs 24.1-24.4. Then the state of the device is characterized by Log.O at the outputs 18.0 5 and 27.0 of decoders 16 and 25, inverters 10.5-10.9, two-input elements And 11.2-11.6 and Log.1 at the output of the inverter 10.4.

The signal at the output of element 11.1 is pulse 0 and is equal to Log. 1 during a positive half-wave of voltage UAB and Log.O at a negative half-wave. This signal, coming through element 12 to the input of the single-vibrator 38, is the last to be converted into 5 pulses of Log.1 with a duration of 5-10 electric gr. network frequencies, which, entering the counting input 14 of the first counting block 13, cause a change in the code at the outputs 15.1-15.4. At the same time, the first and kth pulses of Log.1 at output 11.1 will cause

Log At the outputs of elements 11.7, 28.1, 28.6, respectively, the formation of pulses by devices 29.1 and 29.6 and the inclusion of thyristors 1 and 4. Pulses Log.1 from 2 to (k-1) at K 2 at the output 11.1 will not cause the inclusion of thyristors 1 and 4, because a signal Log.O will be sent to the input of element 11.7. From the output 21 of the switch 19. The decline of the k-ro pulse at the output 11.1, coinciding in time with the transition from positive to negative values, will cause the first recalculation block 13 to be reset, the state will go from Log . 1 in Log.O at the output 18.0 of the decoder 16, as a result, the appearance of the code combination 0001 at the outputs 24.1-24.4, the signal Log.O at the output 27.1 of the decoder 25 and the inverter 10.4 and Lor.G at the output of the inverter 10.5. Now, by a known 1st step, the signal at the output of element 11.6 becomes pulsed, during 1 and k-ro pulses of Log.1, thyristors b and 1 turn on at output 11.6, and after the k-ro pulse there will be another zeroing of the first conversion block 13 and change state of the decoder 25.

As described below, the inclusion of the following thyristor thyristors is carried out: 3-6. 2-3, 5-2, 4-5. Then, the cycle starting with turning on the thyristors 1-4 is repeated.

The sequence of alternating half-wave voltages on the motor is rigidly set by the block diagram of the device: UAB, UCA, UBC, UBA, UCA. Uce, and the form of the output voltage of the switch for and is shown in FIG. 2 IZ,

Claims (2)

SUMMARY OF THE INVENTION -1. A method for controlling the drive of a regulatory body of a nuclear reactor, which consists in supplying control voltages in series to the thyristors of the first and second, then second, third, third and first phases of the network, distinguishing also by the fact that in order to increase the accuracy of regulation when the linear voltage of the network through O passes from the negative to the positive region between the first and second phases, a control voltage is applied to a pair of thyristors, one of which is in the first and the other in the second phase , then repeat this operation with voltages in series between the first and third, second and third, second and first, third and first, as well as the third and second phases, and the moment of the above transition through O is fixed k times, where TO O) max O) (Oman - maximum drive speed,  the required drive speed, at the Kth fixation of the transition through O, control voltages are applied to a pair of thyristors, one of which is in the first phase and the other in the second. 2. The drive control device of the regulatory body of the nuclear reactor, comprising an asynchronous squirrel-cage motor with stator phases A, B, C connected to the star and a switch of six thyristors connected to a three-phase network with phases A, B, C, the cathode of the first thyristor connected to the anode of the second and motor phase a, the anode of the first thyristor is connected to the cathode of the second and phase A of the network, the cathode of the third thyristor is connected to the anode of the fourth and phase b of the motor, the anode of the third thyristor is connected to the cathode of the fourth and phase B c In this case, the cathode of the fifth thyristor is connected to the anode of the sixth, with the motor phase C, the anode of the fifth thyristor is connected to the cathode of the sixth and with the network phase C, characterized in that, in order to increase the accuracy by decreasing the step of the regulator, the currents of the motor, thyristors and consumed from the network, and elimination of the constant component and subharmonics in the output voltage of the commutator, a synchronizing transformer, first-third zero-organs, first-ninth inverters, first-twelfth AND elements, six-input OR element, are introduced into it again a brother, first and second conversion blocks, first and second decoders, a switch consisting of fourteen keys and a resistor, the first is the sixth two-input OR element, the first to sixth thyristor triggering devices, and the synchronizing transformer is made with one primary and one secondary three-phase windings, the primary winding with beginnings A1, B, C and ends X, Y, Z is connected to a triangle1 so that X is connected to B, Y is connected to C, Z is connected to A, phases of the supply network A, B, C and start A, B , With the primary windings connected respectively, the ends of the secondary oh the windings Xi, Yi, Zi are connected to a common bus, the beginning of the secondary winding Ai, 81. Ci are connected respectively through the first, second and third zero-elements with the inputs of the first, second and third inverters and the first inputs of the first third two-input elements And, the outputs of the first the third inverters are connected respectively to the first inputs of the fourth to sixth two-input elements AND, the outputs of the first to sixth two-input elements I / I are connected respectively to the first to sixth inputs of the six-input element OR and the first inputs of the seventh, tenth of the eleventh, eighth, ninth and twelfth two-input elements AND, the output of the six-input element OR is connected through a single vibrator to the counting input of the first conversion unit, the first and fourth outputs of which are connected respectively to the first and fourth address inputs of the first decoder, the first output of which connected to the counting input of the second conversion unit, the first to fourth outputs of which are connected respectively bitwise to the first to fourth address inputs of the second decoder, the first to sixth the odes of which are connected respectively through the fourth-ninth inverters with the second inputs of the first, third, second, fourth, sixth and fifth of the two-input elements And, the second n-th outputs of the first decoder are connected respectively to the first (p-1) inputs of the switch, the nth input of which is connected to the fifth output of the first conversion block, and the output to the second inputs of the seventh to twelfth two-input elements AND, the output of the seventh two-input element AND is connected to the first inputs AND % the first and second two-input elements OR, the output of the eighth two-input element AND is connected to the second input and the first input of the third two-input OR element, the output of the ninth AND element is connected to the second input of the third and the first input of the fourth OR element, the output of the tenth element AND is connected to the second input of the fourth and first input of the fifth element OR. the output of the eleventh AND element is connected to the second input of the fifth and first input of the sixth OR element, the output of the twelfth element And is connected to the second inputs of the sixth and second OR elements, the outputs of the first to sixth two-input OR elements are connected respectively to the first to sixth thyristor triggering devices, positive poles the output voltages of which are connected respectively to the control electrodes of the first, sixth, third, second, fifth and fourth thyristors, and the negative poles of the output voltages are first go, second, third, fourth, the fifth and sixth triggering devices are connected respectively to the cathodes of the first, sixth, third, second, fifth and fourth thyristors. at 0 e 0 f and I / Shchig. 1 n u) and AND u    1 MP W h „ md . P l LvJ 1 MP % tfU 8 l "C / Yes 1 in vyql CtOGSIl Figure 5