RU1783610C - Device for analog-to-digital conversion with automatic selection of measurement limit - Google Patents

Abstract

The invention relates to a digital information measuring technique and can be used to convert rapidly changing signals into a digital code, as well as to interface digital computers with analog channels / 7 having a large dynamic range. The purpose of the invention is to increase the conversion speed while expanding the dynamic range. The device comprises a scale unit 1, an analog storage device 2, an analog-to-digital converter 3, an arithmetic logic unit 4, a scale selection unit 5, a synchronization unit 16. The introduction of speed analysis into the device 12 and establishing new connections in the scale selection unit 5 allows, by analyzing the instantaneous values and the rate of change of the signal voltage, the transmission coefficient of the scale unit 1 to be controlled in order to ensure the minimum reduced error and eliminate the ADC overload at a given speed input signal changes. 2 s.p. f-ly, 2 ill. (L C

Description

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The invention relates to a digital information and measurement technique and can be used to convert rapidly changing signals to a digital code, as well as to interface digital computers with analog channels having a large dynamic range of the signal.

A device for analog-to-digital conversion is known, based on the automatic control of the bias voltage supplied to the input of the analog-to-digital converter together with the input signal, which allows to expand the dynamic range of the input signals and increase the accuracy of the conversion. This device comprises a position coordinate changing unit executed on a summing amplifier and keys, an analog-to-digital converter, a read-only memory, a control unit made on two read-only memory devices and a memory register.

This device provides a high conversion speed, however, it does not provide high accuracy at low signal voltages and thereby significantly expand the dynamic range, since the expansion of the operating range occurs only in the region of high voltages exceeding the upper limit work of the analog-to-digital converter.

The closest in technical essence to the invention is a device for analog-to-digital conversion with automatic selection of the measurement limit, the principle of operation of which is based on automatic control of the transmission coefficient of the scale unit by a preliminary assessment of the input signal level and calculation, based on this , such a value of the transfer coefficient of the scale block, which will provide the smallest value of the reduced error. The device comprises an analog storage unit, a scale unit, an analog-to-digital converter, a scale selection unit including a read-only memory device, a digital divider, as well as a register, a synchronization unit, an arithmetic logic unit, a scale register, an OR element, and a timer.

This device is characterized by high conversion accuracy, however, it has low speed and does not significantly expand the dynamic range of the device. These disadvantages are due to the fact that each conversion is performed in two cycles; in the first cycle, preliminary conversion and calculation of the transfer coefficient of the scale block, and in the second, the exact conversion itself, which increases the total conversion time by a factor of 2, respectively. The inclusion of an analog storage device at the input of the device does not allow linearity of the conversion characteristics at low signal levels and thereby limits the dynamic range of the input signals.

The aim of the invention is to increase the conversion speed while expanding the dynamic range.

This goal is achieved by the fact that in the device of analog-to-digital conversion with automatic selection of the measuring range, containing a scale unit, an analog storage device, an analog-to-digital converter, an arithmetic-logic unit, a scaler and a synchronization unit, while the first output is analog- the digital converter is connected to the first input of the arithmetic-logical unit and to the first input of the scale selection unit, the second input of the analog storage device and the second input of the analog-to-digital converter the developer is connected to the Start bus, and the output of the arithmetic-logical unit is the output bus of the device, a speed analysis block is introduced, while the first input of the speed analysis block is connected to the first output of the synchronization block, the second output of which is connected to the third input of the scale selection block, the input of the block synchronization is connected to the second output of the analog-to-digital converter, the second input of the speed analysis unit is connected to the second output of the scale selection unit, the output of the speed analysis unit is connected to the second input of the unit select the scale, the third input of the forming unit, the first input of the scale unit and the second input of the arithmetic-logical unit are connected to the first output of the scale selection unit, the first input of the analog-to-digital converter is connected to the output of the analog storage device, the first input of which is connected to the output of the scale unit, the second the input of the scale unit is the input bus of the device, while the scale selection unit is made on a code converter, a first ROM, a register, an adder, a second ROM and an NAND element, the first adder input n is connected to the output of the first ROM, and the second input of the adder and the first input of the second ROM are connected to the output of the register, the output of the adder is connected to the first input of the register, the second input of the register is connected to the output of the AND-NOT element, the output of the register is the first output of the block, the first input of the first The ROM is connected to the output of the code converter, the second input of the first ROM is the second input of the block, the input of the code converter is the first input of the block, the output of the first ROM is connected to the second input of the second ROM and is the second output of the block, the first input The AND-NOT element is connected to the output of the second ROM, the second input of the AND-NOT element is the third input of the block, the speed analysis unit is made on the ROM, with a mat and register, and the first input of the register is connected to the output of the sum, mat and the register output is connected to the second input of the adder, the second input of the ROM and is the output of the block, the first input of the adder is connected to the output of the ROM, the first input of which is the second input of the block, the second input of the register is the first input of the block.

The proposed device, in comparison with the prototype, provides the possibility of increasing the conversion speed and expanding the dynamic range of the measured signals by introducing a speed analysis unit, a new scale block control algorithm based on the analysis of the instantaneous values of the input signal and the rate of change of the input signal, which allows It is possible to organize adaptive control of the scale unit, at which the magnitude of the reduced error depends on the rate of change of the input voltage.

Figure 1 presents a structural diagram of the proposed device; figure 2 is a timing diagram of its operation.

An analog-to-digital conversion device with automatic selection of the measurement limit (FIG. 1) includes a scale unit 1, an analog storage device 2, an analog-to-digital converter 3, an arithmetic logic unit to 4, a scale selection unit 5, including a code converter 6, first ROM 7, adder 8, register 9, second ROM 10, AND-NOT element 11, and a speed analysis unit 12 including ROM 13, adder 14, register 15, as well as synchronization unit 16, trigger input terminal 17, output terminal 18 and input terminal 19. First analog-to-digital output reobrazovatel 3 is connected to the first input of the arithmetic logic unit 4 and the first input of ratio selection unit 5 and the second input of the analog storage device 2 and a second input of analog-to-digital converter 3

connected to the start bus 17. The output of the arithmetic logic unit 4 is the input bus 19 of the device. The first output of the speed analysis unit 12 is connected to the first output of the synchronization unit 16, the second output of which is connected to the third input of the scale selection unit 5, and the input of the synchronization unit 16 is connected to the second output of the analog-to-digital converter 3. The second input of the speed analysis unit 12 is connected to the second the output of block 5 select the scale.

The output of the speed analysis block 12 is connected to the second input of the scale head unit 5, and the first input of the scale block 1 and the second input of the arithmetic logic block 4 are connected to the first output of the scale block 5. The first input of the analog-to-digital converter 3 is connected to the output of the analog storage device 2, the first input of which is connected to the output of the scale unit 1, and the second input of the scale unit 1 is the input terminal 19 of the device.

The first input of the adder 8 and the first input

the second ROM 10 is connected to the output of the register 9. The second input of the register 9 is connected to the output of the NAND element 11, the output of the register 9 is the first output of the scale selection unit 5, The first input of the first ROM 7 is the second input of the scale selection unit 5, the input of the converter codes 6 is the first input of the scale select unit 5. The output of the first ROM 7 is connected to the second input of the second ROM 10 and is the second outputs of the scale select unit 5. The first input of the AND-NOT 11 element is connected to the output of the second ROM 10, and the second input of the AND-NOT 11 element is the third input of the scale selection unit 5.

The input of the register 15 is connected to the output of the adder 14. and the output of the register 15 is connected to the second input of the adder 14, the second input of the ROM 13 and is the output of the speed analysis unit 12. The first input of the adder 14 is connected to the output of the ROM 13, the first input of which is the second input of the speed analysis unit 12, the second input of the register 15 is the first input of the speed analysis unit 12.

The practical implementation of all the described functional blocks of the analog-to-digital conversion device with automatic selection of the measurement limit at a lower structural level than that shown in Fig. 1 and set forth above is known.

The scale unit 1 is a programmable amplifier; the analog storage unit 2 can

be implemented on the integrated circuit K1100SC2. Block 16 synchronization can be implemented on a standby multivibrator K155AGZ. ROMs 7, 10, and 13 can be performed on any integrated ROM with an organization of 256 x 4 (for example, K556RT4), code converter 6 can be executed on an integrated ROM with an organization of at least 4096 x 4 or implemented on a combination decryption scheme. As adders 8, 14, the arithmetic 4-bit adder K155IM1 can be used, as registers 9 and 15 - registers K155IR15.

The invention is as follows. From the point of view of ensuring the smallest reduced error of the analog-to-digital conversion, the gain of the scale block must be controlled so that for any value of the input signal at the input of the device, the voltage at the input of the analog-to-digital converter (ADC) 3 is as close as possible to the upper limit of the operating range of the ADC. The entire range of ADC input voltages is divided into n intervals, where n is the number of ADC bits, and it is believed that some 1-sample with the highest order weight k is in the kth quantization interval. The higher the sample quantization interval, the smaller the reduced error is, and from the point of view of the sequence number of the quantization interval, the reduced quantization error can be estimated.

The transmission coefficient of the scale block is controlled so that each current sample is in the uppermost interval. To this end, after each clock cycle of the analog-to-digital converter, the value of the obtained sample is analyzed and the corresponding quantization interval is determined. A new value of the gain of the scale unit 1 is then calculated so that the next sample, taken through a constant value of the sampling time, is in the nth quantization interval. Obviously, at a fast voltage at the input of the device during the time between two adjacent samples, it can go beyond the upper limit of the nth quantization interval and, accordingly, beyond the working range of the ADC, in which case the value of such a sample will be distorted. In order to prevent overload of the ADC unit, an analysis of the rate of change of the input voltage is carried out. The higher the rate of change of voltage;

the lower the working quantization interval, i.e. the interval in which all current signal samples should be. As the rate of change of the signal changes, the corresponding quantization interval also changes. Thus, adaptive control of the transmission coefficient of the scale block is carried out in order to ensure the minimum reduced conversion error and eliminate the ADC overload at a given rate of change of the input signal.

Turning on the scale unit 1 directly to the input of the device allows increasing the dynamic range, since in this case the dynamic range is determined by the range of the transmission coefficient of the scale unit 1, the accuracy of setting the transmission coefficient and the noise properties of the scale unit and can be quite large.

The device operates as follows. Upon the arrival of the next start pulse on the bus 17, the output voltage of the scale unit 1 is fixed in the analog memory 2 and converted into a digital code by an analog-to-digital converter 3. The scale unit 1 is controlled by a 4-bit code and provides a change in the transfer coefficient from 1 to 215, with the coefficient. Transmission can take values from the following series: 1, 2, 4, 8, 16, 32 ... 32768. The result of the analog-to-digital conversion is fed to the input of code converter b, where the current quantization interval is encoded with a binary 4-bit code (tab. 1). From the output of the code converter b, the interval code is fed to the first input of the ROM 7, to the second input of which from the speed analysis unit 12, a 4-bit operating interval code is supplied in which the current sample should be located. The ROM 7 generates a 4-bit gain code for the gain of the scale block 1. The firmware for ROM 7 is shown in Table 2. The correction code from the output of the ROM 7 is fed to the second input of the adder 8, the first input of which is supplied with the transmission coefficient code of the scale unit 1, which is stored in register 9. In this case, if the current sample falls into the interval quantization which at this

5, the moment is defined as working, the generated correction code is 0000; thus, after summing in the adder 8 with the transfer coefficient of the scale unit 1, the same value will be written to register 9. If the quantization interval of the current

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5

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5

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the sample turned out to be lower than the working interval, for example, by one interval, this means that the transmission coefficient of the scale unit 1 should be doubled and the generated correction code of the ROM 7 will be 0001. If the quantization interval of the current sample is one interval higher than the working interval, then in ROM 7, a code 1111 is generated, which is an additional code of the number - 1 and, if summed in adder 8 with the value of the transmission coefficient code, it will be reduced by 1, which corresponds to a reduction in the transmission coefficient by 2 times. The code of the transfer coefficient from register 9 is fed to the second input of the scale unit 1 and thereby determines the required transfer coefficient, which should be set by the next ADC start pulse 3 and the analog storage device 2. The input to the resistor 9 is carried out by the signal from the block 16 sync

The synchronization unit 16 is triggered by the signal to end the ADC conversion. This signal at the second output of the synchronization unit 16 appears with a delay relative to the signal at the first output by an amount equal to the settling time in the logic elements of the scale selection unit 5. The signal at the first output of block 16 appears, respectively, with the same delay with respect to the input signal.

The correction code from the output of the ROM 7 is supplied to the first input of the ROM 10, the second input of which is supplied with the code of the transfer coefficient from the output of the register 9. The firmware of the ROM 10 is shown in Table. 3. The ROM 10 generates a write inhibit signal, which is supplied to the first input of the AND-11 element, as a result of which the signal to end the conversion from the second ADC output does not pass to the write input of register 9. The write inhibit signal is generated as follows. When the transmission coefficient code values are close to the extreme values of 0000 and 1111, for some correction code values other than 0000, inverse values of the transmission coefficient code can be obtained, which will lead to device inoperability. To exclude this, in ROM 10, the current value is analyzed a transmission coefficient code and a correction code, and when a correction code is greater than a certain value for a given transmission coefficient code, a low level signal is generated at the output. So, for example, if the transmission coefficient code is equal to 1101, then with the value of the correction code 0011, 0100, 0101 and more, the passage of the recording signal will be blocked, since

the output of the adder 8 will overflow. Similarly, a write-lock signal is generated when crossing the lower limit of the range of variation of the transmission coefficient code.

The transmission coefficient code from the first output of the scale selection unit 5 is fed to the second input of the arithmetic logic unit 4, in which data is converted taking into account the transmission coefficient of the scale unit. In this case, the code of block 3 of the ADC is the mantissa of the number, and the code of the transmission coefficient is the order in base 2.

The correction code of the current interval from the second output of the scale selection unit 5 is supplied to the second input of the speed analysis unit 12, in which the working interval code is generated. The correction factor code from the output of the ROM 7 is fed to the first input of the ROM 13, the second input of which is supplied with the working interval code from the output of the register 15. The ROM 13 generates a correction code for the working interval, which is fed to the first input of the adder 14, in which , it is summed with the code of the working interval. Firmware ROM 13 is given in table. 4.

As can be seen from the data table. 4, the set value of the working interval code is determined by the correction code of the current interval (i.e., the rate of change of the voltage at the input of the device) and the value of the working interval code at the previous conversion step. For large values of the correction code of the current interval, i.e. at a high rate of change of voltage, the working interval is set in the middle of the range of the working intervals of the ADC quantization. At low rates of change, the working interval code becomes 10, which will provide one guard quantization interval. If in this case a positive voltage jump appears at the input of the device with a slew rate of not more than 6 dB during the analog-to-digital conversion period, the overload of block 3 of the ADC will be eliminated.

Since the working interval code is first written to register 15, and then the current interval code is written to register 9, the current interval code is generated in the following sequence. At the l-th clock of analog-to-digital conversion, a correction code for the current interval is generated in ROM 7 based on the working interval code generated on the (S) clock. Then the generated code

A current interval code is generated and recorded in the register 15. After that, the code value of the current quantization interval, which will already correspond to the new value of the working interval code, is generated and written into register 9.

The maximum value of the rate of change of voltage at the input of the device is 36 dB per analog-to-digital conversion cycle. The time of analog-to-digital conversion is reduced by 2 times compared with the prototype. In addition, unlike the prototype, the conversion accuracy at low signal values is determined only by the accuracy characteristics of the scale unit and is limited by its noise level. In the prototype, the minimum value of the converted signal is determined by the linearity of the analog storage device and with a modern component base is not less than 1-2 orders of magnitude higher than in the proposed device.

Claims (3)

SUMMARY OF THE INVENTION 1. An analog-to-digital conversion device with automatic measurement limit selection, comprising a scale unit, an analog storage unit, an arithmetic logic unit, a scale selection unit, a black synchronization unit, and an analog-to-digital converter, the information output of which is connected to the first input of an arithmetic logic block and with the first input of the scale selection block, the input inputs of the analog storage device and the analog-to-digital converter are the bus Start, exit arithmetic co logical block is an output bus, characterized in that, in order to increase the conversion speed while expanding the dynamic range, a speed analysis block is introduced into it, the first input of which is connected to the first output of the synchronization block, the second output of which is connected to the second input of the block scale selection, and the input is connected to the output. The end of the conversion of the analog-to-digital converter, the second input of the speed analysis unit is connected to the first output of the scale selection unit, the output of the speed analysis unit and connected to the third input of the scale selection block, the first input of the block scale and the second input of the arithmetic logic unit are connected to the second output of the scale selection unit, the information input of the analog-to-digital converter is connected to the output of the analog storage device, the information input of which is connected to the output of the scale unit, the second input of which is the input bus. 2. Device pop. 1, characterized in that the scale selection unit is made on a code converter, first and second read-only memory devices, a register, an NAND element and an adder, the first input of which is connected to the output of the first read-only memory, combined with the first input of the second read-only memory and is the first output of the block, and the second input of the adder and the second input of the second read-only memory are connected to the output of the register, which is the second output of the block, the output of the adder is connected to the first input of the register, the second input of which is connected to the output of the element, the first input of which is connected to the output of the second read-only memory device, and the second input is the second input of the unit, the first input of the first read-only memory device is connected to the output of the code converter, the input of which is the first input of the unit, the second input of the first constant of the storage device is the third input of the block. 3. The device according to claim 1, with the exception that the speed analysis unit is made in series-connected. a fixed storage device, an adder and a register, the output of which is the output of the unit, and its first input is the first input of the unit, the second input of which is the first input of the permanent storage device, the second input of which and the second input of the adder are combined and connected to the output of the register . thirteen 1783610 14 table 1 table 2 Table 3 Table a