RU1781825C - Threshold decoded of convolution code - Google Patents

Abstract

The invention relates to communication technology and is intended for use in apparatus for transmitting discrete information. The aim of the invention is to increase the noise immunity of the device. The device comprises encoders, syndrome analyzers, threshold detectors, a modulo two adder, a shift register, an information sequence delay block, and an error corrector. This allows it to be fully used for a wide class of both self-orthogonal and orthogonalization of other convolutional codes. 2 silt 5 tablets

Description

The invention relates to communication technology and is intended for use in apparatus for transmitting discrete information.

A convolutional code decoding apparatus is known, comprising an encoder, a syndrome analyzer, a correction inhibit block, an error burst detection block, and other elements for detecting error bursts and interrupt correction for a while to stop possible error propagation. Its disadvantage is low efficiency due to inaccurate determination of the boundaries of the location of the error packet

A device for threshold decoding of convolutional codes is known, comprising shift registers, modulo two adders, a threshold element, and a key that breaks the feedback in the syndrome register in the event of an error propagation effect. In this case, the depth of reproduction is limited by the code restriction length of the code used. Its disadvantage is a limited class of codes

for which it is applicable (the device is intended primarily for self-orthogonal convolutional codes).

Closest to the technical nature of the proposed device is a convolutional threshold decoder containing a serial encoder, a first syndrome analyzer, a first threshold detector and a first correction inhibit block. the output of which is connected to the corresponding input of the syndrome analyzer, as well as an error packet detection unit and a second threshold detector and a second correction inhibit block connected in series, the output of which is connected to the first input of the error corrector, while the output of the first inhibit block is connected to the input of the error packet detection unit correction, and the output of the error packet detection unit to the correction control input, the output of which is connected to the second input of the first correction prohibition block directly and through b control signal delay lock

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the second input of the second correction inhibit block, and the output of the second correction inhibit block is connected to the corresponding inputs of the additional syndrome analyzer, while the input of the error corrector is connected to the encoder output through the delay block of the information sequence, and the encoder outputs are connected to the corresponding inputs of the delay block.

The disadvantage of this device is its low noise immunity,

In the known device, the conclusion about the occurrence of the error propagation effect is made by the frequency of single symbols at the output of the threshold element generating the error vector symbols (correction symbols). If this value exceeds a certain threshold value, which is usually equal to the correcting ability of the code, the correction of the information sequence delayed for some time in the shift register is prohibited. Since the device can correct a significant part of errors, the multiplicity of which exceeds the multiplicity of guaranteed correctable errors, the known device in this case will prohibit correction and, in fact, introduce an error.

The aim of the invention is to increase noise immunity by changing the algorithm for detecting error packets.

This goal is achieved in that in a device containing a series-connected encoder, an information sequence delay unit and an error corrector, as well as a first syndrome analyzer, one of the outputs of which is connected to the corresponding output of the encoder, and the other is the input of the device, while its outputs are connected to the inputs of the first threshold detector, the output of which is connected to the input of the first error analyzer, as well as the second syndrome analyzer, the outputs of which are connected to the corresponding inputs of the WTO the second threshold detector, the output of which is connected to the corresponding input of the second syndrome analyzer, a second encoder, an adder modulo two, and a shift register are introduced, while the output of the first threshold detector is connected to the corresponding input of the second encoder, the first output of which is connected to the corresponding input of the second syndrome analyzer and its second output is connected to the first input of the adder modulo two and the input of the shift register, while the second input of the adder modulo two is connected to the output of the second thresholds og detector, and its output is connected to the corresponding inputs of the first and second analyzers of the syndrome, the second encoder and the shift register.

The reliability of the achievement of the goal is confirmed by the following. In the known device, the conclusion about the occurrence of a burst of errors leading to their propagation is made when the frequency of individual correction symbols arriving at the output of the first threshold detector is increased. If their number exceeds a certain threshold value N, the fact of propagation of errors is recorded and their correction in the previously delayed information sequence is prohibited. The problem lies in the correct choice of the threshold value N. If it is selected one more than the multiplicity of guaranteed errors.

0N J / 2 + 1,

where J is the number of independent orthogonal checks in this code, the device does not allow to correct a significant part of errors that could be corrected, since threshold decoding corrects a significant number of errors and higher multiplicity, the configuration of which is almost impossible to take into account in advance. If you select the threshold value N

0 is somewhat more than the multiplicity of errors guaranteed by the code; the decoder will skip a significant part of the multiplied errors.

To confirm the above, let us consider the following example of an orthogonalizable code having a code rate of R 1/2 and forming a polynomial f (D) 1 + D6 + D7 + D9 + D10 + D11. Figure 2 shows a fragment of a circuit device, including

0 some blocks and the relationships between them that are common to the known and proposed device. Symbols of the information sequence 1 (0) together with the symbols of the additive schema

5 sequences Ei (D) go to the input of encoder 1 where they are multiplied by the generator polynomial f (D). The result is a sequence Z (D) of the form: Z (D) l (D) f (D) + Ei (D) f (D)

0 This sequence is fed to the input of the analyzer of Syndrome 2, where it is added to the symbols of the test sequence P (D) and superimposed on no additive noise sequence

5 E2 (D), resulting in a sequence of S (D) syndrome symbols of the form

S (D) P (D) + E2 (D) + l (D) f (D) + Ei (D) f (D). Given that F (D) l (D) f (D),

the sequence S (D) will have the form; S (D) Ei (D) f (D) + E2 (D) (1)

The symbols of this sequence are combined into independent checks as follows: Ai S0; A2 Se; Az S. Az Sg; As Si + 5s + 5y: Ae 84 + Se + Sn. The test results are analyzed in the first threshold detector 3. Since for this code the number of independent orthogonal checks is J 6, all errors up to three times inclusive and some errors of higher multiplicity will be corrected. Correction is as follows: if more than three single characters are present at the inputs of the threshold detector, it generates a single character arriving with some delay at the inverter input, where it is added to the sequence I (D) + Ei (D), also somewhat delayed by time no. Tables 1 and 2 give examples of correctable five and six multiple errors in the information sequence of correctable devices. Column B in these tables contains the sequence of characters Ea (D) superimposed on the test sequence P (D), the next 12 columns of the table contain the error vector symbols Ei (D) that are shifted sequentially in the information register, and the next 12 columns are arranged sequentially symbols of the analyzed segment of the sequence S (D) shifted in the syndrome register, the sequence of correction symbols generated by the first threshold detector is placed in column F - the symbols output are placed in columns C and D one correctable and corrected sequence of characters, respectively, Table 3 shows an example of a multiplied 5-fold error that is not detected by the device, since when decoding the device generates only three correction characters (column F), which is less than the corrective ability of the code. Table 4 gives an example of a 5-fold error, the propagation of which can be detected. Thus, it is necessary that a device with a greater degree of certainty distinguishes a correctable error of a large multiplicity from a multiplied unrecoverable error,

In the proposed device, the conclusion about the propagation of errors is made not upon the increase in the frequency of single correction symbols, but on the basis of the analysis of this sequence. Suppose that an error has occurred in the communication channel, the multiplicity of which exceeds the correcting ability of the code, but is correctable by the device. In this case, at the output of the threshold detector, correction symbols whose sequence E (D) exactly matches the sequence Ei (D) superimposed in the communication channel on the information sequence I (D) will appear. In this case, each single symbol of the correcting sequence Ei (D) through the feedback loop is supplied to the corresponding inputs of the syndrome analyzers, correcting the symbols of the sequence S (D). If the error is correctable, then the unit symbols belonging to the sequence E2 (D), in this case not

5 affect the correct formation of the sequence Ei (D), it follows that we multiply it by the generatrix polynomial f (D), we get a new syndrome S (D), the analysis of which gives the same vector Ei (D).

0 This syndrome will have the form S (D) Ei (D) f (D).

Having analyzed this syndrome, we obtain a new sequence Ei (D), which, in the case of a correctable error, will coincide5 with the sequence Ei (D) If the error is not correctable, the S (D) syndrome will be incorrectly corrected and the resulting error propagation will lead to sequence inequality Ei (D) and

0 Ei (D) and, therefore, to the inequality of the sequences Ei (D) and Ei (D). Having formed the sequences Ei (D) and Ei (D) in the proposed device, and comparing them element by element, we can uniquely

5 highlight all correctable errors, including those whose multiplicity exceeds the corrective ability of the code.

To implement the proposed algorithm, the following devices were introduced into the device: a second decoder, multiplying the sequence Ei (D) by the generatrix polynomial f (D), a shift register that delays the characters of the correction sequence Ei (D) by the time this

5 of the sequence and an adder modulo two, performing step-by-step comparison of the sequence Ei (D) n Ei (D). The listed blocks entered into the device make it possible to implement the error correction algorithm laid down in the proposed device and therefore are significant differences.

The essence of the invention consists in increasing the noise immunity of the device beyond

5 by changing the error detection algorithm,

1 is a block diagram of a threshold convolutional decoder; Fig. 2 is a fragment of the device of the invention explaining its operation.

The device comprises an encoder 1, a first syndrome analyzer 2, a first threshold detector 3, a second encoder 4, a second syndrome 5 analyzer, a second threshold detector b, an adder modulo two 7, a shift register 8, an information delay unit 9, and an error corrector 10.

Encoder 1 is a polynomial multiplier device. It contains a shift register 1-1, a block of adders modulo two 1-2 and forms a sequence

Z (D) (D) f (D) + E1 (D) f (D). (2)

It is connected to one of the inputs of the first analyzer of syndrome 2 and the input of the information storage unit 9.

Syndrome 2 analyzer includes a shift register 2-2 and adders modulo two, allowing to form and correct the sequence of characters of the syndrome S (D). Its outputs are connected to the inputs of the first threshold detector 3.

The first threshold detector 3 is a majority element having J inputs. It forms a single signal at the output in the presence of J / 2-H and more than single signals at its inputs and is intended to form the characters of the sequence E (D). It is connected to the inputs of the second encoder 4 and the first identifier of syndrome 2.

The second encoder 4 is designed to form a sequence of additional syndrome

S (D) Ei (D) f (D) t (3)

It contains a shift register 4-1, the adder block modulo two 4-2 and is connected to the input of the second syndrome analyzer 5 and the corresponding adder input modulo two 7.

The second syndrome 5 analyzer includes a shift register and modulo two adders that allow the analysis and correction of the S (D) sequence. It is connected to the inputs of the second threshold detector 6.

The second threshold detector 6 is a majority element having J inputs and forming a single symbol at the output in the presence of J / 2 + 1 or more single symbols at its inputs. It is designed to form an E (D) sequence and is connected to the corresponding adder input modulo two 7, as well as to the input of the second syndrome 5 analyzer.

The device operates as follows.

Symbols of the input information sequence I (D) superimposed on

of them by the symbols of the additive noise sequence Ei (D) through the first input of the device 11 are fed to the input of the encoder 1, where they are delayed by the number of clock cycles determined by the degree of the generating polynomial f (D). At the same time, from the outputs of bits of the shift register 1-1, the numbers of which are determined by nonzero coefficients of the generating polynomial f (D), the symbols delayed in it are fed to the adder block modulo two 1-2, where the input sequence is multiplied. Next, the sequence Z (D) of the form (2), which is the result of multiplying the input information sequence by the generating polynomial, is fed to the input of the first analyzer of syndrome 2, where on the adder modulo two 2-1 is added to the verification sequence PfD) and the additive noise the sequence E2 (D) coming from the second input of device 12. As a result, syndrome S (D) of the form (1) is formed. This syndrome enters register 2-2, the corresponding bits of which are separated by adders modulo two and have outputs to the first threshold detector 3, which generates a sequence of correction symbols Ei (D), fed through the feedback circuit to the inputs of the corresponding adders modulo two to correct the characters of the sequence of the S (D) syndrome. Figure 2 shows the structure of a syndromic sequence analyzer 2 for the above example.

The sequence Ei (D) thus formed is fed to the input of the second encoder 4, where in the same way as in encoder 1 it is delayed in register 4-1 and multiplied by the generator polynomial f (D) using the adder block modulo two 4-2. The resulting syndrome S (D) of type (3) is fed to the input of the second analyzer of the syndrome in which, similarly to the analyzer of syndrome 2, it is analyzed and corrected. A second threshold detector connected to it forms a new sequence of correction symbols Ei (D) which, through the feedback loop, corrects the sequence of syndrome S (D) and enters the first input of the adder modulo two 7. the symbols of the sequence Ei ( D), previously delayed in register 4-1 of encoder 4. Bearing in mind that in order for the error to be corrected by a convolutional code, a protective interval between error packets equal to the length of the code restriction NA is required, the number of bits all registers in the device must be chosen equal to the highest power generator polynomial f (D). The exception is the register of the information delay unit 9; its length is twice the number of bits. Correction symbols delayed in shift register 8 are input to error corrector 10, which is an adder modulo 2, the second input of which receives elements of a distorted information sequence of symbols previously delayed in delay unit 9. If the sequence of correction symbols Ei (D) formed correctly, they are subtracted from the channel sequence and, after correction, it is output to the output of device 13.

If an uncorrectable error occurs that multiplies with during decoding, the sequences Ei (D) and Ei (0) will not coincide, since in this case the causes that cause them will be different. Their mismatch is detected by an adder modulo two 7 which gives a signal to the installation inputs of the registers of the first and second analyzers of syndromes 2 and 5, the second encoder 4 and shift register 8, setting them to the zero state. In this case, for a time equal to the length of the two code constraints, the channel information sequence will not be corrected.

Technical and economic advantages of the claimed object in comparison with the prototype consist in its greater noise immunity, due to the full implementation of the correcting properties of the code. The propagation of errors in the known device is prevented by introducing a limit on the number of generated correction symbols, which does not allow to correct some of the errors, the multiplicity of which significantly exceeds the multiplicity of guaranteed error correction. The proposed device allows to correct all errors corrected by the code by changing the algorithm for recognizing uncorrectable errors. Table 4 shows an example of multiplying a five-fold uncorrectable error. If in the known device prohibit the correction of five or more error rates, then errors, examples of which are given in tables 1 and 2 will not be corrected. A known device can detect an uncorrectable error.

Table 5 shows an example of error detection shown in Table 4. Columns A and B of this table contain symbols of distorted test and information sequences, respectively.

in column F the symbols of the correcting sequence Ei (D) are placed, in columns K and L are the symbols Ei (D) and Ei (D) arriving at the inputs of the adder modulo two 7 7, in column M are the symbols of the delayed correcting sequence Ei ( D), in columns C and D the symbols of the input distorted information sequence I (D) and the same corrected sequence, respectively, in addition to the columns S-SINDROM there are symbols of the syndromes S (D) and S (D), respectively, shifted to shift registers of the corresponding syndrome analyzers.

5 The indicated sequences are taken at the points marked in FIG. 1. The worst case are errors in which, if they multiply, the number of unit characters at the output of the threshold device

0 correction does not exceed the multiplicity of guaranteed correctable errors (see table 3). However, in this case, the reproduction is not infinite, and the number of multiplied characters, as a rule, does not exceed the number

5 characters of correction. Thus, the proposed device in the considered example (see table 5) for an uncorrectable propagated error more than halves the number of errors at the output and

0 allows you to correct all correctable errors, the multiplicity of which exceeds the multiplicity of guaranteed errors,

The use of the proposed device

5 in channels with grouping errors allows the use of orthogonalizable convolutional codes. The authors performed statistical tests of the device in the VHF radio channel described by model Guillaubert. The test results showed that the proposed device can reduce the number of errors by an average of 8%.

Claims (1)

Claim 5 A threshold convolutional decoder comprising a first encoder, the input of which is the first input of the device, the first and second outputs of the first encoder are connected respectively to the input of the delay block 0 of the information sequence and the first input of the first syndrome analyzer, the second input and outputs of which are connected respectively to the second input of the device and the inputs of the first threshold 5 detector, the second analyzer of the syndrome, the outputs of which are connected to the inputs of the second threshold detector, the output unit and information sequence delays are connected to the first input of the error corrector, the output of which is device output, characterized in that, in order to increase the noise immunity, an adder modulo two shift registers and a second encoder are introduced into it, the first output of which is connected to the first inputs of the adder modulo two and a shift register, the output of which is connected to the second input of the error corrector, the output of the first threshold detector is connected to the third input the input of the second encoder, the second output of which is connected to the first input of the second syndrome analyzer, the output of the second threshold detector is connected to the second input of the second syndrome analyzer and adder modulo two. the output of which is connected to the second inputs of the shift register and the second encoder, the third input of the second analyzer of the syndrome and the fourth input and 928L8a El TABLE 4 Si 92818M Z.L  thirteen (rig. 2