RU1780157C - Level-fixing device - Google Patents

Abstract

The invention relates to a pulsed technique and can be used to stabilize a constant component in pulse amplitude analysis. The aim of the invention is to expand the scope of use of the device by suppressing relatively slow changes in the DC component of the input signal. This goal is achieved in that in the level fixing device containing the input bus 1 connected to the direct 3 and parallel 2 channels, the outputs of which are connected to the corresponding inputs-2 of the adder 4, the output of which is connected to the output bus 5, the direct channel 3 contains the voltage follower 9, the input of which is the input of the direct channel 3, the pair / wire rope 2 is composed of a signal minimum detector 6, a stabilized positive current generator 8, a clamp capacitor 7, and a voltage follower 10, the input of the detector 6 is minimized and the signal is connected to the input of the parallel channel 2, and the output is with the output of the stabilized current generator 8, one of the capacitor plates 7 and the input of the voltage follower 9, the other is a latching capacitor 1 connected to a common bus, and the output of the voltage follower 9 is connected with the output of the parallel channel, the output of the isolator 9 of the voltage Q of the forward channel 3 is connected to the output of the direct channel. The device extracts pulses from the input signal whose slew rate exceeds a threshold and generates them relative to a predetermined level. 4 ill. (Ls • h00 "case VI. The invention relates to the field of pulsed technology and can be used to stabilize a constant component in an amplitude analysis of pulses. A level locking device is known that contains a limiter amplifier, a pulse shaping driver, two sources reference voltage, isolation capacitor, low-impedance divider, transistor switches, high-impedance divider and source follower. The disadvantages of the device are the limitation of sensitivity by the threshold of the amplifier - limit , The inability to work if the DC bias of the input signal level exceeds the threshold limiting amplifier, the presence of significant distortion of the desired signal due to work

Description

keys, a tedious process of rep / dividing the coefficient of division of resistive dividers. A device is also known, containing the delay element, i-ti-sBepTop, comparator, amplifier-limiter, | coupling pulse shaping, transistor switch, reference voltage source, isolation capacitor. The disadvantages of the device are the need to fix the potential at the input) e in the initial state, limit the sensitivity to the threshold of the comparator, the presence of pulsed noise at the output due to the operation of the transistor, The closest to the proposed device is a level lock containing a direct channel formed by the serial connection of the repeater, an isolation capacitor, a delay element, and a parallel channel formed by the serial connection of two diode-resistor circuits ochek and i-iHBepTHpyioatero integrator, the outputs of both channels are connected to an input of the summing amplifier. The charge and discharge time constants of the parallel channel are tuned to maximize compliance with the same parameters of the forward channel, and the delay line in the forward channel is adjusted according to the signal delay in the parallel channel. Thus, when pulses arrive at the input of the device in the direct and parallel channels, constant level displacements equal in magnitude but opposite in sign will occur. The STS / S mix supplied to the input of the Dmatopus is very much compatible, and the output remains the pulses that passed through the direct channel, which are fixed on a given hazard, The disadvantage and the known device are a laborious process of two-stage adjustment before matching the time dependent parameters s directly parallel (ala, the need for precision clementoses to ensure the stability of these parameters, uncompensated voltage drift at the output of the integrator when the constant of the input signal. The aim of the invention is to expand the field of use of the device by suppressing relatively slow changes in the constant component of the input signal. This goal is achieved by the fact that the level fixing device contains an input bus connected to direct and parallel analo connected to the corresponding inputs of the adder, the output of which is connected to the output bus, while the direct channel contains a voltage follower, the input of which is the input of the direct channel, in parallel The first channel is composed of a signal minimum detector, a stabilized positive current generator, a fixing capacitor, and a voltage follower, the input of the signal minimum detector being connected to the parallel channel input, and the output connected to the stabilized current generator, one of the capacitor plates and the voltage follower input On the other hand, on the other hand, the latch of the latching capacitor is connected to the common bus, and the output of the voltage follower is connected to the 1-way parallel channel, the output of the voltage follower is direct m kanal-e is connected to the direct kznal exit. Comparative analysis with the prototype shows that the claimed device is distinguished by a new composition of direct and parallel channels. The direct channel contains only a repeater, and the parallel channel consists of a minimum detector with a fixing capacitor, a toke generator, and a repeater. The use of a minimum input signal detector in conjunction with a positive current generator connected to its fixing capacitor makes it possible to extract a component with a relatively low slew rate from the input signal, subtracting which from the initial signal it is possible to obtain input pulses, C (| preset voltage level 81-; and. In Fig. 1 is a diagram of a fix device, 1K1.1 level, which shows the input of device 1, parallel 2 and pr Muf 3 channels, adder 4, output us 5, detector 6 of the minimum signal, a fixed capacitor 7, a generator 8 of stabilized positive current, repeaters 9 and 10. N Fig, 2 shows the time diagram of the sweat of the device, and Fig. 2a shows .. ..- I input signal devices where the useful signal (pulse base) is conventionally depicted at a slightly increasing level with the following characteristics: differential due to 1.; m, by the differentiating effect of the chains of the sprometer

the path, in Fig. 26 shows the voltage at the clamp capacitor, in Fig, 2c a separate signal at the output of the device.

In FIG. Figure 3 shows a timing diagram of the operation of the device when the input signal (Fig. 3a) contains a low-frequency component. On Fig, 36 shows the signal at the output of the device.

Fig. 4 is a schematic diagram of a level fixing device, from which in addition to fig. 1, op-amp 10-14, transistors 15.16, diode 17, capacitors 18-20, resistors 21-32, and a voltage reference voltage source are shown (Jo 33.

During operation of the level locking device, two modes are possible. The first mode, which takes place in the time intervals ti, t5 (Fig. 2), is realized when the slew rate of the input signal is less than the threshold speed, i.e., the charge rate of the fixing capacitor 7 by the current generator 8. In this case, the minimum detector 6 supports capacitor 7 potential equal to the potential at the input of the device.

Thus, at the output of adder 4, a voltage level is observed that differs from the summation constant Uo by the total displacement in the used OY UCM (Fig. 2c), which has a value not exceeding tens of millivolts, and can be compensated by either the corresponding correction Uo or by offset correction in any OY device.

The device switches to the second mode when the slew rate of the input signal exceeds a threshold value determined by the charge rate of the capacitor 7 from the current generator 8 (time interval t3 in Fig. 2). The time T2 spent on the transient in the minimum detector has practically no effect on the output signal. After this time, the minimum detector 6 no longer tracks the input signal, making it possible for the capacitor 7 to charge with the current of the generator 8, as a result of which the voltage on this capacitor rises at a given threshold speed. Since this increasing voltage level is subtracted by the adder 4 from the initial signal, the threshold slew rate should be selected several orders of magnitude lower than the slew rate of the leading edge of the working pulses, which will allow you to subtract the slowly rising component from them without significantly reducing their amplitude.

When, during the drop in the input pulse, the voltage at the input of the device becomes lower than the voltage at the fixing capacitor 7, after some time t4 (Fig. 2), more than several tens of nanoseconds, the parallel channel will again track the input signal.

Over the Breach ti, the voltage across the capacitor 7 slightly increases the input voltage, which will lead to the appearance of a small negative surge at the output of the device (Fig. 2c), which, however, is not essential for the subsequent amplitude analysis.

Fig. 3 illustrates the operation of the device G at the time of the change in the constant component of the input signal, provided that the rise rate of this difference does not exceed the threshold rise rate indicated in Fig. Behind the dotted line emanating from the bases of the working pulses. Fig. 36 shows the same pulses fixed at the level Uo defined by voltage source 33 (Fig. 4);

Fig. 4 shows a variant of the circuit diagram of the inventive device, which shows the elements contained in the functional blocks shown in fig. 1. Transistor 15 provides a sufficient value of the discharge current con, the censor 7 m reduces the time T4 (ph. 2), the diode 17 eliminates the saturation of the op-amp 12 at time points: h. Resistor 23 prevents the possible generation of op-amp 12 at a low frequency. The purpose of the remaining elements is obvious,

The device uses OA KR544UD2A (pos. 10-14 in FIG. 4), transistors KT345B (15) and KP103E (16). diode KD521A (17).

The operation of the inventive device showed that, unlike the known device of a similar purpose, it provides the specified characteristics without any adjustment of 0 (time dependent parameters. For this, the fixation level offsets are determined only by the temperature drift of the bias voltage used by the op amp , while in the known device the bias of the fixation level may occur due to shifts of the constant level of the input signal and the mismatch of the dependent parameters in the forward and parallel channels x

A feature of the claimed device is that small changes in the threshold slew rate do not affect the efficiency of the device, provided that this speed is optimally selected. Such a device can significantly reduce the time requirements of the drive elements and simplify the process of setting up and operating the device.

Claims (1)

The claims A level fixing device comprising an input bus connected to direct and parallel channels, the outputs of which are connected to the corresponding inputs of the adder, the output of which is connected to the output bus, the direct channel containing a voltage follower, the input of which is the input of the direct channel, characterized in that, in order to expand the scope of use of the device by suppressing relatively slow changes in the constant component of the input signal, in parallel the channel includes a signal minimum detector, a stabilized positive current generator, a fixing capacitor and a voltage follower, the input of the signal minimum detector connected to the input of the parallel channel, and the output to the output of the stabilized current generator, from one of the capacitor plates and the voltage follower input, of a friend the latch of the fixing capacitor is connected to the common bus, and the output of the voltage follower is connected to the output of the parallel channel, the output of the voltage follower in the forward channel is connected with direct channel output. .1 and and about / and 5 about / 7l 1 / - ,- -SB-YI J., ija3