RU1774518C - Stereotelevision camera with automatic focusing - Google Patents

Abstract

The invention relates to stereo television and can be used in technical vision systems under conditions when the size of the recorded objects is commensurate with the vertical size of the television camera raster. The purpose of the invention is to improve accuracy. The device generates focus control signals for the first and second television cameras based on the analysis of the parallax value when observing an object with two television cameras whose optical axis of the lenses are parallel. In this case, the time delay of the video signal of one television camera relative to the video signal of another is determined. The parallax value is determined at the center of each line of television scan. 1 ill.

Description

The invention relates to optical television technology and can be used in photoelectronic devices for automatically focusing camera lenses, in the technical vision systems of robots.

A device for automatic focusing is known, comprising two pulse shapers, each of which is connected to a corresponding transmitting television camera (PTC). a synchro-generator, the output of which is connected to the first inputs of the first and second PTCs, the second inputs of which are connected respectively to the first and second outputs of the focusing unit, as well as the comparison unit, series-connected gate pulse generator and a pulse width converter, the output of which is connected through the comparison unit to

the duration of the converter is the voltage whose output is connected to the input of the focusing unit, as well as a single vibrator, the first and second inputs of which are connected respectively to the second output of the first pulse shaper, the second output of which is connected to the first input of the gate pulse shaper, and the output of the single-vibrator is connected with the second input of the comparison unit, and the output of the second pulse shaper is connected to the second input of the gate pulse shaper. However, this device has a low resolution in the process of tracking objects, as well as insufficient focus accuracy of the PTC.

The closest is a device containing two pulse shapers, each of which is connected to the corresponding

2

SL

Jb

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PTC, a sync generator, the output of which is connected to the first inputs of the first and second PTC, the second inputs of which are connected respectively to the first and second outputs of the focusing unit, as well as the comparison unit (Cooper L.K., Fulkerson L.K. Lineina I.S. for automatic focusing of cameras. - Electronics, 1978, v. 51, No. 9 (536), pp. 54-60.

However, this device has a complex focusing system and a mechanical system for combining images, which do not provide high accuracy of focusing in the event that several objects fall in front of the PTC.

The aim of the invention is to improve the accuracy of focusing,

The goal is achieved in that a stereo television camera with automatic focusing, containing a sync generator, the output of which is connected to the first inputs of the slave and master PTC, the second inputs of which are connected respectively to the first and second outputs of the focusing unit, as well as a comparison unit, a master oscillator is introduced, the fourth input of which connected to the input of the clock, a pulse shaper, the first input of which is connected to the first output of the master oscillator, and the second and third inputs are connected respectively to the outputs in home and host PTC, an address counter, the second input of which is connected to the second output of the master oscillator, a control unit, the first input of which is connected to the output of the clock generator, the second input of which is connected to the third output of the master oscillator, and the third and fourth inputs are connected respectively to the first and second pulse generator outputs, the first output of the control unit is connected to the third input of the address counter, the fourth output of the control unit is connected to the input of the master oscillator and the first input of the address a read-only memory block, the first group input of which is connected to the second group output of the address counter, the second group input of which is connected to the second group output of the control unit, the third input of which is connected to the fourth output of the control unit, and the group output to the first input of the block comparison, a memory unit, the first input of which is connected to the third output of the address counter, the second group input of which is connected to the third group output of the control unit, and the group output to the second input of the block alignment, a code generator, a first input coupled to the first output of the address counter, a second input coupled to a first output of the oscillator, a third input coupled to the output of

comparison, the fourth input of which is connected to the fourth output of the control unit, a code-voltage converter, the group input of which is connected to the output of the code generator, and the output is connected to

0 input focus unit.

Figure 1 presents a diagram of the proposed device; figure 2 - diagram of the pulse shaper; Fig. 3 is a diagram of a master oscillator; Fig. 4 is a diagram

5 control units; Figures 5 and 6 are diagrams of the operation of the control unit.

The auto focus stereo television camera contains a slave PTC 1, a sync generator 2, a focusing unit 3, a leading PTC 4, a pulse shaper 5, a driver 6, an address counter 7, a control unit 8, an operational memory unit 9, a memory unit 10, a unit 11 of comparison, code converter 12 is voltage, as well as code generator 13.

The device operates as follows.

The PTC - slave 1 and master 4 are positioned apart from each other at a certain distance B (base) so that the optical axes of their lenses are parallel, but some linear parallax is achieved. In this case, the video signals generated by the PTC, the electron beam sweep of which

5 are strictly synchronous, shifted in time, The closer the subject to be focused on, the greater the offset between its right and left images, according to the formulas

0

 , p Bf K G

where V is the scanning speed of electron beams;

P - linear parallax; B is the base;

f is the distance from the optical center to the photo target onto which the image is projected;

I is the distance to the focused object.

In this case, the video signal from the left image of the object lags behind in time by goth 5 of the video signal corresponding to the right image.

Initially, the address counter 7, control unit 8, memory unit 10, code former 13 are reset. The master oscillator 6 simultaneously generates clock pulses with a frequency of 40.10, 2.5 MHz and 20 KHz, clock pulses with a frequency of 20 KHz from its fourth output are fed to the input of the clock generator 2, which synchronizes the horizontal scanning of the PTC, where they are converted to the horizontal pulses of the scanning PTC. The horizontal clock pulses (SR) come from the output of the clock generator 2 to the first input of the control unit 8, and at its fourth output, the Log.1 level is set with the leading edge of the first horizontal pulse CP, which is fed to the input of the master oscillator 6, the first input of the address counter 7, the third input of the online memory unit 9 and the fourth input of the code generator 13. As a result, from the first output of the master oscillator 6, clock pulses with a frequency of 10 MHz are constantly supplied to the first input of the pulse generator 5 and to the second input of the code converter 13, from the second output of the master oscillator 6, clock pulses with a frequency of 2.5 MHz come to the second input of the address counter 7 , and from the third output of the master oscillator 6, clock pulses with a frequency of 10 MHz are received at the second input of the control unit 8. The operational memory unit 9 is set to the recording mode, and the code generator 13 remains in the reset mode (zero setting), the address counter 7 starts the counting. The video signals from the slave PTC 1 and the leading PTC 4 are supplied separately to the second and third inputs of the pulse shaper 5, respectively, which also separately but synchronously samples the signals from each PTC with a frequency of 10 MHz, which from the first and second outputs respectively pass through the third and fourth the inputs of the control unit 8 to its second and third group outputs are sequentially distributed separately into groups of four streams each. Four streams of discretized signals of the slave PTC 1, samples from the second group output of the control unit 8 are supplied to the second group input of the operational memory unit 9 through the third group, where the samples of one of the four streams are stored in one memory element. Functionally (and structurally), the operational memory unit 9 is divided into four parts, each of which stores 512 samples of the image line. Samples are recorded in each part separately in the active part of the horizontal pulse for each line of the image; in the first part - the recording of the first line, in the second - the recording of the second line, in the third and fourth - respectively, the recording of the third and fourth lines. Addressing

operational memory unit 9 is implemented through the address counter 7 from its second group output through the first group input of the operational memory unit 9. For one address, four samples of the image line are recorded separately in four corresponding memory elements, in one part of the operational memory unit 9, and one image line is recorded in 128 addresses, and the addressing is repeated with the recording of a new line. Resetting of the address counter 7 upon completion of recording of each image line is carried out at all times on the trailing edge of the line pulse CP through its third input from the first output of the control unit 8. Sync pulses controlling separately the recording of each image line consist of four streams. The clock pulses from the First group of outputs, synchronized by the CP pulses that come from the output of the clock 2 to the first input of the control unit 8, come through its second group output to the second group input of the operational memory unit 9. These clock pulses control the recording of each line of the image in turn memory elements of the corresponding part of the operational memory unit 9.

The control clock pulses of the second group of outputs, consisting of four streams, also pass through the second group output of the control unit 8 to the second group input of the operational memory unit 9. They control, sequentially and separately, the recording of every four samples from 512 lines of the image in every four memory elements of each part of the operational memory unit 9, synchronized pulses of the master oscillator 6 with a frequency of 10 MHz, which come from its third output to the second input of block 8 control, in the process of addressing, at the time of recording the samples, upon reaching the address corresponding to the digital code 64, a control pulse from the third output of the address counter 7, which allows for vivo Recording four counts each of first - the fourth picture line leading PTK 4.

Functionally (and constructively), the memory unit 10 is divided into four parts, each of which separately remembers four samples of the image line. Four streams of samples of the leading PTC 4 of the first group from the third group output of the control unit 8 through the second group Gtlock 10 memory separately enter the information inputs every four cops of memory (D-flip-flops) parallel mm i parts. The memory elements are stored in one sample. The clock pulses controlling the process of writing separately each image line to the memory elements, each part of the operative memory unit 9, control and writing four samples of each image line separately to the trigger memory elements, to one of the four parts of the memory unit 10 and enter their enable inputs through the second group input of the memory unit 10 from the third group output of the control unit 8 (second group of outputs). Thus, in the memory block 10, four samples of each first to fourth line of the image are stored for one address corresponding to the digital code 64. Thereby, a microfield of the image is formed. With the trailing edge of the fourth horizontal pulse CP at the second input of the control unit 8, a logic level is set at its fourth output. O, as a result of which, from the second output of the master oscillator 6, the second input of the address counter 7 receives clock pulses with a frequency of 10 MHz, from the third output of the master oscillator 6 connected to the second input of the control unit 8, clock pulses with a frequency of 40 MHz are received, the operational memory unit 9 is set to the information reading mode, the code generator 13 is set to the counting mode, at first the first group of outputs of the second group output of the control unit is log level 0. Samples are read until the next horizontal line pulse CP arrives (on the leading edge of the pulse). Thus, the reliability of the operation of the device, and hence the focusing of the PTC, is achieved by synchronizing the operation of all units of the device at any time. From the group output of the operational unit 9, memories are read out over sixteen channels simultaneously for one address from each memory element of all parts, according to one sample of the slave PTC 1 from the comparison unit 11 through its first group input. All information is read at 128 addresses with a frequency of 10 MHz. The state of the triggers of the memory unit 10 does not change at the time of reading. At the group output of the memory unit 10 on sixteen channels, samples of the leading PTC 4 are installed, which is connected to the second group input of the comparison unit 11. In comparison block 11, each uniquely located sample of the image line of the slave PTC 1 recorded in the memory element of the part of the operational memory unit 9 with a specific address is also compared with the uniquely located sample of the image line of the master

PTC 4 recorded in the trigger element of the part of the memory unit 10 by level. If sixteen samples of four lines of the image of the slave PTC 1 do not match

sixteen samples of the image lines of the leading PTC 4, at the output of the comparison unit 11, which is connected to the third input of the code generator 13, a logic level O is formed, and the code generator 13

0 operates in the mode of increasing the count in the direct code and outputs from its group output to the input of the converter 12 a code - voltage, seven-digit code words. Thus, the code generator 13 counts out the number of sixteen mismatched sixteen samples of the slave PTC 1 with sixteen samples of the master PTC 4. If there is no match up to address code 64, seven-digit code words are output

0 code shaper 13 is converted from ESL to TTL levels, and code shaper counters are reversed. When the output level of the comparison unit 11 matches, the level of log.1 is established, as a result of which the code generator 13 stops the count and fixes the code at the group output. The seven-bit code word carries information about the amount of movement of the PTC carriage, and its polarity is the logical level of

0 direction of travel. The voltage corresponding to the code from the output of the code-to-voltage converter 12 is supplied to the focusing unit 3, which, in turn, moves the carriage in the desired direction5. The focusing process is terminated when, during the next process of reading information, all unambiguous levels of samples are equal. The information in the code-to-voltage converter 12 is supplied periodically after passing every fourth line pulse of the CP (its active part) along the trailing edge and before the arrival of the next line pulse of the CP along its leading edge.

5 The 5 pulse shaper consists of two similar devices: a pulse modulator A, an emitter follower B, a delay line C, an amplifier D, a detector E, a pulse shaper and a matching circuit G (Fig. 2). Signals with a frequency of 10 MHz are supplied from the first output of the master oscillator 6 to the first inputs of the device modulators A (the first input of the 5 pulse shaper). On the second and third inputs of the block

5 5 (the second inputs of the pulse modulators A of the devices), video signals are received in analog form from the corresponding PTCs. Consider the processes in one of the devices of unit 5. The carrier frequency of 10 MHz lies in the transmission field of the delay line. The carrier frequency is fed to the first input of modulator A, and the video signal, previously converted into unipolar pulses, is fed to the second input. The AND logic composed of the OR elements of the logic logic is used as a modulator. At the output of the modulator there are pulses filled with a carrier frequency, the pulse duration depends on the size of the image currently crossed by the scan line. These pulses are transmitted through the emitter follower B to the input of the delay line C. This dann of the delay line introduces signal attenuation of the order of 14 dB; therefore, amplifier D is placed after it.

The amplified signal arrives at detector E due to the fact that when the signal passes through the elements of the delay channel, the pulse shape may be distorted, after the detector there is a pulse generator F, which is a transistor switch. Thus, two signals simultaneously arrive at the coincidence circuit G: a pulse delayed by 64 μs, i.e. information from the previous line, and the impulse is uncontrolled, i.e. information from the current line. Thus, from the output of the matching circuit (from the first and second outputs of block 5), the level-sampled video signals are fed to the third and fourth inputs, respectively, of control unit 8 (Fig. 1).

The master oscillator 6 consists of a series-connected generator A, a frequency divider B by four, a frequency divider C four, a frequency divider 125D, and a logical switch E connected in parallel to them (Fig. 3). The clock pulses with a frequency of 40 MHz from the output of generator A are fed to the input of the frequency divider B to the four and third inputs of the logical switch E. The clock pulses with a frequency of 10 MHz from the output of the divider B to the frequency of four are fed to the first output of the master oscillator 6, the input of the frequency divider C to four, as well as to the second input of the logical switch E. Sync pulses with a frequency of 2.5 MHz from the output of the divider C frequency of four are fed to the first input of the logical switch E. Sync pulses with a frequency of 20 KHz are fed to the fourth output of the master 6. The first input of the master oscillator 6 is connected to the fourth input of the logical switch E. The first and second outputs of which are connected to the second and third outputs of the master oscillator 6. Logical switch E connects its first and second outputs

respectively, to its first and second inputs when it arrives at its fourth input, the first input of the master oscillator 6, log level 1, and connects the second and third inputs, respectively, when it arrives at its fourth input, the log.io.

The control unit 8 consists of the following elements: an inverter A, the input of which is connected to the first input of the control unit 8, where these inputs are also connected to the first output of the control unit 8, a frequency divider B by four, whose input is connected to the first input of the control unit 8, and its output is connected to the fourth output of the control unit 8, the ring D-flip-flop C, the input of which is connected to the output of the inverter A, the ring D-flip-flop D, the input of which is connected to the second input of the control unit 8, the group output of which (second group of outputs) is connected to the second group output of the control unit 8, logical switch E, the first input of which is connected to the output of the frequency divider B by four, the second input of which is connected to the output of inverter A, the third group output of which is connected to the group output of the ring D-flip-flop C, group output which (the first group of outputs) is connected to the second group output of the control unit 8 and the third group output (second group of outputs) of the control unit 8, logical switch F, the first group input of which is connected to the first output of the ring D-flip-flop D, the second input of which is connected to the third input of the control unit 8, the group output of which, the third group of outputs, is also connected to the second group output of the control unit 8, the logical switch F, the first group input of which is connected to the group output of the ring D-flip-flop D, the second input of which is connected to the fourth input of the control unit 8, the group output of which, the first group of outputs, is connected to the third group output of the control unit 8 (Fig. 4).

Lowercase impulses CP duration through the first input of the control unit 8, they enter the input of inverter A (Fig. 5a), as well as the input of the frequency divider B by four. Inverted line pulses of the SR (Fig. 5, b) from the output of the inverter A go to the input of the ring D-flip-flop C which transfers the level of log.0 through its four channels sequentially for four clock cycles (Fig. 5, g) from the fupp the output, as well as the second input of the logical switch E, are connected. To the frequency divider B for four for the duration of the four horizontal pulses CP, the level is set to log 1 (Fig. 5 c), which is fed to the fourth output of the control unit 8, the first input of the logical switch E. Logical switch E, consisting s of four OR elements, each on one channel of its inputs the third group, adds the levels of each channel separately with the levels of the first and its second input. At the group output of the logical switch E through its four channels, we have clock pulses that come from the group output of the ring D-flip-flop C, which control the recording of each image line in the corresponding parts of the memory elements of the operational memory unit 9 and the memory unit 10 for the active part of the lowercase pulse CP with a duration of Tak., which are supplied to the second group output (first group of outputs) and to the third group output (second group of outputs) of the control unit 8 (Fig. 5, s-l). On the trailing edge of the active part of the fourth horizontal pulse CP at the output of the frequency divider B, the log level 0 is set to four, the read mode (Fig. 5, c), as a result of which the log 0 level is set at the group output of the logical switch E (Fig. 5, s) Through the second input of the control unit 8, the synchronous pulses with a frequency of 10 MHz are received at the input of the annular D-flip-flop D (Fig. 6, a). The operation of the ring D-flip-flop D is similar to the operation of the ring D-flip-flop C (Fig.6, bd). From the group output of the ring D-flip-flop D, the clock pulses are fed to the first group inputs of the logical switches F and G, which control the process of passing samples of image lines along one of the channels of the group outputs of the logical switches F and G, as well as to the second group output of the control unit 8 ( second group of outputs) (Fig.6, e-and). Through the third and fourth outputs of the control unit 8, the second inputs of the logical switches F and G, respectively, receive samples, respectively, from the slave PTC 1 and the leading PTC 4. From the group output of the logical switch F through four channels (the third group of outputs), the readings of the slave PTC 1 are also sent to second group output of control unit 8. From the group output of the logical switch G via four channels (the first group of outputs), the reports of the master PTC 4 are sent to the third group output of the control unit 8. At the time of reading, the ring D-flip-flop is controlled at a frequency of already 40 MHz. Change of position in space along

the depth at which the PTC lenses are focused causes a change in the address position of identical sixteen samples of four lines of image driven

PTC 1 relative to the central sixteen samples of four lines of images of the leading PTC 4 recorded in the memory unit 10, when they are compared by level in the comparison unit 11, in the process of reading them from

group output of the operational memory unit 9, as a result of which a seven-digit address word (address code) is generated at the group output of the code generator 13, which, after converting to voltage in the code converter 12, the voltage is applied to the processing and determines the direction and amount of movement carriages with transmitting television tubes. This is achieved

increasing the accuracy and resolution of focusing when several objects enter the PTC field of view.

Claims (1)

The claims An auto-focusing stereo television camera comprising first and second television cameras, a synchronizer, the output of which is connected to the synchronization inputs of the first and second television cameras, a focusing unit, the first and second outputs of which are connected to the focus control inputs of the first and second television cameras, and the unit comparison with in order to increase the focusing accuracy, a master oscillator, a pulse shaper, an address counter, a random-access memory block, a read-only memory block, a code shaper are introduced; . a code converter is a voltage and a control unit, wherein the first output of the master oscillator is connected to the first input of the pulse shaper, the second and third inputs of which are connected to the outputs of the first and second television cameras, and the first input of the code shaper, the second output is connected to the first input address counter, the first output of which is connected to the second input of the driver, the second output is connected to the first input of the random access memory block, and the third output is connected to the first input of the read-only memory block, the outputs of the random access memory block and the block the read-only memory is connected respectively to the first and second inputs of the comparison unit, the output of which is connected to the third input of the code generator, the output of which through the code-voltage converter is connected to the input of the phasing unit, the synchronizer output is connected to the first input of the control unit, the second input of which is connected with the third input of the clock, and the third and fourth inputs are connected respectively to the first and second outputs by pulse shapers, the first output of the control unit is connected to the second input of the addressable counter, the second output with the second input of the RAM block, the third with the second input of the read-only memory block, and the fourth output with the third input of the random access memory block, with the fourth input of the code generator, with the input of the master oscillator and with the third input address counter. g -, -, th g P burp. 2 Figs  5  i 1 / At Figure 3 Shchig4