RU1774346C - Forward and reverse cosine transformation device - Google Patents

Abstract

The invention relates to the construction of digital computing devices and discrete automation. The device calculates a sequence of DCT coefficients of length K from a known sequence of samples of length N in the encoder and the inverse transform in the decoder. The aim of the invention is to reduce hardware costs by reducing the amount of memory. The discrete cosine converter comprises a multiplier, a function adder, an output register, a function register, a counter and a memory unit, and an address generator. What's new is that an address generator has been introduced that allows you to access memory cells in a specific order. The volume of ROM is reduced by N / 4 times, the number of bits of the counter is reduced by 2 times. 3 ill. next to

Description

The invention relates to the construction of digital computing devices and discrete automation. It can be used in radio engineering and communication, in particular: in digital broadcasting and multifunctional communication systems, stereo audio tracking of television, recording, storage and reproduction of audio signals.

The aim of the invention is to reduce hardware costs by reducing N / 4 times the size of the memory block, where N is the sample size of the process implementation.

A block diagram of the device is shown in FIG. 1; in FIG. 2 is a schematic diagram of an address driver for forward and reverse conversion in a forward conversion; in FIG. 3 is a schematic diagram of a former during inverse transformation.

The device (Fig. 1) contains a multiplier 1, information input 2. memory block 3, adder 4 functions, register 5 functions, output register 6, output 7. counter 8. inputs 9 and 10 of the first and second clock sequences, reset input 11 , an address generator 12 for forward and reverse conversion.

Shaper 12 (Fig. 2) for direct conversion contains an adder 13, information input 14, output 15, adder 16, register 17.

Shaper 12 (Fig. 3) in the inverse transformation contains an adder

44 VI

Јь

with

ABOUT

18, register 19, information input 20 and output 21.

The device calculates a sequence of coefficients of discrete cosine transform (DCT) YK from the original sequence of samples Xn according to the expression:

YK VcKXn s- -k, (1)

N 0

where, 1,.,., K-1, K-th of the DCT coefficients, which represent the instantaneous spectrum of the processed signal;

, 1, ..., N-1, n-th PCM sample in the conversion interval;

K is the number of DCT coefficients;

N is the sample size (the number of samples in the conversion interval)

Ck - when

 , 2K-1,

and performs the inverse transform of the sequence of spectral transform coefficients YK restored in the decoder into blocks of frames according to the expression:

to - 1

v V v.. „(2п +1) ..,

2, SKUKSOZ „., K

K 0

2 N

(2)

Usually

, mG {4,5 ....}

At the input 9 of the device receives a clock sequence corresponding to the period of submission of samples at input 2. At the input 10 receives a clock sequence with a period of r K times greater than at input 9.

For each DCT coefficient, the multiplier 1 multiplies all M samples received at information input 2 by the corresponding cosine value recorded in the memory block 3. According to expression (1), when calculating all (N.K) products, it is sufficient to use only 4N different cosine values, i.e. cosine - the function is periodic, with a period of 2lg. In the memory block write l-- K 2N

4N values, and using the address generator 12, an appeal is made to the corresponding memory cell when calculating the corresponding product.

In the adder 4, the result of the current multiplication received at one input of the adder 4 functions from the output of the multiplier,

cos values

- (, 14N-1) - total

added to the result of the previous multiplication recorded in function register 5 in the previous clock cycle.

In output register 6 sequentially

values of all DCT coefficients are recorded. The output 7 of register 6 is the output of the device.

When calculating the Kth coefficient of DCT in the transition from one product

0 to the next, in each clock cycle, it is necessary to increase the address of the cell block of memory 3 from which the cosine value is read by 2K. When proceeding to the calculation of the K + 1th coefficient, it is necessary to read the cosines with a step of 2K + 2. Such a loop for accessing the desired cells is provided by the address generator 12.

Note that when implementing inverse DCT according to expression (2) is structural

0, the device diagram is identical to that of the DCT device shown in FIG. 1, which follows from a comparison of expressions (1) and (2).

The only difference is in the construction of the address generator 12, since when restoring the nth reference, see expression (2) - it is necessary, when switching from calculating the current product to calculating the subsequent one, increase the number of the cell from which the corresponding cosine value is read by 2n + 1.

The address generator, the circuit of which is shown in FIG. 2, provides access to the cells of the memory unit, the numbers of which are determined according to the expression

5 S-2K p,, 1, ..., N-1 when calculating the K-th coefficient of DCT for direct DCT.

The address generator, the circuit of which is shown in FIG. 3, provides access to the cells of the memory unit, the numbers of which are determined according to the expression (2n + 1) K,

KO, 1K-1

when calculating the n-th sample using DCT coefficients restored in the decoder.

5 Compared with the prototype, the memory size is reduced by N / 4 times and is 4N words, the number of bits of the counter 8 is reduced by 2 times.

Claims (3)

01. Device for forward and reverse cosine transform, comprising a counter, a memory unit, a multiplier, a function adder, a function register and an output register, wherein the information input of the device 5 is connected to the input of the first multiplier of the multiplier, the input of the second factor of which is connected to the output of the memory unit, the output of the multiplier is connected to the input of the first term function adder, the second term of which is connected to the output function register, the information input of which is connected to the output of the function adder and the information input of the output register, the output of which is connected to the output of the device, the input of the first clock sequence of which is connected to the synchronization inputs of the multiplier and the function register, the installation input to which is connected to the synchronization input of the output register and the input of the second clock sequence of the device, the reset input of which is connected to the input of the installation in the counter O, characterized in that, in order to reduce the apparatus costs due to the reduction in N / 4 times the size of the memory block, where N is the sample size of the process implementation, it contains an address generator for direct and inverse transformations, information inputs from the first to the mth bits of which are connected to the output - by the corresponding bits of the counter, where rrHogaN, the outputs from the first to (t + 2) -th bits of the address generator for the forward and reverse conversions are connected to the address inputs of the corresponding bits of the memory block, synchronization inputs and settings of the address generator for direct and reverse transformations are connected respectively to the inputs of the first and second clock sequences of the device, the input of the second clock sequence of which is connected to the synchronization input of the counter. 2. The device according to claim 1, characterized in that the address generator for the forward and reverse conversions in the forward conversion mode contains two adders and a register, the information inputs from the first to the mth bits of the former being connected to the information inputs - Dams of the corresponding bits of the first term of the first and second adders, the outputs from the first to (t + 2) -th bits of the first adder are connected to the outputs of the corresponding bits, the synchronization input of which is connected to the register synchronization input, the outputs from the first to (t + 1) -th bits which are connected to information inputs, respectively, from the second to (t + 2) th bits of the second term of the first adder and information inputs, respectively, from the first to (ggi-1} th bits of the second term of the second adder, the outputs of which bits are connected to informationstrokes corresponding register bit rows, a set input of which is connected to the input for setting the shaper, a logic-zero input connected to the input of the first discharge of the second term of the first adder. 3. The device according to claim 1, characterized in that the address generator for the forward and reverse transforms in the inverse transform mode comprises an adder and a register, the outputs from the first to (t + 2) th bits of which are connected to the outputs of the corresponding bits shaper and information inputs of the corresponding bits of the second term of the adder, information inputs from the second to (t + 1) -th bits of the first term of which are connected to the inputs respectively from the first to rn-th bits of the shaper, synchronization inputs and set whose kits are connected to the inputs of synchronization and installation in О of the register, the information inputs of the bits of which are connected to the outputs of the corresponding bits of the adder, the information input of the first bit of the first term of which is connected to the input of the logical unit of the generator. B Figure 2