RU17631U1 - MONO PULSE RADAR SYSTEM - Google Patents

Abstract

A monopulse radar system containing a pathogen, a phase manipulator and a power amplifier connected in series through an antenna switch to an antenna that is kinematically connected to the antenna drive, and a sum-difference converter connected to the third arm of the antenna switch in series with the corresponding inputs and outputs of the sum and difference signals , a high-frequency amplifier, a mixer and an intermediate-frequency amplifier, to the corresponding outputs of which о the block of quadrature phase detectors of the total signal and the block of quadrature phase detectors of the difference signal are connected, the sine and cosine outputs of which are connected through the amplitude quantizer to the corresponding information inputs of the digital matched filter, as well as a pulse modulator and code generator connected to the output of the synchronizing trigger pulses, the combining unit quadrature, range discriminator and code converter in the time interval, while the digital code inputs are consistent of the filter and phase manipulator are connected to the output of the code generator, the outputs of the local oscillator and intermediate frequencies of the exciter are connected respectively to the heterodyne input of the mixer and the reference inputs of the blocks of quadrature phase detectors of the total and difference signals, and the output of the pulse modulator is connected to the second input of the power amplifier, characterized in that the first and second blocks of comparators, the first and second automatic threshold regulators, the first and second multi-digit matched filters, the block about

Description

Monopulse radar system

The utility model relates to radar systems (radar), mainly to radar with complex, in particular, phase-shifted signals used on mobile carriers and designed to detect and track in single-pulse signals from targets in the presence of reflections from local objects.

In currently used monopulse radars designed to detect and track targets, the received high-frequency signals after sum-difference conversion are fed to the mixers of the sum and difference channels and then to the intermediate-frequency amplifiers, from the outputs of which the signals are fed to an amplitude detector in the sum channel and to phase detector in the difference channel. As a result of phase detection, an angular mismatch signal is generated, which is used for angular tracking 1, p. 22, fig. 1.9, 2, p. 20, fig. 15. The signal of the total channel is fed to a temporary discriminator, in which a signal is generated for tracking along the range.

The disadvantage of these devices is the low noise immunity in relation to active and passive interference, and, accordingly, low tracking accuracy. Active interference leads to the detection of false targets and the masking of real targets. Passive interference in the form of reflections from local objects also mask a useful signal due to the impossibility of realizing high angle resolution at long ranges with limited sizes of radars mounted on moving carriers, which therefore have a wide antenna radiation pattern.

A device 3 is known which uses complex phase-manipulated (hereinafter referred to as FM) signals for operation and contains digital compression filters of binary quantized signals coming from the outputs of phase detectors in two quadra GO IS 13/44

tours in the total and differential channels. The output signals of the same quadrature of the total and difference channels are fed to the multipliers to multiply the quadrature of the same name, and the resulting products are fed to the adder to exclude the influence of a random initial phase. The output signal of the adder is quantized into three levels, which determine the output signal of the angular mismatch, along which target tracking can be conducted.

The noise immunity of this device with respect to active impulse noise is slightly increased compared to the radars considered earlier due to the use of a complex FM signal.

The disadvantage of this device is its low noise immunity with respect to passive interference, for example, in the form of reflections from local objects, which is due to the low angular resolution of radars on moving objects, which have significant weight and size limitations. As a result, the interfering signal passes through the compression filter and reduces the accuracy of the angular tracking of the target.

Known radar 4, which is the closest in technical essence to the proposed device and adopted as a prototype. The radar contains a series-connected code generator, phase manipulator, amplification amplifier, antenna switch and antenna, series-differential converter, high-frequency amplifier, mixer, intermediate-frequency amplifier, as well as an exciter, pulse modulator, antenna drive, blocks of phase and total detectors difference signals, amplitude quantizers, digitally matched filters of binary quantized signals, quadrature combining unit, primary data processing device deformations of, vklyuchayushee discriminator range and code converter during the time interval in the composition of the rangefinder, the angle discriminator, an integrator, the intensity measurement unit, and second information processing apparatus.

Due to the use of complex FM signals and digital matched filters, this radar has good noise immunity with respect to active interference.

the mutual influence of closely spaced objects and the possible suppression of the signal from the target by interfering signals when it is detected by reducing the resolution in range. The low angular resolution of the antennas of such radars mounted on mobile carriers leads to the ingress of a powerful interfering signal into the receiving channel of the radar, which passes to the output of digital matched filters and reduces the noise immunity of the radar and the accuracy of target tracking using the angle discriminator and integrator. In particular, when both the target and the interfering objects fall into the antenna beam, disruptions to the target tracking and false radar transitions from tracking the target to tracking the interference can occur. At the same time, tracking accuracy is reduced.

The technical task of the utility model is to increase the resolution of target detection, accuracy and noise immunity of target tracking with respect to active and passive interference when installing a radar on a mobile carrier.

To achieve the claimed technical result, it is proposed to use adaptive multi-level quantization of the signal with adjustment of quantization thresholds when tracking the target for tracking, to measure the Doppler component of the signal by narrow-band Doppler filtering and, when tracking the target, to close using narrow-band frequency filters tracking contours along the Doppler component range and range in the total channel, and the output quadrature components of the narrowband target signal in the difference channel should be normalized to the same quadrature components in the total channel and the obtained estimate of the angular mismatch to be used for the target's angular tracking contour.

The essence of the utility model consists in the fact that in a monopulse radar system containing a pathogen, a phase manipulator and a power amplifier connected through an antenna switch to an antenna that is kinematically connected to the antenna drive, a sum-difference converter is connected in series with the corresponding inputs and outputs of the total and difference signals connected to the third arm of the antenna switch, high-frequency amplifier, mixer and gap amplifier full-time frequency, to the corresponding outputs of which a block of quadrature phase detectors are connected

a sum signal and a block of quadrature phase detectors of a difference signal, the sine and cosine outputs of which are connected through an amplitude quantizer to the corresponding information inputs of a digital matched filter, as well as a pulse modulator and code generator connected to the output of the synchronizing triggering pulses, a quadrature combining unit, a range discriminator, and a converter code in the time interval, while the code inputs of the digital matched filter and phase manipulator are connected to Ode to the code generator, the outputs of the local oscillator and intermediate frequencies of the pathogen are connected respectively to the heterodyne input of the mixer and the reference inputs of the blocks of quadrature phase detectors of the sum and difference signals, and the output of the pulse modulator is connected to the second input of the power amplifier, the first and second blocks of comparators, the first and second automatic threshold regulators, first and second multi-digit matched filters, target detection and selection unit, antenna angle sensor, kinematically connected to the antenna drive, the control input of which is connected to the output of the angle switch, angle register, range register, target acquisition unit, first, second, third, fourth, fifth and sixth Doppler frequency filters, first second and third Doppler frequency generators, first and second subtractors, register, first, second, third and fourth adders, code bus, valve block, frequency discriminator, first and second code dividers, first and second delay elements and range counter, zeroing the input of which is combined from the input we start the detection unit and select the target and the code converter in a time interval and is connected to the output of the triggering pulses of the synchronizer, the output of the synchronizing pulses of which is connected to the inputs of the siphonization of the first and second automatic threshold controllers, the detection and target selection unit, the target capture unit and the range counter, output which is connected to the first input of the target detection and selection unit, the second input of which is connected to the output of the quadrature combining unit, the third to the output of the angular position sensor a tones, the first and second outputs are connected to the recording inputs of the angle register and range register, the third output is connected to the first input of the angle switch, and the fourth output is connected to the control inputs of the angle switch, target acquisition unit, range register and angle register, the output of which is connected to the first input of the first subtractor, the second input of which is connected to the output of the valve block, and the output from

the second input of the angle switch, the output of the range register is connected to the nerve input of the first adder, the second input of which is connected to the output of the range discriminator, and the output is connected to the information input of the code converter in the time interval, the code inputs of the first and second multi-bit matched filters are connected to the output of the code generator, whose inputs, combined with the inputs of the first and second automatic threshold regulators, respectively, are connected to the outputs of the first and second blocks of the comparators, respectively the input inputs of which are connected respectively to the sine and cosine outputs of the block of quadrature phase detectors of the total signal, and the second inputs are connected to the outputs of the first and second automatic threshold regulators, respectively, the outputs of the first and second multi-digit matched filters are connected to the sine and cosine information inputs of the quadrature combining unit, first to fifth, sine and cosine outputs of the first and second generators the Doppler frequency are connected to the same frequency inputs of the fourth and fifth Doppler filters, and the sine and cosine outputs of the third Doppler generator are connected to the same frequency inputs of the first, second, third and sixth Doppler filters, the sine and cosine information inputs of the sixth Doppler filter are connected to the corresponding outputs of the digital matched filter, the output of the code converter in the time interval is connected to the synchronization input the first filter of the Doppler frequency and the input of the first delay element, the output of which is connected to the synchronization inputs of the second, fourth, fifth and sixth filters of the Doppler frequency, the start input of the target capture unit and the input of the second delay element, the output of which is connected to the synchronization input of the third Doppler frequency filter, the sine outputs of the second and sixth Doppler filters are connected respectively to the second and first inputs of the first code divider, and their cosine outputs are connected to the second and first the input of the second code divider, the modular output of the second Doppler filter is connected to the second inputs of the range discriminator and the frequency discriminator, the modular outputs of the first and third filters of the Doppler frequency are connected respectively to the first and third inputs of the range discriminator, the modular outputs of the fourth and fifth filters of Doppler frequency are connected respectively to the first and third inputs of the frequency discriminator, the output of which is connected to the second input of the second adder, the first the stroke of which is connected to the register output, and the output is connected to the code input of the third Doppler frequency generator and to the first inputs of the second subtractor and third adder, the second inputs of which are connected to the code bus, the outputs of the second subtractor and third adder are connected to the code inputs of the first and second Doppler generators frequencies, respectively, the outputs of the first and second code dividers are connected to the corresponding inputs of the fourth adder, the output of which is connected to the input of the valve block, the control input is cerned is combined with the input register and is connected to the synchronizing control output of target acquisition unit, the information output of which is connected to the input of a register entry.

The essence of the utility model is illustrated by a further description and drawings, which show:

FIG. 1 is a structural diagram of a monopulse radar;

FIG. 2 is a block diagram of a block of comparators;

FIG. 3 is a block diagram of an automatic threshold regulator;

FIG. 4 is a block diagram of a multi-bit matched filter;

FIG. 5 is a block diagram of a review and target selection unit;

FIG. 6 is a block diagram of a target capture unit;

Fig.7 is a structural diagram of a Doppler frequency generator;

FIG. 8 is a block diagram of a Doppler frequency filter.

In FIG. 1 structural scheme monopulse radar adopted the following notation:

1 - pathogen,

2-phase manipulator.

3- power amplifier,

4-antenna switch,

5- antenna

6 - synchronizer,

7- code generator,

6) 0/5 / - 6 - in d 10 - a high-frequency amplifier, 11 - a mixer, 12 - an intermediate frequency amplifier, 13 - a block of quadrature phase detectors of the total signal, 14 - a block of quadrature phase detectors of the difference signal Hz 15 - amplitude quantizer, 16 is a digital matched filter, 17.18 is the first and second blocks of comparators, respectively, 19, 20 are the first and second automatic threshold regulators (ARP), respectively, 21, 22 are the first and second multi-digit matched filters (MSF), respectively, 23- block combining quadratures, 24- block detection and selection spruce (BOVTS), 25- angle switch, 26- antenna drive, 27- antenna angle sensor, 28- angle register, 29- first subtracter, 30- range register, 31- first adder, 32- code converter in a time interval, 33- target capture unit (BHX), 34- register, 35, 36, 37, 38, 39, 40 - first, second, third, fourth, fifth, fifth, sixth filters of the Eros frequency (FFD), respectively, 41, 42, 43 - the first, second, third Doppler frequency generators (DCH), specifically, 44,45,46 - the second, third, fourth adder, respectively, 47 - the second subtractor,

49- valve block,

50 - range discriminator, made in the form of a block comparing the signals of half-gates with control by the signal of the central gate.

51-frequency discriminator, made in the form of a unit for comparing the signals of two side frequency filters with control by the signal of the central frequency filter,

52, 53 - the first and second code dividers, respectively,

54, 55 - the first and second delay element, respectively,

56 - range counter.

According to the block diagram of FIG. 1, in the proposed monopulse radar, pathogen I, a phase manipulator 2 and a power amplifier 3 are connected in series, the second input of which is connected to the output of the pulse modulator 8, and the output through the antenna switch 4 is connected to the antenna 5, which is kinematically connected to the antenna drive 26, connected in series the inputs of the outputs of the total and differential signals, the sum-differential converter 9 connected to the third arm of the antenna switch 4, the high-frequency amplifier 10, the mixer 11 and amplify s 12 of the intermediate frequency to the respective outputs of which are connected a block 13 for quadrature phase detectors and the sum signal unit 14 quadrature phase detector difference signal. The sine (in Fig. 1 -S) and cosine (in Fig. 1 -C) outputs of block 14 are connected to the corresponding information inputs of the digital matched filter 16 through the amplitude quantizer 15.

The inputs of the pulse modulator 8 and the code generator 7 are connected to the output of the triggering pulses of the synchronizer 6. The code inputs of the digital matched filter 16, the phase manipulator 2, the first and second MSF 21 and 22 are connected to the output of the code generator 7. The output of the local oscillator frequency of the pathogen 1 is connected to the heterodyne input of the mixer 11, and its output of the intermediate (reference) frequency is connected to the reference inputs of blocks 13 and 14 of quadrature phase detectors of the total and difference signals.

The zeroing input of the range counter 56 is combined with the start inputs of the target detection and selection unit 24 and the code converter 32 in a time interval and is connected to the output of the trigger pulses of the synchronizer 6, the output of the synchronizing pulses of which is connected to the synchronization inputs of the first and second automatic threshold regulators 19, 20, of the block 24 detection and target selection, block 33 of the target acquisition and counter 56 range, the output of which is connected to the first input of block 24 detection and target selection.

The second input of the target detection and selection unit 24 is connected to the output of the quadrature combining unit 23, the third to the output of the antenna angular position sensor 27. The first and second outputs of the BOVC 24 are connected to the recording inputs of the angle register 28 and range register 30, the third output is connected to the first input of the angle switch 25, and the fourth output is to the control inputs of the angle switch 25, target acquisition unit 33, range register 30 and register 28 angle, the output of which is connected to the first input of the first subtractor 29, the second input of which is connected to the output of the valve block 49, and the output to the second input of the angle switch 25.

The output of the range register 30 is connected to the first input of the first adder 31, the second input of which is connected to the output of the range discriminator 50, and the output is connected to the information input of the code converter 32 in a time interval.

The code inputs of the first and second multi-bit matched filters 21 and 22 are connected to the output of the code generator 7, the inputs of which, combined with the inputs of the first and second automatic threshold regulators 19, 20, respectively, are connected to the outputs of the first and second blocks 17 and 18 of the comparators. The first inputs of the comparator blocks 17 and 18 are connected respectively to the sine and cosine outputs (sine and cosine quadrature components of the total video signal) of block 13 quadrature phase detectors of the total signal. The second inputs of the comparators 17 and 18 are connected to the outputs of the first and second automatic threshold regulators 19 and 20, respectively.

The outputs of the first and second multi-bit matched filters 21 and 22 are connected respectively to the sine and cosine (quadrature) information inputs (in Fig. 1 - From and Is) of the block 23 combining quadrature block 33 capture target and filters 35, 36, 37, 38 and 39 Doppler frequencies. The sine and cosine signals of the first Doppler frequency generator 41 are connected to the sine and cosine

frequency (in Fig. 1 - 4s and Cs) of the fourth Doppler frequency filter 38, the sine and cosine outputs of the second Doppler frequency generator 42 are connected to the corresponding frequency inputs of the Doppler frequency filter 39, and the sine and cosine outputs of the third Doppler frequency generator 43 to the corresponding frequency filter inputs 35, 36, 37 and 40 Doppler frequency. The sine and cosine information inputs of the Doppler frequency filter 40 are connected to the corresponding outputs of the digital matched filter 16.

The output of the code converter 32 in a time interval is connected to the synchronization input of the Doppler frequency filter 35 and the input of the first delay element 54, the output of which is connected to the synchronization inputs of the Doppler frequency filters 36, 38, 39, 40, the start input of the target capture unit 33 and the input of the second element 55 delays. The output of the delay element 55 is connected to the synchronization input of the Doppler frequency filter 37.

The sine and cosine outputs of the Doppler frequency filter 40 are connected to the first inputs of the first and second code dividers 52 and 53, respectively, the second inputs of which are connected to the sine and cosine outputs of the Doppler frequency filter 36, respectively. The modular output of the Doppler frequency filter 36 is connected to the second inputs (center tracking gate) of the range discriminator 50 and the frequency discriminator 51. The first and third inputs (range tracking half-gates) of the range discriminator 50 are connected to the modular outputs of the Doppler frequency filters 35 and 37, respectively. The modular outputs of the filters 38 and 39 of the Doppler frequency are connected respectively to the first and third inputs (side frequency half-gates) of the frequency discriminator 51.

The output of the frequency discriminator 51 is connected to the second input of the second adder 44, the first input of which is connected to the output of the register 34, and the output is connected to the code input of the Doppler frequency generator 43 and to the first inputs of the second subtractor 47 and the third adder 45, the second inputs of which are connected to the code bus 48. The outputs of the second subtractor 47 and the third adder 45 are connected to the code inputs of the first and second Doppler frequency generators 41 and 42, respectively. The outputs of the first and second code dividers 52 and 53 are connected to the corresponding inputs of the fourth adder 46. The output of the adder 46 is connected to the input of the block

49 gates, the control input of which is combined with the synchronization input of the register 34 and connected to the control output of the target capture unit 33, the information output of which is connected to the input of the register register 34.

The causative agent 1, phase manipulator 2, power amplifier 3, pulse modulator 8, code generator 7, forming the transmitting part of the radar, are designed to generate a pulsed FM probe signal and can be performed according to known schemes given in 5.

The radar receiving path as part of a sum-difference transducer 9, a high-frequency amplifier 10, a mixer 11, an intermediate-frequency amplifier 12, and quadrature phase detector units 13, 14 is designed for the sum-difference conversion of the received echo signal and its sequential processing in the sum and difference channels. Examples of the implementation of the corresponding blocks of the receiving path are known and are given, for example, in 3 and 5.

The digital matched filter 16 is designed for matched filtering (compression) of the sine and cosine quadrature components of the binary quantized differential video signal and can be implemented similarly to the digital matched filter of the prototype according to the circuit shown in description 4, FIG. 2.

The comparator blocks 17 and 18 are designed to generate a two-phase digital code of the compressed quadrature signal of the total channel corresponding to the current range quantum and are executed each according to the circuit shown in FIG. 2.

In FIG. 2 is indicated:

57, 58 - digital-to-analog converters (DAC),

59.60, 61 - comparators,

62- zero bus (NS),

63 - element of equivalence, 64, 65 - inverters,

66, 67 - valves,

68 - element ШШ,

69 - the negative threshold voltage (OS), made in the form of a conductor connected to the negative pole of the power source,

Qj) ./3/11 The first inputs of the comparator unit 17 (18) form the signal inputs of the comparators 59, 60, 61, the threshold inputs of which are connected respectively to the NS 62, the output of the DAC 57 and the output of the DAC 58. The first inputs of the DAC 57 and 58 form the second input block 17 (18) of the comparators. The second input of the DAC 57 is connected to the OR 69, and the second input of the DAC 58 is connected to the PN 70. The outputs of the comparators 60 and 61 are connected to the corresponding inputs of the equivalence element 63, the output of which is directly connected to the first input of the valve 67 and through the inverter 64 to the first input of the valve 66 The outputs of the gate 66 and 67 are connected to the inputs of the OR element 68, the output of which forms the low-order output of the two-bit code of the block 17 (18) of the comparators, the high-level output of which forms the output of the comparator 59, to which the second input of the valve 67 and h is also directly connected Through inverter 65 - the second input of the valve 66.

Automatic threshold regulators 19 and 20 are each made in accordance with the circuit shown in FIG. 3, on which is indicated:

71, 72 - elements of equivalence.

73 - delay element

74-valve

75 inverter

76- integrator.

The information input of the ARP 19 (20) is formed by the inputs of the lower and upper bits of the two-bit code of the equivalence element 71, the output of which is directly connected to the first input of the equivalence element 72, through the delay element 73 - with its second input, and also directly connected to the input of the least significant bits of the integrator 76 , and through inverter 75 - with its high-order input. The output of the equivalence element 72 is connected to the first input of the valve 74, the second input of which serves as the synchronization input of the ATM 26 (20). The output of the valve 74 is connected to the sync input of the integrator 76, the output of which serves as the output of the ARP 19 (20).

The multi-channel matched filters 21 and 22 are made according to the circuit shown in FIG. 4, where indicated:

77, 78 - elementary quadrature channels (ECC), each of which consists of a series-connected shift register, random access memory device codes, multi-input adder and two-input adder.

79 is a block shear,

80- adder.

The inputs of the upper and lower digits of the two-bit code, forming the input of MSF 21 (22), are connected to the first inputs of E1SK 77 and EYUS 78, respectively, the second inputs of which are connected to the code input of MSF 21 (22). The output of the ECC 77 through the block 79 shift is connected to the first input of the adder 80, and the output of the ECC 78 is directly connected to its second input. The output of adder 80 is the output of MSF 21 (22).

Block 23 combining quadratures is designed to combine the sine and cosine quadrature components of the information signal according to the rule "the sum of squares and can be performed similarly to the block combining quadratures of the prototype 4, Fig. 4, p. 37.

The target detection and selection unit 24 is made according to the circuit shown in FIG. 5.

In FIG. 5 adopted the following notation:

81-threshold block

82-shift register

83 - random access memory (RAM),

84- adder single bits,

85- threshold block

86- RAM availability of the target,

87- ram target intensity,

88- RAM of the initial angle of the target, 89, 90 - comparison blocks,

91- intensity memory unit,

92- range memory unit,

93- corner memory block,

94 half-adder,

95 counter

96 - final code decoder, 97, 98 - delay elements,

The first input of the BOVC 24 is connected to the recording input of the range memory block 92 and the address inputs of the target availability RAM 86, the target intensity RAM 87, the target initial angle RAM 88 and the RAM 83. The outputs of the RAM 83 are bitwise connected to the inputs of the bits of the shift register 82, starting from the second, and the input of the first discharge of the shift register 82 is connected to the output of the threshold unit 81, the input of which forms the second input of the BOVC 24.

The first input of the half-adder 94 and the write input of RAM 88 of the initial angle of the target are connected to the third input of the BOVC 24, the start input of the BOVC 24 is connected to the input of the counter 95, and the synchronization input is connected to the input of the delay element 97 and the synchronization input of the shift register 82, the output of which is connected to the input write RAM 83 and the input of the adder 84 single bits.

The output of the adder 84 is connected to the input of the threshold unit 85, the first input of the comparison unit 89 and the recording input of the RAM 87 of the target intensity, the second input of the comparison unit 89, the first input of the comparison unit 90 and the recording input of the intensity memory unit 91, the output of which is connected to the second input of block 90 comparison.

The output of the delay element 97 is connected to the synchronization inputs of the And 99 and 100 elements and the input of the delay element 98, the output of which is connected to the synchronization inputs of the RAM 83, the RAM 86 and the And 101 element, the output of which is connected to the synchronization input of the RAM 87. The first input of the And 101 element is connected with the output of the comparison unit 89, and the second with the output of the threshold unit 85, which is also connected to the write input of the RAM 86, with the first input of the And 99 element and through the inverter 102 with the second input of the And 100 element.

The output of the RAM 86 is directly connected to the first input of the AND element 100 and through the inverter 103 to the second input of the And 99 element, the output of which is connected to the synchronization input of the RAM 88, the output of which is connected to the second input of the half-adder 94 connected to the recording input of the angle memory unit 93, the output of which forms the first output of BOVC 24.

The third input of the And 100 element is connected to the output of the comparison unit 90, and the output is connected to the synchronization inputs of the intensity memory unit 91, the angle memory unit 93 and the range memory unit 92, the output of which forms the second output of the BOVC 24.

to the end of the review) BOVC 24.

The target capture unit 33 is made according to the circuit shown in FIG. 6 on which

indicated by:

104 - counter

105, ..., 105s are the FDF of the target capture unit from the first to the Nth, respectively,

106i, ..., 106N - GDCH block capture target from the first to the Nth, respectively,

107i, ..., 107N - code buses of the frequency (FC) of the target capture unit from the first to the Nth,

respectively, made in the form of a set of contacts (conductors) connected to

sources of zero and unit potential, 108, 109, software valves,

111 - final code decoder,

112-switch

113-register

114- comparison unit,

115- frequency register,

116 counter

117- final code decoder,

118- trigger.

The sine and cosine information inputs of the BHX 33 are connected respectively to the sine and cosine information inputs (From, Is) of the PDF 105i, ..., 105n, the frequency inputs 4s, and Hs of which are connected to the sine and cosine outputs of the HDF 106i, ..., 106n, the code inputs of which are connected to the frequency converter 107i, ..., 107y. The synchronization inputs of the PDF 105i, -, 105s are combined with the counting input of the counter 104 and are connected to the output of the software gate, the control input of which is connected to the inverse output of the trigger 118, and the signal input of the software gate forms the start input of the BZX 33. The control input of the BZX 33 is connected to the zeroing input counter 104, and the synchronization input to the signal input of the valve 109.

The countercode 104 is connected to the input of the final code decoder 111, the output of which is connected to the signal input of the trigger 118, the reset input of which is connected to the output of the final code decoder 117, which also serves as the control output of the BZX 33.

j5 00- / 5/5

The direct output of the trigger 118 is connected to the control input of the valve 109, the output of which is connected to the counting input of the counter 116 and through the gate 108 to the synchronization inputs of the register FROM and the frequency register 115, the output of which forms the information output BZX 33. The output of the counter 116 is connected to the input of the final decoder 117 code, the input of the recording of the frequency register 115 and the control input of the switch 112, the inputs of which from the first to the Nth are connected to the modular outputs of the PDF 105, ..., 105m, respectively, and the output of the switch 112 is connected to the recording input of the register 113 and the first Valid comparisons of block 114, the second input of which is connected to the output of the register 113, and the output - to the control input of the gate 108.

The Doppler frequency generators 41, 42, 43, 106i, ..., 106y are implemented in accordance with the circuit shown in FIG. 7, on which is indicated:

119 - master oscillator

120- counter

121 - read only memory (ROM) of the sines,

122- ROM of cosines.

The code input of the HDC 41 (42, 43, 106i, ..., 106n) is connected to the first inputs of the ROM 121 sines and ROM 122 of the cosines, the outputs of which form respectively the sine and cosine outputs of the HDC, and the second inputs are connected to the output of the counter 120, the input of which connected to the output of the master oscillator 119.

Filters 35, 36, 37, 38, 39, 40, 105i, ..., 105s of Doppler frequencies are made in accordance with the circuit shown in FIG. 8, on which is indicated:

123, 124 - multipliers,

125, 126 - integrators of the moving interval,

127 - block combining quadratures.

The sine and cosine frequency inputs ($ 4 and Hs) of the pass filter are connected to the second input of the multiplier 123 and the second input of the multiplier 124, respectively, the first inputs of which form the sine and cosine information inputs (From and Is) of the pass filter. The outputs of the multipliers 123 and 124 are connected to the inputs of the integrators 125 and 126 of the moving interval, respectively, the outputs of which form the sine and cosine (quadrature) outputs of the pass filter. The outputs of the integrators 125 and 126 are also connected to the inputs of the block 127 combining quadrature, forming a modular (M) output of the filter. The synchronization input of the pass filter is connected to the synchronization inputs of integrators 125 and 126

SjO ") 0/2 / S

sliding interval.

The device operates as follows.

The pathogen 1 generates a carrier frequency signal supplied to the phase manipulator 2, a local oscillation frequency signal supplied to the mixer 11, and an intermediate frequency reference signal supplied to the reference inputs of the blocks 13 and 14 of the quadrature phase detectors.

The synchronizer 6 generates triggering pulses with a sounding frequency and synchronizing pulses with a quantization frequency of the received signal. The trigger pulse is fed to the input of the code generator 7 and to the input of the pulse modulator 8. In this case, the code generator 7 generates a pseudo-random binary code supplied to the phase manipulator 2, which changes the phase of the carrier frequency of the pathogen 1 in accordance with the incoming code. The phase-manipulated signal obtained in this case is fed to the input of the power amplifier 3, the second input of which receives a trigger pulse from the pulse modulator 8. The output phase-manipulated pulse of the power amplifier 3 through the antenna switch 4 enters the antenna 5 and is emitted into space.

The signal received by antenna 5 through the antenna switch 4 is fed to the sum-difference converter 9, the outputs of which are formed by the sum and difference signals supplied to the corresponding inputs of the high-frequency amplifier 10, from the output of which the amplified sum and difference signals are fed to the mixer 11, where they are shifted with the local oscillator frequency signal of the pathogen 1. At the same time, at the output of the mixer 11, the total and difference signals of the intermediate frequency are formed, which are fed to the amplifier 12 th frequency, and from its outputs the total and difference signals are fed to blocks 13 and 14 of quadrature phase detectors of the total and difference signals, respectively. Pa reference inputs of blocks 13 and 14 receives the reference signal of the pathogen 1, which in each block is shifted with the signal of the intermediate frequency amplifier (IFA) directly and with a phase shift of 90 °, as a result of which two quadrature are formed at the output of each block 13 (14) signal (sine and cosine) at the video frequency. These quadrature components of the difference video signal from block 14 of the quadrature phase detectors are fed to the amplitude quantizer 15, which performs their binary quantization with a zero threshold. Binary quantized signals with

the output of the amplitude quantizer 15 is supplied to the quadrature information inputs of a digital matched filter 16, the code input of which in each sounding interval receives and stores the phase-shift code from the code generator 7.

In the digital matched filter 16, the received signal is compressed by calculating the correlation function between the received signal and the phase-shift keying code of the probe signal. At the same time, two compressed quadrature signals (sine and cosine) corresponding to the current range quantum are generated at two quadrature outputs of the filter 16 at each current time instant.

The sine and cosine quadrature components of the total video signal from the output of block 13 of the quadrature phase detectors of the total signal are received respectively at the input of the block 17 of the comparators and at the input of the block 18 of the comparators, which form two-bit codes arriving at the multi-bit matched filters 21 and 22, respectively.

Moreover, in each of the comparator blocks 17 (18) (see Fig. 2), the input signal from the block 13 of the quadrature phase detectors is supplied to the comparators 59, 60, and 61, where it is compared with threshold signals supplied to the comparator 59 from the busbar 62 forming a zero signal, and to the comparators 60 and 61, respectively, from DAC 57 and DAC 58, forming negative and positive thresholds symmetrical with respect to zero, for which a digital code from automatic controller 19 (20) is supplied to their first inputs, and negative respectively and put the total supply voltage from the negative threshold voltage bus 69 and the positive threshold voltage bus 70, which are equal in magnitude and opposite in sign.

The binary signals from the outputs of the comparators 60 and 61 are fed to the equivalence element 63, the output signal of which is supplied to the valve 67 and through the inverter 64 to the valve 66, the second inputs of which respectively receive the output signal of the comparator 59 directly and through the inverter 65. The output signals of the valves 66 and 67 are supplied to the OR element 68, the output signal of which forms the low-order bit of the output two-bit code of the block 17 (18) of the comparators, and the output of the comparator 59 forms the high-order bit of the specified two-bit code.

By analyzing various combinations of the signal from the block 13 of the phase detectors and the threshold signals supplied to the comparators 59, 60, 61, we can verify that the output signal of the block 17 (18) of the comparators sequentially takes values from O to 3 in binary code for the following values of the signal block 13 phase detectors:

below the negative threshold - ... Oh

negative threshold, but below zero - ... 1

above the zero threshold, but below the positive - ... 2

above a positive threshold - ... 3.

The resulting binary code from the output of block 17 of the comparators goes to the inputs of the multi-bit matched filter 21 and the automatic threshold controller 19, and from the output of block 18 kbparators to the inputs of the multi-bit matched filter 22 and the automatic threshold controller 20.

In the automatic threshold regulator 19 (20) (see Fig. 3), the signal from the output of the comparator unit 17 (18) is supplied to the inputs of the equivalence element 71, the output signal of which is supplied to the delay element 73, where it is delayed by a single phase manipulation discrete probe signal . Tekup; its signal value of the equivalence element 71 and delayed (from the output of the element 73) are supplied to the inputs of the equivalence element 72. In this case, the output signal of the equivalence element 71 takes a zero value in the case when the input signal of the comparator unit 17 (18) lies between the upper and lower threshold voltages, and takes a unit value in the opposite case, and the output signal of the equivalence element 72 takes a unit value in that p.11, when the input signal of the block 17 (18) of comparators several times in a row in adjacent time samples takes values inside a specified threshold range or several times in a row takes values outside horn range. In these cases, the output signal of the equivalence element 72 opens the valve 74 and passes the sync pulses from the synchronizer 6, coming through the synchronization input of the automatic threshold regulator 19 (20), to the input of the integrator 76, changing its output value by the value of the elementary increment.

The value of the elementary increment of the integrator 76 is formed by the output signal of the equivalence element 71, which is transmitted to the lower bits of the input of the integrator 76 and through the inverter 75 to the higher bits of the input of the integrator 76, including the sign bit.

In this case, the output code of the integrator 76 is changed so that the output signal of the block 13 of the quadrature phase detectors with equal probability falls into the threshold range of the blocks 17 and 18 of the comparators and outside it.

The output signals of the comparator units 17 and 18 are also sent to the MSF 21 and 22, respectively (see Fig. 4), the code inputs of which (the second inputs of the ECC 77 and ECC 78) are supplied with a pseudo-random code of the probe signal from the code generator 7. In ISF 21 (22), the most significant bit of the input signal is supplied to the elementary quadrature channel 77, and the least to the elementary quadrature channel 78, which are similar to the quadrature channels of the digital matched filter 16. The output signal of the ECC 77 through the shift unit 79, doubling the output signal, is transmitted to the first input of the adder 80, and the output signal of the ECC 78 to its second input. In this case, the output of the adder 80, which is the output of the MSF 21 (22), generates a compressed signal of the corresponding quadrature component of the total video signal from the output of the block 13 of the quadrature phase detectors.

The output signals of the multi-bit matched filters 21 p 22 are supplied to the quadrature combining unit 23, in which the quadrature combining occurs according to the sum of squares rule, as a result of which the output signal of the quadrature combining unit 23 does not depend on the initial phase of the received echo signal.

The output signal of the quadrature combining unit 23 is supplied through the first input of the target detection and selection unit 24 to the threshold block 81 (see Fig. 5). In the threshold block 81, the incoming signal is compared with the threshold signal set in it, as a result of which a binary signal is generated at the output of block 81 and fed to the input of the shift register 82. The clock signal from the synchronizer 6 is supplied to the synchronizing input of the BOVC 24, which is fed to the sync input in block 24 the shift register 82 and the delay element 97. In this case, the signal from the output of the threshold block 81 is recorded in the first bit of the shift register 82, and the signal from the output of the RAM 83 from the cell, whose address is determined by the signal of the current range arriving at the first input of the BOVC 24, is recorded with a shift in the remaining bits, starting from the second from the counter 56 range.

At the beginning of each sensing interval, a start pulse from synchronizer 6 arrives at and at the beginning of each sounding interval at the zeroing input of range 56, and a synchronizing pulse arrives at synchronizer input at counter 56 from the output of synchronizer 6, ensuring the formation of the current range element code in counter 56.

The specified code of the current range element also arrives at the address inputs of the target availability RAM 86, the target intensity RAM 87, the target initial angle RAM 88, and the recording input of the range memory unit 92. The signal from the output of the shift register 82 is fed to the input of the RAM 83 and is written into it by a clock pulse from the synchronizer 6, which has passed through the delay elements 97 and 98.

Thus, after a certain number of sounding intervals in the RAM cells 83, a packet of single signals is formed corresponding to a packet of reflected pulses from the target, or a noise collection of random single signals against the background of a large number of zero bits.

The signal from the output of the shift register 82 also goes to the input of the adder 84 single bits, the output of which at the same time generates a code equal to the number of single bits in the output signal of the register 82 of the shift. The output signal of the adder 84 is supplied to a threshold block 85, where it is compared with a predetermined target detection threshold by the logic K from N, where K is the number of unit bits in the register 82, and N is the total number of bits in it.

If the specified threshold is exceeded, which corresponds to target detection in the current range element, the single output signal of the threshold block 85 is supplied to the And 99 element, the second input of which receives the signal from the RAM 86 of the presence of the target through the inverter 103. If in the previous sensing interval to the current cell RAM 86 was recorded a zero signal, indicating the absence of detection, then a single output signal of the inverter 103 coincides with a single output signal of the threshold block 85, which indicates the beginning of the reflected packet x from the target pulses. In this case, the clock pulse passes through the And 99 element from the output of the delay element 97, which goes to the synchronization input of the RAM 88 and writes the code of the beginning of the pulse train from the target to the cell from the sensor 27 of the angular position of the antenna in its cell corresponding to the current range element through the third entrance of BOVC 24.

The output signal of the adder 84 single bits, characterizing the intensity of the target in the current range element, also goes to the input of the RAM 87 of the target intensity and to the block 89 comparison, the second input of which comes from the RAM 87 signal of the target intensity for the current range element, recorded in it before (/ 3 / j)

21st sensing interval. If the signal of the adder 84 exceeds the signal of the RAM 87, then a single signal is generated at the output of the comparison unit 89, which is fed to the element And 101, the second input of which receives the output signal of the threshold block 85. In the event that this signal is single, which indicates the detection of the target , then through the element And 101 passes the clock from the output of the element 98 delay and writes the intensity of the target in the RAM 87 of the intensity of the target.

As a result of repeated repetition of the above operations in the RAM 87 is entered the maximum intensity of the targets for each element of the range. In the case when in the current sounding from the threshold block 85 a zero signal is received, indicating the absence of detection, and from the RAM 86, the presence of the target is a single signal indicating the presence of detection in the previous sounding interval, this combination of signals indicates the end of the packet in the current element range. Thus on the element And 100 receives two single signals from RAM 86 and from block 85 through the inverter 102.

At this time, from the RAM 87, the signal of the maximum target intensity for the current range element is supplied to the intensity memory unit 91 and to the comparison unit 90. The second input of the comparison unit 90 receives a signal from the intensity memory unit 91 recorded in it in the previous sounding interval. A single signal is generated at the output of the comparison unit 90 if the current intensity signal from the RAM 87 exceeds the intensity signal recorded previously in the memory unit 91. A single signal from the output of the comparison unit 90 is fed to the third input of the AND element 100, opening it to pass a clock from the output of the delay element 97.

Thus, at the output of the And 100 element, a pulse is formed at the moment of the end of the packet of reflected pulses from the target, the intensity of which exceeds the intensity of the targets detected earlier.

The pulse from the output of the element And 100 is fed to the clock input of the intensity memory unit 91 and writes a signal of the current intensity into it. As a result of repeated repetition of the above operations, the maximum intensity of the target detected by the radar is recorded in the intensity memory unit 91.

intensity.

The current value of the angle of rotation of the antenna from the sensor 27 of the angular position of the antenna through the third input of BOVC 24 is also supplied to the half-adder 94, the second input of which receives the angle code of the beginning of the pulse train from the target for the current range element from the RAM 88. At the output of the half-adder 94, a signal is generated half the sum of the angular positions of the antenna, corresponding to the beginning of the packet of reflected pulses and the current time.

At the time of formation of the pulse at the output of the And 100 element (the end of the burst of pulses from the target), the signal at the output of the half-adder 94 is equal to the half-sum of the coordinates of the beginning and end of the burst of pulses reflected from the target, which corresponds to the angular coordinates of the target. This signal enters the block 93 of the angle memory and is recorded in it by the output pulse of the element And 100.

Thus, after performing the above operations repeatedly, the coordinates of the target detected by the radar and having the maximum intensity are recorded in blocks 92 and 93 of the range and angle memory.

The trigger pulses of the synchronizer 6 through the start input of the unit 24 for detecting and selecting a target pass to the counter 95, which generates a control signal for the antenna drive, which from the third output of the BOVC 24 enters the angle switch 25 and passes to its output. From the output of the switch 25, the control signal is supplied to the antenna drive 26, which through the kinematic connection rotates the antenna 5 by an angle proportional to the incoming code. The antenna drive 26 is connected by a second kinematic connection with the antenna angular position sensor 27, at the output of which, when the antenna is rotated, a code for the current angular position of the antenna is generated, which arrives at the third input of the BOVC 24.

At the same time, the signal from the output of the counter 95 enters the decryptor 96 of the final code. When the counter reaches the corresponding code 95, the decoder 96 switches off and generates a control signal for the end of the space survey, which arrives at the fourth output of the BOVC 24.

Thus, during the review of the space at the outputs of the angle and range (first and second outputs) of the BOVC 24, the coordinates of the angle and range of the largest of the detected targets are recorded. These coordinates by the end of the pulse from the fourth output of the BOVC 24 are recorded respectively in the angle register 28 and the range register 30. At the same time, the control pulse of the end of the review enters the angle switch 25, switching it to the signal transmission position from its second input connected to the output of the converter 29.

The pulse of the end of the review also arrives at the control input of the target capture unit 33, in which it passes to the zeroing input of the counter 104 (see Fig. 6). The signal of the range register 30 is supplied to the adder 31, the second input of which receives the signal of the range discriminator 50, which has a zero output signal before starting operation. In this case, at the output of the adder 31, a signal is generated equal to the range code of the maximum detected target, which is transmitted to the code converter 32 in a time interval, to the trigger input of which from the synchronizer 6 a trigger pulse is received in each sounding. The Converter 32 generates at its output pulses delayed relative to the probe pulse of the radar for a time interval that, in total, with the delay on the delay element 54 corresponds to the range to the maximum detected target.

The output pulse of the converter 32 through the delay element 54 is fed to the start input of the target capture unit 33, in which through the open gate 110 it is supplied to the clock input of the counter 104 and to the synchronization inputs of the Doppler frequency filters 105i, -, 105m, in which it goes to the clock inputs of the integrators 125 and 126 sliding interval (see Fig. 8). The compressed quadrature signals from the outputs of the multi-bit matched filters 21 and 22 are respectively supplied to the sine and cosine information inputs of the target capture unit 33, in which they are fed to the inputs of the same-name filter 105h ..., 105s. In the PDF 105b, 105k, these signals are supplied to the first inputs of the multiplier 123 and the multiplier 124. The frequency inputs of the filters 105i, ..., 105s receive the sine and cosine signals from the outputs of the Doppler frequency generators 106b ..., 106y, each tuned to its frequency from the buses 107i, ..., 107N with the codes of the corresponding frequencies installed on them, shifted by the discrete Doppler frequency frequency D Gd, inversely proportional to the Tzx interval in the capture mode (A% 1 / Tzx).

In the Doppler frequency generators 106i, ..., 106N (see Fig. 7), the code signal from the buses 107i, ..., 107m is supplied to the first inputs of the sines ROM 121 and the cosines ROM 122, to the second inputs of which a counter signal 120 is applied, to the sync input of which a signal is supplied from the master oscillator 119. At the same time, at the outputs of the ROM 121 and 122, I form 0

The 24 outputs of the Doppler frequency generators 106i, ..., 106N generate sine and cosine signals of the corresponding frequency, which are supplied to the pass filter 105i, ..., 105N to the second inputs of the multipliers 123 and 124, respectively. The output signals of the multipliers 123 and 124 are fed to the inputs of the integrators 125 and 126 of the sliding interval equal to the capture interval Tzx.

The output signals of the sliding interval integrators 125 and 126 are supplied to the quadrature (sine and cosine) outputs of the Doppler frequency filter and to the inputs of the quadrature combining unit 127, at the output of which a modular value signal of the corresponding Doppler component of the target signal is generated, which is fed to the modular output of the Doppler frequency filter.

The integration of the signals in the integrators 125 and 126 of the sliding interval of the FDF 105, ..., 105s occurs until synchronizing pulses from the gate 110 are received at their synchro inputs. These pulses also arrive at the counter 104, increasing its content. The output of the counter 104 is supplied to the final code decoder 111, which is triggered when the set code is reached equal to the number of sounding intervals required to capture the target for tracking. The output signal of the decoder 111 sets the trigger 118 to a single state, in which the trigger 118 locks the valve 110 with its inverse output signal, and opens the valve 109 with a direct output signal.

In this case, the integration of signals in the FDF 105b-, 105m ends. The signals from the modular outputs of the PDF 105i, ..., 105N are supplied to the corresponding inputs of the switch 112, to the control input of which a signal is supplied from the counter 116.

The synchronizer pulses of the synchronizer 6 are received at the synchronization input of the singing capture unit 33 and, through the open valve 109, are fed to the input of the counter 116. The binary code from the output of the counter 116, which is transmitted to the control input of the switch 112, provides for the transmission of all the output signals of the PDF 105i, .. ., 105N. At the same time, the output signal of the counter 116, which is the code number of the current Doppler channel, the modular signal of which is generated at the output of the switch

112, enters the frequency register 115 and the final code decoder 117.

from the switch 112 exceeds the one previously recorded in the register 113, then a single signal is formed at the output of the comparison unit 114, opening the valve 108.

In this case, the clock signal from the output of gate 109 through the open gate 108 is fed to the clock inputs of registers 113 and 115. In register 113, it writes the output signal of the current Doppler channel, and in register 115 records the number of the current Doppler channel. Thus, the maximum of the signals of the Doppler channels is recorded in the register 113, and its number in the register 115.

After polling all the signals of the switch 112, the final code decoder 117 is triggered, the output of which resets the trigger 118. At the same time, the gate 109 is locked and the contents of the register 115 no longer changes. It stores the Doppler frequency code corresponding to the maximum signal.

The signal from the output of the register 115 enters through the information output of the target capture unit 33 to the input of the register 34, which is recorded by the signal of the decoder 117 coming from the control output of the target capture unit 33 to the clock input of the register 34. At the same time, this control signal of the target capture end arrives at block 49 gates, opening it.

Next, support for the selected target begins.

In this case, the Doppler frequency code from the output of the register 34 is supplied to the first input of the adder 44, the second input of which receives a signal from the frequency discriminator 51, reset to zero at the beginning of target tracking. The output signal of the adder 44 is supplied to the code input of the Doppler frequency generator 43, at the outputs of which the sine and cosine components of a given frequency are formed, which are fed to the corresponding frequency inputs of the Doppler frequency filters 35, 36 and 37. Sinus and cosine compressed signals from the outputs of multi-bit matched filters 21 and 22 are respectively supplied to the information inputs of filters 35, 36, and 37, and synchronization pulses, respectively, from the code converter 32 to the time interval, from the delay element 54, and from element 55, are supplied to their synchronization inputs delays. The delay value of the elements 54 and 55 is equal to half the sampling interval of the phase in the probe pulse. In this case, as in the capture mode, the clock signal from the output of the delay element 54 corresponds to the range of the captured and tracked target and is a signal of the central tracking gate, and the signals from the output of the code converter 32 to the time interval and the output of the delay element 55 correspond to the lead and delay half the sampling interval of the FM code relative to the set range to the target and are the signals of the corresponding tracking half-gates along the range.

The modular signals of the filters 35, 36, and 37 of the Doppler frequency are fed to the range discriminator 50, in which an estimate of the deviation of the clock signal from the output of the delay element 54 from the true range to the target is formed by the value of the output modular signals of the PDF 35, 36, and 37. The specified deviation signal from the output of the range discriminator 50 is fed to the second input of the adder 31, which with its output signal changes the delay of the pulses generated by the code converter 32 in the time interval relative to the triggering pulses of the synchronizer 6.

Thus, target tracking is implemented using the central tracking gate in the FFD 36 and two tracking half-gates in the FFD 35 and 37, while the FFD 35, 36 and 37 are narrow-band Doppler filters.

The signal from the output of the adder 44 is also fed to the first inputs of the adder 45 and the subtractor 47, the second inputs of which are supplied with a signal from the code line 48, on which the code of half the discrete Doppler frequency A Gd is set in the target capture unit 33. The output signals of the subtractor 47 and the adder 45 are supplied respectively to the HDC 41 and 42, which generate Doppler frequency signals shifted relative to the frequency of the generator 43 in different directions by half the discrete Doppler frequency D d.

Sine and cosine output signals of the HDF 41 and 42 are supplied to the corresponding frequency inputs of the PDF 38 and 39, respectively. The sync pulse from the delay element 54, corresponding to the central tracking gate in range, is fed to the synchro-inputs of the PDF 38 and 39. The sine and cosine information inputs of the PDF 38 and 39 receive signals from the outputs of the MSF 21 and 22. At the same time, the signals of the frequency half-gates of the Doppler frequency tracking signal shifted relative to the center tracking frequency in the FDF 36 are generated on the moving outputs of the FFD 38 and 39.

The output modular signals of the FFD 36, 38, and 39 are fed to the corresponding inputs of the frequency discriminator 51, the output of which, depending on the ratio of the output signals of the central strobe with the FFD 36 and the two side frequency half-gates of tracking with the FFD 38 and FFD 39, the frequency value ®0 $ / $ f; S

-27 mismatch, which from the output of the discriminator 51 goes to the second input of the adder 44, shifting by the appropriate amount of frequency generated by the HDC 41, 42 and 43, thus closing the signal tracking loop in frequency.

The quadrature components of the differential compressed signal from the outputs of the digital matched filter 16 are supplied to the corresponding information inputs of the Doppler frequency filter 40, the frequency inputs of which receive signals from the corresponding outputs of the Doppler frequency generator 43, and the signal from the output of the delay element 54 is received at the sync input, as a result of which the MFD 40 It works in the target tracking gate in range and in the central target tracking gate for the radar difference channel.

The output sine and cosine signals of the pass filter 40 are received respectively by the code dividers 52 and 53, the second inputs of which receive the sine and cosine output signals of the pass filter 36, operating in the total channel of the radar in the same tracking gates in range and frequency as the pass filter 40. the outputs of the code dividers 52 and 53 generate signals equal to the quotient of dividing the signals (sine or cosine) of the Doppler filter 40 of the difference signal by the same signal of the filter 36 of the Doppler frequency of the total signal.

The specified output signals of the dividers 52 and 53 are received in the adder 46 and are added to it. Thus, the dividers 52 and 53 and the adder 46 form an angular discriminator. The output signal of the adder 46 through the signal of the end of the capture target (from the output of the decoder 117 of the final code BZX 33), the valve block 49 is fed to the second input of the subtractor 29, where it is subtracted from the angle code received at its first input from the angle register 28. The output signal of the subtractor 29 through the angle switch 25 is fed to the antenna drive 26 and, thus, closes the target tracking loop in angle.

Thus, the proposed monopulse radar implements simultaneous tracking of the target in range, Doppler frequency and angle, providing improved tracking accuracy and noise immunity of the radar with respect to active and passive interference.

Based on the above description and drawings, the proposed device can be manufactured using well-known components and known technological equipment in the electronics industry and used

OG (3/96

-28 on mobile carriers as a radar for detecting and tracking targets.

LIST OF REFERENCES

1. Leonov A.I., Fomichev K.I. Monopulse radar. - M: Owls. Radio. 1970

 2. Handbook of radar. / Ed. M. Skolnik. - M: Owls. Radio. -1978 -T. 4.

3. RF patent No. 2084919, IPC G01S 13/44, publication July 20, 1997.

4. RF patent .№ 2099739, IPC GO IS 13/42, publication December 20, 1997, prototype.

5. Reference book on radar. / Ed. M. Skolnik. - M: Owls. Radio. - 1970 - T. 3, S. 19-52,103-107,144.

-29-i o / 5 /

The notation for FIG. 1 1- pathogen, 2-phase manipulator. 3- power amplifier, 4- antenna switch, 5- antenna, 6 synchronizer, 7- code generator, 8- pulse modulator, 9- total-difference converter, 10- high-frequency amplifier, 11- mixer, 12- intermediate frequency amplifier, 13-block quadrature phase detector 14-block quadrature phase detector 15-amplitude quantizer, 16-digital matched filter, 17, 18 - first and second blocks of comparator 19, 20 - first and second ATM, 21, 22 - first and second MSF, 23- quadrature combining unit, 24- BOVC, 25- angle switch, 26- antenna drive, 27- sensor antenna angular position, 28- angle register, 29- first subtractor, 30- range register, 31- first adder, 32- time code converter int- 33- БЗХ, 34- register, 35, 36, 37, 38, 39, 40 - first, second, tert 41, 42, 43 - first, second, third GDCH, 44, 45, 46 - second, third, fourth sum 47 - second subtractor, 48 - code bus, 49 - valve block, 50 - range discriminator , 51 - frequency discriminator, 52, 53 - the first and second code dividers, 54, 55 - the first and second delay element, 56 - range counter.

Monopulse radar

List 31 - threshold block

82-shift register

83- RAM

84- adder single bits

85- threshold block

86- RAM availability of the target,

87- ram target intensity,

88- RAM of the initial angle of the target, 89, 90 - comparison blocks,

91- intensity memory unit,

92- range memory unit,

93- corner memory block,

94 half-adder,

95 counter

96 - final code decoder, 97, 98 - delay elements,

99, 100, 101 - elements And, 102, 103 - inverters.

 -9

Monopulse radar

Claims (1)

A monopulse radar system containing a pathogen, a phase manipulator and a power amplifier connected in series through an antenna switch to an antenna that is kinematically connected to the antenna drive, and a sum-difference converter connected to the third arm of the antenna switch in series with the corresponding inputs and outputs of the sum and difference signals , high-frequency amplifier, mixer and intermediate-frequency amplifier, to the corresponding outputs of which о the block of quadrature phase detectors of the total signal and the block of quadrature phase detectors of the difference signal are connected, the sine and cosine outputs of which are connected through the amplitude quantizer to the corresponding information inputs of the digital matched filter, as well as a pulse modulator and code generator connected to the output of the synchronizing trigger pulses, the combining unit quadrature, range discriminator and code converter in the time interval, while the digital code inputs are consistent of the filter and phase manipulator are connected to the output of the code generator, the outputs of the local oscillator and intermediate frequency of the exciter are connected respectively to the heterodyne input of the mixer and the reference inputs of the blocks of quadrature phase detectors of the total and difference signals, and the output of the pulse modulator is connected to the second input of the power amplifier, characterized in that the first and second blocks of comparators, the first and second automatic threshold regulators, the first and second multi-digit matched filters, the block about target detection and selection, an angular position sensor of the antenna kinematically connected to the antenna drive, the control input of which is connected to the output of the angle switch, angle register, range register, target acquisition unit, first, second, third, fourth, fifth and sixth Doppler frequency filters, first, second and third Doppler frequency generators, first and second subtractors, register, first, second, third and fourth adders, code bus: valve block, frequency discriminator, first and second code dividers, first and second ele delays and a range counter, the resetting input of which is combined with the start inputs of the detection and target selection unit and the code converter in a time interval and is connected to the output of the trigger pulses of the synchronizer, the output of the synchronizing pulses of which is connected to the synchronization inputs of the first and second automatic threshold controllers, the detection unit and target selection, target capture unit and range counter, the output of which is connected to the first input of the detection and selection unit, the second input of which is connected to the output an ode of the quadrature combining unit, the third input is connected to the output of the antenna angular position sensor, the first and second outputs are connected to the recording inputs of the angle register and range register, the third output is connected to the first input of the angle switch, and the fourth output is to the control inputs of the angle switch, unit capture target, register range and register angle, the output of which is connected to the first input of the first subtracter, the second input of which is connected to the output of the valve block, and the output to the second input of the angle switch, the output of the register gave connected to the first input of the first adder, the second input of which is connected to the output of the range discriminator, and the output to the information input of the code converter in the time interval, the code inputs of the first and second multi-bit matched filters are connected to the output of the code generator, the inputs of which are combined with the inputs, respectively the first and second automatic threshold regulators are connected to the outputs of the first and second blocks of comparators, respectively, the first inputs of which are connected respectively to syn the sine and cosine outputs of the block of quadrature phase detectors of the total signal, and the second inputs are connected to the outputs of the first and second automatic threshold regulators, respectively, the sine and cosine information inputs of the quadrature combining unit, target capture unit, and Doppler filters are connected to the outputs of the first and second multi-bit matched filters frequencies from the first to fifth, sine and cosine outputs of the first and second Doppler frequency generators are connected to the corresponding to the frequency inputs of the fourth and fifth Doppler filters, respectively, the sine and cosine outputs of the third Doppler generator are connected to the corresponding frequency inputs of the first, second, third and sixth Doppler filters, the sine and cosine information inputs of the sixth Doppler filter are connected to the corresponding outputs of the digital matched filter, the output of the code converter in the time interval is connected to the synchronization input of the first Doppler filter frequency and the input of the first delay element, the output of which is connected to the synchronization inputs of the second, fourth, fifth and sixth Doppler filters, the input to the start of the target capture unit and the input of the second delay element, the output of which is connected to the synchronization input of the third Doppler filter, the sine outputs of the second and the sixth Doppler filters are connected respectively to the second and first inputs of the first code divider, and their cosine outputs are respectively connected to the second and first inputs of the second code divider, the modular output of the second Doppler filter is connected to the second inputs of the range discriminator and the frequency discriminator, the modular outputs of the first and third filters of the Doppler frequency are connected respectively to the first and third inputs of the range discriminator, and the modular outputs of the fourth and fifth filters of Doppler frequency are connected respectively to the first and the third inputs of the frequency discriminator, the output of which is connected to the second input of the second adder, the first input of which is dynamically with the register output, and the output is connected to the code input of the third Doppler frequency generator and to the first inputs of the second subtractor and third adder, the second inputs of which are connected to the code bus, the outputs of the second subtractor and third adder are connected to the code inputs of the first and second Doppler frequency generators, accordingly, the outputs of the first and second code dividers are connected to the corresponding inputs of the fourth adder, the output of which is connected to the input of the valve block, the control input of which is combined Synchronization of the input register and is connected to the control output target acquisition unit, the information output of which is connected to the input of a register entry.