RU171445U1 - Adaptive encryption device - Google Patents

Abstract

The utility model relates to the field of information encryption and can be used in data transmission systems to ensure their confidentiality. The device provides for increasing the cryptographic resistance of information to statistical cryptanalysis through the use of various recursive registers for various input information formats (text, multimedia), as well as increasing the encryption speed by selecting the length of the recurrent register in accordance with the input information format. The device includes a transmitter and a receiver, which consist of: an analyzer, a linear shift register synthesis block, a key generator, a linear shift register, a nonlinear logic block, an adder, a synchronization block, and a communication channel. The device operates as follows (see Fig.): The data intended for transmission inside the transmitter enters the synchronization block, where it is stored until a command is received from the nonlinear logic block. The key generator fills the linear shift register, the structure and dimension of which is determined in the synthesis unit of the linear shift register based on the format of the input information stream, according to the control command received from the analyzer. The output sequence from the linear shift register is complicated in the nonlinear logic block and enters the adder, where it is summed with the input information sequence received from the synchronization block. The encrypted information enters through the communication channel to the receiver, where it is decrypted and received at the output of the device. 1 ill.

Description

The proposed utility model relates to the field of information encryption and can be applied in data transmission systems to ensure their confidentiality.

The closest technical solution to the claimed and adopted as a prototype is an information encryption device (Romanets Yu.V., Timofeev P.A., Shangin V.F. Information security in computer systems and networks / Edited by V.F. Shangin. - 2nd ed., Revised and enlarged. - M .: Radio and communications, 2001. - P. 73-76. - prototype.), Containing a key generator, a linear shift register, a nonlinear logic block, an adder in the transmitter and receiver .

However, the known device today does not fully satisfy the requirements for information encryption devices, due to the impossibility of selecting and changing the structure of the linear shift register.

The purpose of the proposed device is to increase the cryptographic stability of information to statistical cryptanalysis, as well as to increase the encryption speed.

The goal is achieved in that the proposed device provides for the selection of a linear shift register by analyzing the format of the information received in the device, its encryption and decryption on the receiving side.

In the known technical solution there are signs similar to those of the claimed device. This is the presence of a transmitter and a receiver, and the presence of a key generator, a linear shift register, a nonlinear logic block, and an adder.

In contrast to the prototype, the inventive device in the transmitter has an analyzer that analyzes the format of the received information, a linear register synthesis unit that selects a linear shift register based on the command received from the analyzer, and a synchronization unit that provides control signals for simultaneous input to the input adder information flow and pseudo-random sequence received from a nonlinear logic block.

In this regard, the claimed technical solution has significant differences from the known prototype. The applicant did not find similar solutions with similar features of the proposed technical solution, and therefore, the applicant concludes that the claimed solution has significant differences.

As a result of the analysis, it was found that the proposed device allows to increase the cryptographic stability of information to statistical cryptanalysis through the use of various recurrence registers for various input information formats (text, multimedia), as well as to increase the encryption speed by selecting the length of the recurrent register in accordance with the input information format .

The figure shows a structural diagram of the device.

The device contains (see Fig.): A transmitter, which consists of: an analyzer (1), a linear shift register synthesis block (2), a key generator (3), a linear shift register (4), a nonlinear logic block (5), a block synchronization (6), adder (7), communication channel (8), receiver, which consists of: an analyzer (9), a synthesis block of linear shift registers (10), a key generator (11), a linear shift register (12), a block nonlinear logic (13), synchronization block (14), adder (15).

The device operates as follows: the data intended for transmission inside the transmitter enters the synchronization block (6), where it is stored until a command is received from the nonlinear logic block (5). The key generator (3) fills the linear shift register (4), the structure and dimension of which is determined in the synthesis unit of the linear shift register (2) based on the format of the input information stream, according to the control command received from the analyzer (1). The output sequence from the linear shift register is complicated in the nonlinear logic block (5) and enters the adder (7), where it is summed with the input information sequence received from the synchronization block (6). The encrypted information is transmitted through the communication channel (8) to the receiver, where it is decrypted and received at the output of the device.

INFORMATION SOURCES:

1. Romanets Yu.V., Timofeev P.A., Shangin V.F. Information Security in Computer Systems and Networks / Ed. V.F. Shangina. - 2nd ed., Revised. and add. - M.: Radio and Communications, 2001. - S. 73-76. - prototype.

Claims (1)

An adaptive encryption device containing a key generator, a linear shift register, a nonlinear logic unit, an adder in the transmitter and receiver, a communication channel, characterized in that it is additionally introduced in the transmitter: a synchronization unit, one input of which is the information input of the device, the second input is the output of the unit nonlinear logic, and the output is connected to the adder, the analyzer, the input of which is the information input of the device, and the output is connected to the synthesis unit of linear shift registers, the output of which is connected with linear shift register input; in the receiver: a synchronization unit, one input of which is connected to the communication channel, the second input is the output of the nonlinear logic unit, and the output is connected to the adder, an analyzer, the input of which is connected to the communication channel, and the output is connected to the synthesis unit of linear shift registers, the output of which is connected with linear shift register input.

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