RU157940U1 - SAMPLING AND STORAGE DEVICE - Google Patents

Abstract

1. A sampling and storage device containing a first analog key, two operational amplifiers, a feedback resistor, two on-board diodes, a positive capacitor converter, the input of the device being connected to the non-inverting input of the first operational amplifier, the output of which is directly connected to the input of the first analog the key and through counter-on diodes is simultaneously connected to the inverting input of the first operational amplifier and a feedback resistor, the second output to connected at the same time with the output and inverting input of the second operational amplifier, the output of which serves as the output of the sampling and storage device, the output of the first analog key is connected to the non-inverting input of the second operational amplifier and the first input of the positive capacitor converter, characterized in that the first and second pulse shaper, delay element, second analog switch, two logical inverters, 2I logic element, the control input of the sample device and and storage, through a first pulse shaper, connected to a parallel control input of the second analog key, input of the delay element and the input of the first logical inverter, the input of the second analog key is grounded, and the output is connected to the second input of the positive capacitor converter, the output of the delay element, through a second pulse shaper, connected to the control input of the first analog switch and the input of the second logical inverter, the outputs of the first and second logical inverters

Description

The technical field to which the utility model relates.

The utility model relates to automation and measurement technology and can be used in analog-to-digital signal processing systems.

State of the art

A device for sampling and storage containing an analog key, two repeaters on operational amplifiers, a storage capacitor, a feedback resistor, a limiting resistor, two on-board diodes, and when the analog key is in the closed state (memory mode), the output potential of the first operational amplifier is known , due to the action of the general negative feedback, it is set such that the output voltage differs from the input voltage by the bias voltage of the first operational amplifier I am. In this case, the bias arising due to the presence of the switch (key) and the second operational amplifier is reduced to zero. The diodes in this state of the circuit are locked, since the voltage drop across them, equal to the indicated bias, is quite small (less than 20 mV). When the key is opened with a control signal, the output voltage remains unchanged. The feedback resistor and diodes prevent saturation of the first operational amplifier, which could have occurred due to the opening of the common negative feedback in this mode. This reduces the transient time when the key is locked. The first operational amplifier provides a high input impedance to a sampling and storage device ([1, p. 102, Fig. 3] - Zhavoronkova MS, Bondar SN Development of a high-speed sampling and storage device with increased accuracy // Methods and technical means of increasing the effectiveness of the use of electrical equipment in industry and agriculture: collection of scientific papers based on the materials of the 75th scientific and practical conference of the Faculty of Electric Power StGAU. - Stavropol: AG-RUS, 2011. P. 100-104).

The disadvantage of this device is the large value of the sampling time Δt _sampling and the small value of the ratio Δt _storage / Δt _sampling .

A device for sampling and storage containing a non-inverting voltage amplifier, the input of which is simultaneously the information input of the device for sampling and storage and the second input of the comparison circuit, the first input of which is connected to the output of the repeater on the operational amplifier and the output of the device for sampling and storage; the output of the comparison circuit is connected to the S-input of the trigger, the R-input of which serves as the control input of the sampling and storage device; the trigger output is connected to the control input of the analog switch, the input of which is connected to the output of a non-inverting voltage amplifier, and the output is connected to the inputs of the storage capacitor and repeater on the operational amplifier; the comparison circuit contains two comparators and an OR-NOT circuit, the inputs of which are the outputs of the comparators, and the output serves as the output of the comparison circuit; opposite inputs of the comparators are interconnected and with the inputs of the comparison circuit ([2] - patent RU 63623, IPC H03K 17/60).

The disadvantage of this device is the low accuracy of storing the magnitude of the voltage of the input signal.

The closest analogue is the prototype of the claimed technical solution is a sampling and storage device containing an analog key, two operational amplifiers, a feedback resistor, two on-board diodes, a positive capacitance converter, and the input of the device is connected to a non-inverting input of the first operational amplifier, the output of which directly connected to the input of the analog key and through counter-on diodes, simultaneously connected to the inverting input of the first opera an ion amplifier and a feedback resistor, the second output of which is connected simultaneously with the output and inverting input of the second operational amplifier, the output of which serves as the output of the sampling and storage device, the control input of which is the control input of the analog key, the output of which is connected to the non-inverting input of the second operational amplifier and converter input positive capacitance.

The positive capacitance converter contains two operational amplifiers, four resistors, a capacitor; moreover, the capacitor is grounded by one contact, the second contact is connected to the inverting input of the first operational amplifier and the input of the first resistor, the output of which is connected to the inverting input of the second operational amplifier and the input of the second resistor, the output of which is connected directly to the output of the second operational amplifier and is connected to parallel through the third resistor connected to a non-inverting input of the second operational amplifier, the output of the first operational amplifier and the input of the fourth resistor, output which is connected to the non-inverting input of the first operational amplifier and the input of the converter of positive capacitive resistance ([3] - patent RU 2342714, IPC G11C 27/02, H03K 17/60).

At the sampling stage, the sampling result is described by the expression:

where U _o - the output voltage of the device sampling and storage;

U _I - the input voltage of the device sampling and storage;

U _c.con is the voltage on the artificial capacitance created by the converter of positive capacitance during the sampling period;

U _s.con.oz - residual charge voltage of the artificial capacity created by the converter of positive capacitance during the sampling period, corresponds (without taking into account the drop in the output voltage) U _{s.con. of the} previous sample;

τ _s.con is the time constant of the charge circuit of the artificial capacity created by the converter of positive capacitive resistance.

That is, in the charge mode of the artificial capacity created by the positive capacitance converter, a switching process takes place in the sampling and storage device with non-zero initial conditions, which are the residual charge voltage of the artificial capacity U _s.con.oz.

. Due to the effect _s.kon.oz U, sampling time Δt _sps required to achieve a given accuracy of memorizing the input signal to be uneven (Figure 1: curve U _{s.kon.1 SELECT1} → Δt; curve U _{s.kon. .2} → Δt _{select 2} ; curve U _{s.con. 3} → Δt _{select 3} ; curve U _{s.con. 4} → Δt _{select 4} ), and since reading devices, for example, ADCs, operate in synchronous mode, time samples in the prototype will be determined by condition (2)

To quantify the effect of the residual charge voltage of the artificial capacity U _s.con.oz on the sampling time in the prototype Δt select _, we introduce the parameter n _u , expression (3)

and parameter n _τ , expression (4)

Taking into account (3), expression (4) will take the form:

, [%] - относительная погрешность представления входного сигнала на выходе устройства (относительная погрешность заряда искусственной емкости создаваемой конвертором положительного емкостного сопротивления в период выборки).Where

, [%] is the relative error in the representation of the input signal at the output of the device (the relative error in the charge of the artificial capacity created by the converter of positive capacitance during the sampling period).

Graph of the function n _τ = f (n _u ), for a typical value of the relative error δ = 0.1%, in the range -1 <n _u <3 (U _c.con.oz ∈ [-U _in ; 3 · U _in ] ) shown in FIG. 2. As follows from the graph, FIG. 2, for given conditions, the relation (6)

That is, the presence of a residual charge voltage of an artificial capacity U _c.con.oz results in:

- to uneven sampling time;

- increase in sampling time, relative to the required interval, by 10%;

- ambiguities in the relative error in the representation of the input signal at the output of the device (ambiguities in the accuracy of memorization).

The disadvantage of this device is the large value of the sampling time Δt _sampling with ambiguity in the accuracy of memorization.

Utility Model Disclosure

The technical result that can be achieved using the proposed utility model is reduced to reducing the sampling time Δt of the _sample while ensuring a given accuracy of memorization.

The technical result is achieved in that a sampling and storage device containing a first analog switch, two operational amplifiers, a feedback resistor, two on-board diodes, a positive capacitance converter, the input of the device being connected to a non-inverting input of the first operational amplifier, the output of which is directly connected to the input of the first analog key and through the on-off diodes, is simultaneously connected to the inverting input of the first operational amplifier and feedback loop source, the second output of which is connected simultaneously with the output and inverting input of the second operational amplifier, the output of which serves as the output of the sampling and storage device, the output of the first analog key is connected to the non-inverting input of the second operational amplifier and the first input of the positive capacitor converter, the first and a second pulse shaper, a delay element, a second analog switch, two logical inverters, a 2I logic element, and the device control input and the sampling and storage, through the first pulse shaper, is connected to the parallel control input of the second analog key, the input of the delay element and the input of the first logical inverter, the input of the second analog key is grounded, and the output is connected to the second input of the positive capacitor converter, output of the delay element, through a second pulse shaper, connected to the control input of the first analog switch and the input of the second logical inverter, the outputs of the first and second logical inverters connected to the inputs of the logic element 2I, the output of which serves as the control output of the device selection and storage.

The positive capacitance converter contains two operational amplifiers, four resistors, a capacitor, and the capacitor is grounded with one contact, the second contact is connected to the second input of the positive capacitance converter, to the inverting input of the first operational amplifier and the input of the first resistor, the output of which is connected to the inverting input of the second operational amplifier and the input of the second resistor, the output of which is connected directly to the output of the second operational amplifier and h Through the third resistor, it is connected to a non-inverting input of the second operational amplifier connected in parallel, the output of the first operational amplifier and the input of the fourth resistor, the output of which is connected to the non-inverting input of the first operational amplifier and the first input of the positive capacitor converter.

Brief Description of the Drawings

In FIG. 1 shows timing diagrams illustrating the operation of the prototype.

In FIG. 2 shows a graph of the function n _τ = f (n _u ) of the prototype.

In FIG. 3 shows a functional diagram of a sampling and storage device.

In FIG. 4 is a timing diagram explaining the operation of the sampling and storage device.

Utility Model Implementation

The sampling and storage device contains operational amplifiers 1 (ОУ1) and 6 (ОУ2), analog switches 2 and 18, diodes 3 (D1) and 4 (D2), a feedback resistor 5 (R1), a positive capacitance converter 7, shapers pulses 15 and 17, delay element 16, logic inverters 19 and 20, logic element 2I 21, and the input of the device is connected to the non-inverting input of the operational amplifier 1, the output of which is directly connected to the input of the analog key 2 and through the on-board diodes 3 and 4, simultaneously connected to inverting input the operational amplifier 1 and the feedback resistor 5, the second output of which is connected simultaneously with the output of the sampling and storage device and the inverting input of the operational amplifier 6, the output of the analog key 2 is connected simultaneously with the non-inverting input of the operational amplifier 6 and the first input of the positive capacitor converter 7, the control input of the sampling and storage device, through a pulse shaper 15, is connected to a parallel connected control input of the analog key 18, the input element levers 16 and the input of the logical inverter 19, the input of the analog key 18 is grounded, and the output is connected to the second input of the converter 7 of positive capacitive resistance, the output of the delay element 16, through the pulse former 17, is connected to the control input of the analog key 2 and the input of the logical inverter 20, outputs logical inverters 19 and 20 are connected to the inputs of the logic element 2I 21, the output of which serves as the control output of the device for sampling and storage.

The positive capacitance converter 7 contains a capacitor 8 (C), operational amplifiers 9 (GLC) and 11 (GC4), resistors 10 (R2), 12 (R3), 13 (R4), 14 (R5), and the capacitor 8 is one contact is grounded, and the second contact is connected to the second input of the converter 7 of positive capacitive resistance, to the inverting input of the operational amplifier 9 and the input of the resistor 10, the output of which is connected to the inverting input of the operational amplifier 11 and the input of the resistor 12, the output of which is connected directly to the output of the operational amplifier 11 and through h resistor 13, is connected to the non-inverting input of the operational amplifier 11 connected in parallel, the output of the operational amplifier 9 and the input of the resistor 14, the output of which is connected to the non-inverting input of the operational amplifier 9 and the first input of the positive capacitance converter 7.

A functional diagram of a sampling and storage device is shown in FIG. 3.

The principle of operation of the proposed device sampling and storage is a series of operations.

1) Forced accelerated discharge (PUR) of the artificial capacity created by the converter 7 of positive capacitance, and in fact, the capacitor 8 of the converter 7 of positive capacitance, according to the expression (7)

where τ _pur is the time constant of the forced accelerated discharge circuit of the capacitor 8 of the converter 7 of positive capacitive resistance.

Moreover:

and in the limit

this is ensured by the analog key 18. And this means that the time interval of the forced accelerated discharge of the capacitor 8 of the positive capacitance converter 7 (the artificial capacity created by the positive capacitance converter 7) Δt _pur , FIG. 4, characterized by the condition

2) The charge of the artificial capacity created by the converter 7 of positive capacitive resistance, FIG. 4, according to the expression (11)

Given the expressions (4), (5), (7) ÷ (11), the relation (12)

which corresponds to n _τ (n _u = 0) of the prototype, FIG. 2. Thus, a reduction in sampling time Δt of the _sample (relative to the prototype) in the limit of 10% will be achieved while ensuring the specified accuracy of memorization, that is, the disadvantages of the prototype are eliminated.

3) Reading the stored voltage during the storage time interval Δt _xp. (Fig. 4, where ΔU is the sampling error of the instantaneous value of the analog voltage).

The operation of the device is illustrated by timing diagrams (Fig. 5), which show:

- the start pulse of the sampling and storage device (input control voltage u _control ) (Fig. 5, a);

- output voltage u ₁₅ of the pulse shaper 15 (Fig. 5, b);

- output voltage u ₁₆ of the delay element 16 (Fig. 5, c);

- output voltage u ₁₇ of the pulse shaper 17 (Fig. 5, g);

- the input voltage of the device u _I , the output voltage of the device u ₆ (Fig. 5, d);

- output voltage u _{19 of the} logical inverter 19 (Fig. 5, e);

- output voltage u _{20 of the} logical inverter 20 (Fig. 5, g);

- the output voltage u _{21 of the} logic element 2I 21 (Fig. 5, and).

The device sampling and storage works as follows.

The start pulse U _control arriving at the control input of the sampling and storage device at time t ₀ (Fig. 5, a) provides, by means of a pulse shaper 15 (Fig. 5, b), the analog switch 18 is closed and forced accelerated discharge of the capacitor 8 Converter 7 positive capacitive resistance (artificial capacity created by the Converter 7 positive capacitive resistance), according to the expression (7). Moreover, due to the fulfillment of conditions (8) and (9) (the pass-through resistance of the closed key in modern ICs is about 0.5 Ohms ([4] 0.45-Ω quad spdt analog switch 4-channel 2: 1 multiplexer - demultiplexer with two controls . [Electronic resource] TS3A44159. Http://www.farnell.com/datasheets/1789043.pdf (accessed: 03/22/2015.)), Time interval of forced accelerated discharge of the capacitor 8 of the converter 7 of the positive capacitive resistance (artificial capacity created by the converter 7 of positive capacitance) Δt _pur = t ₁ -t ₀ (Fig. 5.1) will correspond to condition (10).

The signal from the output of the delay element 16 (Fig. 5, c) provides, by means of a pulse shaper 17 (Fig. 5, g), the analog key 2 is closed and the artificial capacitance created by the positive capacitance converter 7 (Fig. 5, e) is charged according to expression (11). Moreover, the time constant of the charge circuit of the artificial capacity τ _s.con created by the converter 7 is determined by the expression (13)

where R _AK - the passage resistance of the closed analog switch 2;

C _con - the value of the artificial capacity created by the Converter 7, expression (14)

where K _k is the conversion coefficient, in the general case, K _k <<1;

C is the capacitance of the capacitor 8 (C);

R _{2 ÷ 5} is the resistance of the resistors, respectively 10 (R2), 12 (R3), 13 (R4), 14 (R5).

It should be borne in mind that the operational amplifier 1 provides a high input resistance of the sampling and storage device, and the output potential of the operational amplifier 1, due to the action of the general negative feedback, is set so that the output voltage differs from the input voltage by the bias voltage of the operational amplifier 1. the offset due to the presence of an analog key 2 and an operational amplifier 6 is reduced to zero. Diodes 3 and 4 in this state of the circuit are locked, since the voltage drop across them, equal to the indicated bias, is quite small (less than 20 mV).

Upon completion of the pulse formation, by the pulse shaper 17 (Fig. 5d), the analog switch 2 opens, the sampling and storage device goes into storage mode - the time interval is Δt _xp = t ₅ -t ₃ (Fig. 5, d)). Which is indicated by the pulse at the control output of the firing and wound device (Fig. 5, i), formed by the logic element 2I 21. The input signals of which are inverted by means of logical inverters 19 and 20 (Fig. 5, f, g), respectively , the output signals of the pulse shapers 15 and 17.

It should be noted that the operational amplifier 6 is turned on according to the repeater circuit, whereby the voltage at the output of the sampling and storage device corresponds to the voltage established at the input of the converter 7 of positive capacitive resistance (voltage drop across the converter 7), and the decrease in the output voltage of the sampling device and storage ΔU (Fig. 4) is determined by the storage time constant τ _x.con

where R _IO.OU2 is the input impedance of operational amplifier 6 (OA2), in general, R _IO.OU2 is thousands of MΩ ([5] - Sample-and-hold amplifiers LF198 / LF298 / LF398 [Electronic resource] http: // pdf.datasheetarchive.com/indexerfiles/Scans-064/DSA2IH00144263.pdf (accessed March 22, 2015.)).

In the future, the algorithm of the sampling and storage device is repeated.

Formers shortened pulse 15 and 17 can be made in the form of waiting multivibrators or single vibrators.

The introduction, in the proposed device, of the operation of forced accelerated discharge of the artificial capacity created by the converter 7 of positive capacitive resistance, and, in fact, the capacitor 8 of the converter 7 of positive capacitive resistance, eliminates the influence of the residual charge voltage of the artificial capacity U _s.con.oz on the sampling time, which allows to reduce sampling time Δt _sampling while ensuring a given accuracy of memorization.

Claims (2)

1. A sampling and storage device containing a first analog key, two operational amplifiers, a feedback resistor, two on-board diodes, a positive capacitor converter, the input of the device being connected to the non-inverting input of the first operational amplifier, the output of which is directly connected to the input of the first analog the key and through counter-on diodes is simultaneously connected to the inverting input of the first operational amplifier and a feedback resistor, the second output to connected at the same time with the output and inverting input of the second operational amplifier, the output of which serves as the output of the sampling and storage device, the output of the first analog key is connected to the non-inverting input of the second operational amplifier and the first input of the positive capacitor converter, characterized in that the first and second pulse shaper, delay element, second analog switch, two logical inverters, 2I logic element, the control input of the sample device and and storage, through a first pulse shaper, connected to a parallel control input of the second analog key, input of the delay element and the input of the first logical inverter, the input of the second analog key is grounded, and the output is connected to the second input of the positive capacitor converter, the output of the delay element, through a second pulse shaper, connected to the control input of the first analog switch and the input of the second logical inverter, the outputs of the first and second logical inverters 2I enes to the inputs of the logic element whose output serves as output of the sampling device and the storage control. 2. The sampling and storage device according to claim 1, characterized in that the positive capacitance converter contains two operational amplifiers, four resistors, a capacitor, the capacitor being grounded with one contact, the second contact is connected to the second input of the positive capacitance converter, and the inverting input of the first operational amplifier and the input of the first resistor, the output of which is connected to the inverting input of the second operational amplifier and the input of the second resistor, the output of which is not connected Directly with the output of the second operational amplifier and through the third resistor, it is connected to the non-inverting input of the second operational amplifier connected in parallel, the output of the first operational amplifier and the input of the fourth resistor, the output of which is connected to the non-inverting input of the first operational amplifier and the first input of the positive capacitor converter.

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