RU1547U1 - VOLTAGE AC VOLTAGE CONVERTER TO DIGITAL CODE - Google Patents

Abstract

A high-speed AC / DC converter in a digital code containing a step-down transformer, the primary windings of which are connected to the input terminals of the converter, the first terminal of the secondary winding of the transformer is connected to the common converter bus, and the second terminal of the winding is connected to the input of the low-pass filter, the output of which is connected to the input of the first input inverter and the input of the first zero-organ, the output of which is connected to the direct and inverse inputs of the first and second formers, the first and second analog to light, an amplitude peak detector, the control input of which through the first ballast resistor is connected to the information input of the third analog switch, the output of which is connected to the common bus of the converter, the first adder, the second input of which is connected to the output of the first reference voltage source, characterized in that it additionally input register, analog-to-digital converter, clock generator, second zero-organ, first and second ideal rectifiers, second inverter, second adder, second are introduced reference voltage source, third and fourth drivers, AND-NOT element, first, second and third LEDs, second, third and fourth ballast resistors, first, second, third elements NOT with open collector outputs, decoder, first, second, third comparators, resistive divider, smoothing capacitor, diode, the anode of which is connected to the output of the low-pass filter, and the cathode is connected to the combined non-inverting inputs of the comparators and through the smoothing capacitor with a common converter bus, inverting

Description

The proposed utility model relates to the field of electrical measurements and can be used as a fast-response) 70 sensor for the amplitude value of an alternating voltage. in the construction of information-measuring, as well as regulatory and control systems.

Known high-speed AC voltage converter 1D 1 to constant l, containing a transformer, a half-wave rectifier diode bridge, a resistor voltage divider, a smoothing capacitor, a voltage follower, an amplifier of a variable voltage component, a voltage combiner, a bias voltage source

The disadvantages of the analogue are low speed (due to the inertia of the variable voltage component amplifier based on an operational DC amplifier with an isolation capacitor at the input), as well as a high level of ripple of the converter output voltage.

Also known is an AC to DC amplitude converter 2 comprising a phase inverter, diode-capacitive storage cells, switches, an OR diode element, an adder, comparators, shapers.

The disadvantages of the converter are: a) low accuracy due to the presence of a phase inverter, which introduces an error due to various parameters of the semi-windings; b) the uneven duration of the steps of the output voltage of the converter, formed after the end of each next half-cycle of the mains voltage (manifests itself during transient processes of the converter and is caused by the changing reference voltage of the comparators supplied to their inputs from the output of the device) - this drawback makes it difficult to synchronize the converter with subsequent blocks of systems and devices into which the converter is included, and sometimes introduces an additional error in the operation of the entire system as a whole;

c) High ripple level (due to the large discharge current of the diode-capacitive storage cells through the input resistance of the adder).

Closest to the proposed technical solution is a high-speed AC-to-DC converter containing a step-down transformer, a low-pass filter, an inverter, a zero-organ, analog switches, drivers, amplitude peak detectors, an adder with smoothing, a voltage reference source.

The disadvantages of the converter are: a) the impossibility of its direct connection to the interface of computer systems (since an analog signal is generated at the converter output); b) the need to manually switch the measuring range at various levels of the input mains voltage; c) significant complexity of the converter circuit; d) low accuracy due to the need to identify the output signals of the two channels of the Converter,

The purpose of the proposed utility model is a) to improve the usability of the device; b) simplification of the device circuit; improving the accuracy of the conversion of the investigated signal.

This goal is achieved by the fact that into a high-speed AC / DC converter containing a step-down transformer, the primary windings of which are connected to the input terminals of the device, the first output of the secondary winding is connected to the common bus of the device, and the second is connected to the input of the low-pass filter, zero-organ The output of which is connected with the direct and inverse inputs of the first and second formers, an amplitude peak detector controlled from an analog switch through a ballast resistor, an adder, the first the path of which is connected with the output of the amplitude peak detector, and the second with the reference voltage source, additionally / introduced an output register, an analog-to-digital converter, a clock generator, a second zero-organ, the first and second ideal rectifiers, the second.inverter, the second adder, the second source of reference support. first and second analog switches, third and fourth drivers, I-HE element, first, second and third LEDs, ballast resistors, element NOT with open collector output gjo; U) oY3

 2.

 ..; - ,: -. . X

Dami, decoder, first, second and third comparators, a resistor divider, a smoothing capacitor, a diode, an anode connected to the output of the low-pass filter, and a cathode with a smoothing capacitor and non-inverting inputs of the comparators, to the inverting inputs of which are connected the outputs of the resistor divider, in which the output of the first resistor is connected to the power source, and the output of the last resistor is connected to the device’s common bus, the outputs are, “Homparators are connected to the inputs of the decoder, the outputs are connected to the control inputs the first and second channels of the switch keys and with the inputs of the elements NOT, the open collector outputs of which are connected through ballast resistors and LEDs to a power source, the input of the first inverter is connected to the output of the low-pass filter, and the output is connected to the input of the second analog key and to the input of the second inverter, output which is combined with the output of the second analog switch and connected to the input of the first ideal rectifier, the output of which is connected to the first input of the first adder, the second input of which is connected to the output of the first about the reference voltage source, the output of the first adder is connected to the input of the amplitude peak detector, the control input of which is connected via a ballast resistor and the third analog key to the device common bus, the control input of the third analog key is connected to the output of the AND-NOT element, the inputs of which are connected to the inverse outputs the first and second shapers, the output of the amplitude peak detector is connected to the first input of the second adder, the second input of which is connected to the output of the second voltage reference and the output of the second adder is connected to the input of the second ideal rectifier © and to the input of the second zero-organ, the inverse input of the third driver is connected to the output of the I-NB element, and the output is connected to the inverse input of the fourth driver, the direct output of which is connected to the analogue input -digital converter, the clock input of which is connected to the output of the clock generator, and the information input of the analog-to-digital converter is connected to the output of the second ideal rectifier, and the analog-to-digital readiness output th transducer is connected to the input of output register records significant bits of data input which are connected to information outputs of the analog-to-digital, converter, and the high output register information input coupled to an output of the second zero-organ.

SBOMffY.

I 0,

The essence of the proposed utility model is illustrated by the drawing, where Fig. I shows a diagram of the device, Fig. 2 shows a diagram of an ideal rectifier, Fig. 3 shows a diagram of an amplitude peak detector, and Fig. 2 shows graphs of changes in voltage across the elements of the device. The converter circuit contains a step-down transformer I, the primary coils of which are connected to the input terminals of the device, the first output of the secondary winding is connected to the common bus of the device, and the second output is connected to the input of the low-pass filter 2, the output of which is connected to the input of the first zero-organ 3, the input of the first inverter 4 and with the anode of the diode 5, the cathode of which is connected to the smoothing capacitor b and to the non-inverting inputs of the comparators 7,8,9, to the inverting inputs of which are connected the outputs of the resistor divider, consisting of of resistors 10,11,12, 13 (of which the extreme terminal of resistor 10 is connected to a power source, and the extreme terminal of resistor 13 is connected to the device’s common bus), outputs; k0mparators 7,8,9 are connected to inputs of decoder 14, the outputs of which are connected with control inputs per. VOG0 and the second analog switch with 15.16 inputs of the elements NOT 17,18,19, the open collector outputs of which are connected via ballasts 20,21,22 and LEDs 23,24,25 with a power source, the first inverter 4, the output of which is connected to the input the second analog switch 16 and with the input of the second inverter 26, the OUTPUT of which is connected to the input of the first analog switch 15, the output of which is combined with the output of the second analog switch 16 and connected to the input of the first ideal rectifier 27, the output of which is connected to the first input of the first adder 28, second the input of which is connected to the output of the first reference voltage source 29, the output of the first adder 28 is connected to the input of the peak amplitude detector 30, the control input of which is connected via a ballast resistor 31 and the third analog key 32 to the common bus, the control input of the third analog key 32 is connected to the output of the AND-NOT 33 element, the inputs of which are connected to the inverse outputs of the first and second shapers 34, -35, of which the direct input of the first shaper 35 is connected to the output of the first zero-Morgan 3 and the inverse: the course of the second shaper 35 is connected to the output of the first null-organ 3, the second adder 36, the first input of which is connected to the output of the peak pick-up detector 30, and the second input is connected to the output

a hot reference voltage source 37, and the output of the second adder 36 is connected to the input of the second ideal rectifier 38 and to the BTOpojo input of the zero-organ 39, the inverse input of the second driver 40 is connected to the output of the I-HB 33 element, and the output is with the inverse input of the fourth driver 41, the direct output of which is connected to the start input of the analog-to-digital converter 42, the clock input of which is connected to the output of the clock generator 43, and the information input of the analog-to-digital converter 42 is connected to the output of the second ideal ryamitelya 39 and output readiness analog-digital converter 42 is connected to the input of recording the output register 44, lower level data input which are connected to information outputs of the analog-digital converter 42, and is connected to the output of the second zero-body 39 senior information input of output register 44.

The proposed utility model can be divided into two functional blocks: an automatic adjustment unit for the voltage measurement range A and an analog-to-digital conversion unit B ($ ig. 1).

The automatic adjustment block of the measuring range A is formed from diode 5, capacitor b, resistor divider, consisting of resistors 10,11,12,13, comparators 7,8,9, decoder 14, elements NOT with open collector outputs 17, 18,19, ballast resistors 20,21,22, LEDs 23,24,25, inverters 4, 26, analog switches 15,16. The block for automatic adjustment of the measuring range A carries out: a) automatic subtraining of the measuring range; b) Indication of the value of the nominal voltage in the investigated network; c) the function of protecting the measuring part of the converter from overvoltage in the network.

Block automatic adjustment of the measuring range And works as follows.

When the primary winding of the step-down transformer I (having a transformation coefficient KI) is connected to the network, a voltage appears at the output of the secondary winding of this transformer, which is fed to the input of the low-pass filter 2. Next, the signal is rectified through diode 5 and, smoothed by capacitor 6, is fed to non-inverting inputs comparators 7.8.9. When the current voltage reaches 70 Volts, it works

k®mparavr9, the unit voltage at eg®out®de p ©, the sneaker at the inputs of the decoder 1 is set to 001, and a single voltage appears on the second output of the decoder 14, which is supplied to the control input of the second analog switch 16 and the element is NOT 17, V As a result, the output of the element NOT 17 opens, through the LED 23, corresponding to the level of the nominal voltage in the 100 volt network, current flows and the LED 23 lights up and the voltage from the output of the first inverter 4 through the second analog to Uche 16.

When the primary winding of the step-down transformer I is connected to the network with the current nominal voltage level of 220 volts, comparators 8.9 are triggered, the code at the inputs of the decoder 14 becomes equal to OH, as a result of which a single voltage appears on the fourth output of this decoder, which is supplied to the element NOT 18 and to the first analog switch 15, as a result of which the first analog switch 15 is unlocked (while the second analog switch 16 is closed) and supplies the voltage from the second inverter 2 to the input of the first ideal rectifier 27 6, the LED 24 lights up, corresponding to the level of the rated voltage in the network 220 volts. The gain of the inverter 26 is 2.2 times less than that of the first inverter 4 and POET0MU with the same relative changes in voltage in the network with a nominal value of 100 volts and 220 volts, the voltage changes applied to the input of the first ideal rectifier 27 will also be the same .

When the operating voltage rises above 290 volts, the comparators 7,8,9 are triggered, as a result, the code supplied to the decoder 14 becomes equal to III, a high potential appears on the seventh output of this decoder, which leads to the glow of the LED 25, which corresponds to an emergency overvoltage in emergency network. In this case, the first and second analog switches 15.16 are in a closed state and do not pass signals from the outputs of the first and second inverters 4, 26 to the input of the first ideal rectifier 27.

When the primary winding of the transformer I is disconnected from the network, zero potential is held at the non-inverting inputs of the comparators 7,8,9, therefore, the code 000 is supplied to the inputs of the decoder 14. At the second, fourth and seventh outputs of the decoder 14 there is a low potential. As a result, the first and second analog

the keys 15.16 are closed and all three LEDs 23.24.25 are off

The block of analog-to-digital conversion B forms from nullorgan Z, 39, shapers 34,35,40,41, element AND-NOT 33, ideal rectifiers 27, 38, adders 28, 36, voltage reference sources 29,37, amplitude peak detector 30 , a ballast resistor 31, an analog switch 32, a clock 43, an analog-to-digital converter 42, an output register 44, the operation of the analog-to-digital conversion unit B consists in highlighting the difference between the current envelope value of the actual value of the mains voltage and the nominal value voltage of this network, with the subsequent conversion of this difference in digital qd every half-period of the investigated voltage.

The operation of the analog-to-digital conversion unit proceeds as follows.

The mains voltage under investigation is supplied to the primary winding of a step-down transformer I, having a transformation coefficient Kli. The voltage from the output of the secondary winding, the second end of which is connected to the device common bus, is fed to the input of the low-pass filter 2, From the output of the low-pass filter 2, the filtered signal is fed to the input of the unit automatic adjustment of the measuring range A-ii of the first zero-organ 3, The voltage from the output of the automatic adjustment of the measuring range A is applied to the input of the first ideal rectifier 27, The rectified voltage from the output of the first ideal rectifier 27 is supplied to the first input of the first adder 28, the second input of which is supplied with the voltage from the output of the first source of the reference voltage 29 having a negative potential. As a result, the output of the dry-out feeder 28 forms a partially filtered into the negative zone, filtered and a rectified voltage that is supplied to the input of the amplitude peak detector 30,

At time io, when the test voltage passes through the low-frequency filter output through zero, the first zero “organ 3 is triggered and generates a positive voltage pulse at its output along the leading edge of which the first driver 34 starts and generates a negative voltage pulse of in duration at the inverse output. (I)

r-very soon EXIT of the shaper 34 passes inverting, through the element Y-HB 33, and enters the inverse input of the third shaper, as well as the control input of the third analog key 32. As a result, the third analog key 32 is opened for the time I: J and discharges through ballast resistor 31, the voltage that was memorized in the previous half time by the amplitude peak detector 30. Next, at time t, at the end of the voltage pulse of the driver 34, the third analog switch 32 closes and the amplitude peak detector 30 starts to work out the maximum value of the voltage of the current half-cycle of voltage, and on the trailing edge of the pulse at the output of the AND-NOT 33 element, it starts at the time T, -0.65T, the third driver 40. The voltage from the output of the amplitude peak detector 30 is supplied to the first input of the second adder 36, the second input of which receives voltage from the output of the second negative reference voltage source 37. As a result, at time 2. corresponding to the maximum voltage value of the current half-cycle, the output of the second adder 3 6, a voltage potential is formed corresponding to the difference between the value of the current effective voltage of the network and the value of the nominal value of the network voltage. The voltage from the output of the second adder 36 goes to the input of the second ideal rectifier 38 and to the input of the second zero-organ 39. The rectified voltage from the output of the second ideal rectifier 38 goes to the information input of the analog-to-digital converter 42. At time t, the positive pulse at the output of the third of the former 40th bottom edge of this pulse, the fourth former 41 is activated, which generates a positive voltage pulse of duration T- - 7 3 40 (3) / g “k At the end of the conversion, at the moment d time bc, a code is generated at the information outputs of the analog-to-digital converter 42, arriving at the lower bits of the information ode of the output register 44, while a significant signal from the output of the second null organ 39 is received at the senior information of this input. After generating the code on the information the outputs of the analog-to-digital converter 42, at time tj, a positive voltage pulse appears on the ready output of the analog-to-digital converter 42, on the leading edge of which information is recorded Migration to the output register 44, Then at time tg the pulse ends from the output of the first zero-organ 3, The second driver 35 starts at the trailing edge of this pulse, the pulse from the inverse output of this driver passes inverting through the AND-NOT 33 element and goes to the control input the third analog key 32, as well as the inverse input of the third driver 40. Further, the device operates as described above in the time interval to-te, etc. Figure 2 shows the well-known circuit 4 of an ideal rectifier, consisting of operational amplifiers 45.46, diodes 47.48 and resistors 49.30.51.52.53, where a is the input of an ideal rectifier, b is the output of an ideal rectifier. .3 shows the well-known circuit p of the amplitude peak detector, consisting of operational amplifiers 54.55, resistor 56, diodes 57.58, capacitor 59, where c is the input of the amplitude peak detector, g is the output of the amplitude peak detector, and d is the control input of the amplitude peak detector. The converter uses an analog-to-digital converter of a parallel type with a serial approximation. The output register 44 is a matching element with external devices and serves to fix the code, the use of the first adder allows: firstly, to reduce the instability of the output voltage of the amplitude peak detector (and, accordingly, the relative error of the amplitude peak detector) arising due to the inevitable presence of power supply ripples device and the smallest possible input voltage of the amplitude peak detector, and also to the maximum extent taken into account in the output code inverter input voltage changes. .3

The advantages of the proposed utility model by comparison with the known ones are: a) increased ease of use due to the automatic adjustment of the measuring range with indication and the presence of a digital signal code at the output of the converter; b) increasing the accuracy of signal processing by introducing an additional first adder and eliminating the need to identify the output signals of the two channels of the converter c) simplifying the circuit by eliminating the second amplitude peak detector, inverter, and three analog switches. Thus, the proposed device is functionally complete and can be used in various information and measuring systems used in the energy sector. Currently, a device is made and introduced, which includes the proposed utility model.

Sources of information used in compiling

1. Ermakov V, $., Terebaev VV, High-speed AC to DC Converter, - Izv, USSR Universities, Ser, Electromechanics, I98I, No. 8, p. 934-935,

2.A, s, USSR No. 1033977.cl. & OIR 19 / 22,1982 ,.

3. Ermakov V. $ ,, Hamelis E, I, High-speed converter of alternating voltage to constant, "IZV, Universities of the USSR, Ser, Electromechanics, 1989, No. 11, p. 64" 67,

4, L. Falkenberry, The use of operational amplifiers and linear integrated circuits, M ,, Mir, 1985, p.241-242,

5. Horowitz P., Hill W. The art of circuitry - t, 1, M., Mir, 1984, p. 598, directors

yoo

&.

description of the application: O.A.Drozdov

Claims (1)

A high-speed AC / DC converter in a digital code containing a step-down transformer, the primary windings of which are connected to the input terminals of the converter, the first terminal of the secondary winding of the transformer is connected to the common converter bus, and the second terminal of the winding is connected to the input of the low-pass filter, the output of which is connected to the input of the first input inverter and the input of the first zero-organ, the output of which is connected to the direct and inverse inputs of the first and second formers, the first and second analog to light, an amplitude peak detector, the control input of which through the first ballast resistor is connected to the information input of the third analog switch, the output of which is connected to the common bus of the converter, the first adder, the second input of which is connected to the output of the first reference voltage source, characterized in that it additionally input register, analog-to-digital converter, clock generator, second zero-organ, first and second ideal rectifiers, second inverter, second adder, second are introduced reference voltage source, third and fourth drivers, AND-NOT element, first, second and third LEDs, second, third and fourth ballast resistors, first, second, third elements NOT with open collector outputs, decoder, first, second, third comparators, resistive divider, smoothing capacitor, diode, the anode of which is connected to the output of the low-pass filter, and the cathode is connected to the combined non-inverting inputs of the comparators and through the smoothing capacitor with a common converter bus, inverting the moves of the comparators are connected to the outputs of the resistive divider, the output of the first resistor of which is connected to the bus of the converter power supply, and the output of the last resistor is connected to the common bus of the converter, the outputs of the comparators are connected to the inputs of the decoder, the outputs of which are connected respectively to the inputs of the elements NOT, the open collector outputs of which ballast resistors and LEDs connected in series are connected to the converter power supply bus, the output of the first inverter is connected to inform the input of the second analog switch and the input of the second inverter, the output of which is connected to the information input of the first analog switch, the output of which is combined with the output of the second analog switch and connected to the input of the first ideal rectifier, the output of which is connected to the first input of the first adder, the output of which is connected to the information the input of the peak amplitude detector, the output of which is connected to the first input of the second adder, the second input of which is connected to the output of the second reference voltage source, you the course of the second adder is connected to the inputs of the second zero-organ and the second ideal rectifier, the output of which is connected to the information input of an analog-to-digital converter, the information output of which is connected to the group of the least significant bits of the information input of the output register, the highest bit of which is connected to the output of the second zero-organ, the first and second outputs of the decoder are connected respectively to the control inputs of the first and second analog keys, the inverse outputs of the first and second formers are connected to the inputs The elements are AND-NOT, the output of which is connected to the control input of the third analog switch and with the inverse input of the third driver, the direct output of which is connected to the inverse input of the fourth driver, the direct output of which is connected to the trigger input of the analog-to-digital converter, the clock input of which is connected to the output a clock pulse generator, and the ready output is connected to the recording input of the output register, the information output of which is the information output of the converter.