RU14707U1 - PARALLEL COMPRESSION-DECOMPRESSION PROCESSOR - Google Patents

Abstract

1. Parallel compression and decompression processor containing an arithmetic logic device, random access memory, control unit, data registers, exchange registers, characterized in that the random access memory is made in the form of a multi-bit shift register with input and output logic, and an additional block is introduced piecewise continuous Gaussian pulse value codes containing an address counter. 2. The processor according to claim 1, characterized in that the unit for generating codes of values of a piecewise-continuous Gaussian pulse contains a read-only memory device for storing in a tabular form codes of values of piecewise-continuous Gaussian pulse controlled by an address counter by sequentially selecting values from a read-only memory device. . The processor according to claim 1, characterized in that the unit for generating codes of values of a piecewise-continuous Gaussian pulse contains a processor for calculating the amplitudes of this function, working in parallel with the main processor and controlled by an address counter.

Description

PARALLEL COMPRESSION AND DECOMPRESSION PROCESSOR

The utility model relates to computer technology and, in particular, can be used to compress binary code in devices for processing, storage, reception, transmission and recording of information, as well as in information systems, for example, in communication and multimedia systems.

There are specialized processors for compressing data with loss of information: natfimer, video compression (laser discs, multimedia). Having studied the specifics of the transmitted information, they allow you to eliminate the relative (subjective) redundancy of information. They use algorithms to achieve a compression ratio of 400 - 4000 percent). However, such processors are not considered in this application, since the task posed does not allow information loss.

As a prototype of a compression and decompression processor, a processor is selected that contains an arithmetic logic device (ALU), random access memory (RAM), control unit (CU), data registers (RD) and exchange registers (RO) (US Patent No. 5,126,739 IPC NOZM 7/42 publ. September 17, 1992).

The disadvantage of the prototype processor is the proportional relationship of the width of the used 11 spectral band with the transmission rate (compression ratio) of the data, as a result of which when transferring more data

М1СИ НОЗМ7 / 30, G 08 С 19/28

it is necessary to significantly expand the spectrum of the signal passing through the channel, and this in turn requires special communication lines or leads to loss of information on ordinary communication lines.

The objective of this utility model is to significantly increase (not less than 100-500 times) the degree of compression of information transmitted in parallel or sequentially with binary code, at a high processing speed (compression) and preserve the information content of the data in a noisy path, increase the encoding-decoding rate signal without significant carrier frequency.

The problem is solved in that in a parallel compression and decompression processor containing an arithmetic logic device, random access memory, control unit, data registers, exchange, according to the invention, the random access memory is made in the form of a multi-bit shift register with input and output logic, in addition, additionally a unit for generating codes of values of a piecewise-continuous Gaussian pulse containing an address counter has been introduced.

The problem is also solved by the fact that the unit for generating codes of values of a piecewise-continuous Gaussian pulse contains a read-only memory for storing tabular codes of values of a piecewise-continuous Gaussian pulse controlled by an address counter by sequentially selecting values from a permanent storage device.

The problem is also solved by the fact that the unit for generating codes of values of a piecewise-continuous Gaussian pulse contains a processor for calculating the amplitudes of this function, working in parallel with the main processor and controlled by the address counter.

To illustrate the model of FIG. 1 shows a block diagram of a device for data compression. In FIG. 2 is a block diagram of a compression and decompression processor. In FIG. 3 shows the structure of a device for decompressing data. In FIG. 4 shows the structure of the drive unit. In FIG. 5, 6 show the structure of the associative storage device AZU1 and the code analysis unit, respectively. In FIG. 7 shows a block for generating codes of values of a piecewise-continuous Gaussian pulse using a read-only memory; in FIG. 8 is the same, but using a specialized processor to calculate the values of a piecewise-continuous Gaussian pulse. In FIG. 9 is a graph of a piecewise-continuous aperiodic function, a portion of which is used as polynomial to convert the original binary code. In FIG. 10 shows a portion of a polynomial function used to convert a binary code.

The compression unit 1 (Fig. 1) contains the actual compression decompression processor (KDN) 2 and a digital-to-analog converter (DAC) Z.

Compression and decompression processor KDP (fng. 2) with memory of random access memory (RAM) 4 to the input of which an uncompressed serial or parallel code is supplied, a unit for generating values of a piecewise-continuous Gaussian pulse (BFZ) 5 to output codes of values used by the polynomial function, arithmeticological device (ALU) 6 for the implementation of operations of algebraic summation and multiplication of uncommitted code and codes of values of the polynomial function used, as well as to control (BU) 7. RAM 4, in turn, consists of input logic 8, multi-bit shift register 9 and output logic 10. ALU 6 contains a block of multipliers 11, a summing block 12 and an output register 13.

The decompression unit 14 (Fig. 3) contains the actual compression and decompression processor 15, a similar KDP 2, an analog-to-digital converter (ADC) 16 for converting an analog signal to a compression code, an arithmetic device (AU) 17 for calculating the difference between the compressed code and the remaining part of the decompressed code, the first associative memory device (AZU 1) 18, which stores decoding codes in the form of tables, a drive unit 19 for summing the decoded values of the source code, and an analysis unit Ode 20.

The drive unit 19 (Fig. 4) consists of w-sections of binary counters 21 and t-decryptors 22.

The first associative storage device AZU 18 (Fig. 5) consists of a register of associative features 23, a storage device 24, information registers 25.

The code analysis unit (LHC) 20 (Fig. 6) consists of a second associative

memory device АЗУ2 26, constructed similarly to АЗУ1 18, which in turn consists of a register of associative features 27, memory device 28, information registers 29. Additionally, the LHC 20 contains a threshold element 30 for finally determining the received bit or byte of a serial or parallel code.

The unit for generating values of a piecewise-continuous Gaussian pulse (BFZ) 5 consists of a ROM 31 (Fig. 7) or a specialized processor 32 (Fig. 8) and an address counter (CA) 33 for polling a ROM 31 or processor 32 and issuing the next value of the piecewise unbroken gaussian impulse.

The device operates as follows. The source binary code is bitwise or byte-wise through input 1 (Bx1) or input 2 (Bx2) and is stored in RAM 4 and recorded in it with an interval of time T. During the next period T, each bit or byte is connected in turn through the output logic 10 of RAM 4 to addresses of the same name of the forming unit for forming the value of BFZ 5. The address of BFZ 5 is enumerated by a built-in address counter CA 33, which is started by the SCHITATB command from BU 7. Since this is a binary code, then during each period T at the enable input Bx1 ROM 31 will be w-times present create logical O or 1, depending on

the next bit value or byte of the source code. In accordance with this, the code value of a piecewise-continuous aperiodic function of the same name with an input bit or byte will be read from BFZ 5. These values in each T / pact alternately go to the first input of ALU 6, the second input of which serves the same values of bits or bytes of the uncompressed code from the output of RAM 4. ALU 6, in accordance with the algorithm of work, performs parallel bitwise or byte-wise multiplication of the source code by the corresponding values given function followed by algebraic summation of the obtained values. Since the piecewise-continuous Gaussian pulse is alternating in nature, the output of the ALU output values of the compressed codes will also be alternating. The indicated values are fed to the input of the DAC 3, which converts the digital code into analog with a smoothing period of no more than the period of the original binary code. As a result, at the output of the DAC 3 there will be a fluctuation in shape close to harmonic, moreover, one period of such an oscillation carries information about 100-500 bits or bits of the original uncompressed code. Further, the specified signal enters the recording or exchange channel rformation. The parameters of the selected piecewise continuous aperiodic function make it possible to increase the throughput of the used channel (path) to 500 bit / s per 1 Hz of the spectrum width. Thus, the standard frequency band used for regular telephone channels with a width of 3 thousand hertz allows transmitting about 1.5 X 10 bits per second. 6

The inverse conversion of the compressed signal to the source code is as follows. From the channel of reproduction or exchange of information, the analog signal is fed to the input of the ADC 16, which converts the analog signal into a compressed code. The specified code is fed to the first input of AU 17, to the second input of which an inverted code is supplied from the output of KDP 15, as a result of which at the output of AU 17 there will be a code value from the polynomial section of the function. Since the length of the section is m-cycles, and m is much smaller than ", and the compression is performed sequentially (bitwise or byte-by-bit), then at the output of AC 17 in each period T there will be one of 2 values of the compressed code. Based on this algorithm, an associative AZU1 18 is constructed, which, when one of the 2 code values arrives at the input of the AC 17 at its input, the information registers 25 will have decompressed values of the source binary code at its output. Since the transmission (recording) and reception (reproduction) of information occurs with an error probability different from nu.11ya, the code value received from the recording (exchange) channel will differ from the compressed one. For this purpose, the code is read in AZU1 18 using the register of associative features 23 according to the principle CLOSE TO THE WHOLE NUMBER. From the output of АЗУ1 18, each decoded value of a bit or byte goes to input БЫ 19, which consists of AI sections of binary counters 21 and W-decoders 22. In the case of a sequential binary code, each value of the discharge of the code from the output of АЗУ1 18 is added only to the first counter of the section counters 21 and shifts with summation from counter to counter in

during w-cycles: in case of compression of the parallel code (byte-by-bit), the binary code from each output of the RAM 1 18 is bitwise added to the corresponding counters of each section of the counters 21. The decoder 22 in each section of the counters controls the summation of logical 1 in each counter for cycles, as a result of which after t-cycles in each counter of the leftmost section of the counters the number of logical 1s equal to ttakts will accumulate. The contents of the counter summing logical O must be zero. If there is dispersion of the noise in the recording-reproduction channels (or communication channels), the actual contents of the counters will differ from the expected one. For example, if the value of one of the possible bytes being compressed is 164, its binary representation will be 10100100. For example, if the length of the polynomial function section is 10, the contents of each counter by the end of the definition will be: 1010-0000-1010-0000-0000-1010-0000- 0000 (in binary representation). АЗУ2 26 in each t-cycle analyzes the contents of each counter and using the threshold element 30 determines 11 the value of each bit in the decoded byte according to the following rule: if the contents of the counter are greater than or equal to (t / 2) +}, then the value of the bit in byte is equal to otherwise, the discharge value is 0.

From the output of the analysis unit of the LHC code 20, the value of the bit or byte goes to the output of the decompression unit 14 and at the same time to the input of the KDP 15. The structure of the KDP 15 of the decompression unit 14 is completely identical to the KDP 2 of the compression unit 1 and differs in the absence of RAM units in the BFZ and the number of elements equal to t .

The inventive device can be implemented by manufacturing a specialized processor that implements the described algorithm and using all components of the invention when transmitting data in various industrial and other systems.

Thus, the use of the proposed utility model allows us to achieve the task, namely, to significantly increase the degree of compression - decompression of data while maintaining the reliability and productivity of the process, and the reliability of data transmission remains high when using public telephone channels.

Patent Attorney of the Republic of Belarus 1, per. No. 0020

A. E. Svidersky

Claims (3)

1. Parallel compression and decompression processor containing an arithmetic logic device, random access memory, control unit, data registers, exchange registers, characterized in that the random access memory is made in the form of a multi-bit shift register with input and output logic, and an additional block is introduced piecewise continuous Gaussian pulse value codes containing an address counter.  2. The processor according to claim 1, characterized in that the unit for generating codes of values of a piecewise-continuous Gaussian pulse contains a read-only memory for storing tabular codes of values of piecewise-continuous Gaussian pulse controlled by an address counter by sequentially selecting values from a read-only memory . 3. The processor according to claim 1, characterized in that the unit for generating codes of values of a piecewise-continuous Gaussian pulse contains a processor for calculating the amplitudes of this function, working in parallel with the main processor and controlled by an address counter.