RU130427U1 - AUTOMATED PLANNING SYSTEM FOR TRANSPORTATION OF TROOPS (CARGOES) BY SEA (RIVER) TRANSPORT - Google Patents

Abstract

An automated planning system for transporting troops (cargo) by sea (river) transport, containing a data array selection block for solving design problems, the first and second information inputs of which are the first and second information inputs of the system, and the synchronizing input is the first synchronizing input of the system, while the first the information input of the system is designed to receive the identifier code of the planning time period, the second information input of the system is designed to receive the identifier code a torus of a group of troop (cargo) transportation flights, and the first synchronizing input of the system is designed to receive synchronizing pulses of entering input codes into a data array selection block for solving computational problems, a data storage address modification block, whose information inputs are connected to the corresponding information outputs of the data array selection block to solve design problems, the synchronizing inputs of the data storage address modification block are connected to the corresponding synchronizing outputs of the block and data arrays for solving computational problems, while the first information output of the data storage address modification block is connected to the first information input of the address signal integration unit, the first synchronizing input of which is connected to the third synchronizing output of the data arrays selection unit for solving computational problems, and the output of the integration unit address signals is the address output of the system, a data selection unit for solving computational problems, the first information input of which is the third information

Description

The utility model relates to computer technology, in particular, to an automated planning system for transporting troops (goods) by sea (river) transport.

Modern military conflicts are characterized by transience, selectivity and a high degree of destruction of objects, the speed of maneuver by troops (forces) and fire, the use of various mobile groupings of troops (forces) [1]. The main tasks of reforming the Armed Forces of the Russian Federation in modern conditions include improving the automated system of command and control and increasing the mobility of troops.

At present, there is a steady tendency towards an increase in the importance and role of military maritime transport in the context of the preparation and conduct of highly maneuverable military operations.

In the threatened period and with the outbreak of hostilities, the need for naval transportation arises: during regrouping and during the strategic deployment of troops; in the preparation of subsequent operations; strengthening or evacuation of coastal groupings of troops and other cases.

In peacetime, sea transport provides: transportation of people, weapons and equipment during the redeployment of troops, their withdrawal from other countries in accordance with the decision of the top military-political leadership; the daily needs of troops and fleet forces deployed in coastal and island territories; transportation of troops, weapons and equipment for participation in peacekeeping and other international actions in accordance with treaties and obligations adopted by the country, as well as for the interests of the country, friendly countries and citizens in remote regions.

The positive properties of maritime transport include: high (compared to railway) speed of transportation (up to 30 knots - about 55 kilometers per hour); unconnectedness of the direction of movement of the ships, which allows for the transportation of troops in any direction, and then to land troops at any point on the coast; compact transportation due to the large capacity and carrying capacity of sea transport vessels (one medium-tonnage vessel with a capacity of three to four military train levels, and with a load capacity of five to six), the ability to use anti-aircraft fire weapons of ships transported, etc.

Along with the positive properties of maritime transport from a military point of view, there are also disadvantages that should be taken into account when preparing and conducting military maritime transport. These include: a high degree of risk of disrupting transportation when exposed to the enemy on ships carrying troops and equipment; the dependence of traffic on the time of year on some seas and inland routes; insufficient accuracy in time of movement and arrival of troops and cargo during military maritime transport; susceptibility of sea-going vessels to rolling during stormy weather, which painfully affects the well-being of the troops being transported;

low rate of loading and unloading operations on ships with the classical method of loading and unloading.

Military shipping, being an extremely complex, capacious and responsible event, requires the involvement of diverse groups of fleet forces, a large number of transport and unloading means, and the strict implementation of temporary parameters in the face of active opposition by the enemy.

Figure 1 shows the composition of the blocks of the proposed complex tasks. Figure 2 and figure 3 shows the distribution of military

Known systems that could be used to solve the problem (1, 2).

The first of the known systems contains data reception and storage units connected to control and data processing units, search and selection units connected to data storage and display units, the synchronizing inputs of which are connected to the outputs of the control unit (1).

A significant drawback of this system is the impossibility of solving the problem of updating data stored in memory in the form of relevant documents at the same time as solving the problem of delivering the contents of these documents to users in real time.

Another system is known, comprising data receiving units whose outputs are connected to a memory unit and to a data processing unit, a time interval selection unit whose outputs are connected to a data receiving unit, to a user request receiving unit and to a memory unit and to a data processing unit, the outputs of which are connected to one of the inputs of the switching unit of the data output channels, the other inputs of which are connected to the selection of time intervals, and the outputs are the outputs of the system (2).

The last of the above technical solutions is closest to the described.

Its disadvantage is the low speed of the system, due to the fact that the search for the requested data is carried out throughout the database system, which leads to unreasonable loss of time to search for the required information and its analysis.

The purpose of the utility model is to increase the speed of the system by excluding the search for the requested data in the entire volume of the system database and selecting data only by identifiers of the flight group and time period.

This goal is achieved by the fact that in a known system containing a block for selecting data arrays for solving computational problems, the first and second information inputs of which are the first and second information inputs of the system, and the synchronizing input is the first synchronizing input of the system, while the first information input of the system is intended to receive the identifier code of the planning time period, the second information input of the system is designed to receive the identifier code of the group of flights of troop transport cargo), and the first synchronizing input of the system is designed to receive synchronizing pulses of entering the input codes into the data array selection block for solving computational problems, the data storage address modification block, the information inputs of which are connected to the corresponding information outputs of the data array selection block for solving computational problems, the inputs of the data storage address modification block are connected to the corresponding synchronizing outputs of the data array selection block to solve the calculation In this case, the first information output of the data warehouse address modification block is connected to the first information input of the address signal integration unit, the first synchronizing input of which is connected to the third synchronization output of the data array selection block for solving computational problems, and the output of the address signal integration block is address system output, a data selection unit for solving computational problems, the first information input of which is the third information input of the system, is intended the second information input of the data selection block for solving computational problems is the fourth information input of the system intended for receiving data from the server data storage, one synchronizing input of the data selection block for solving computational problems is the third synchronizing input of the system for entering the code of the data selection criterion in the data selection block for solving computational problems, and another synchronizing input of the data selection block for For solving computational problems, it is the fourth synchronizing input of the system intended for entering data storage data into the data selection block for solving computational problems, while the information output of the data selection block for solving computational problems is an information output of the system, a block for specifying features of computational problems, the information input of which it is the fifth information input of the system intended for receiving the identifier of the selected data array, and the synchronizing input of the job block is recognized s of computational tasks is the fifth synchronizing input of the system, intended for receiving synchronizing signals of entering the identifier of the selected data array into the unit for specifying the characteristics of the computational tasks, the integration unit of read signals, the first input of which is connected to the third synchronizing output of the data array selection unit for solving computational problems, while one output of the read signal integration unit is the first synchronizing output of the system designed to provide read signals to One of the first interrupt channel of the data warehouse server, and the other output of the read signal integration block is connected to the installation input of the address signal integration block, a record signal integration block, the first output of which is the second synchronizing output of the system, designed to provide write signals to the input of the second channel of the storage server interrupt data, and a unit for integrating reset signals, the output of which is the signal output of the system, designed to signal the end of the separation procedure m data assists, characterized in that the system comprises a data sampling interval identification block, the information input of which is connected to another information output of the data storage address modification block, the counting input of the data sampling interval identification block is connected to the second output of the recording signal integration block, and the synchronization input of the identification block of sampling intervals of data is connected to the third output of the unit for integrating recording signals, while one output of the identification block of intervals of sampling data by it is connected to the counting input of the data warehouse address modification block, to the second synchronizing input of the read signal integration unit, and to the second synchronizing input of the address signal integration unit, and the other output of the data sampling interval identification unit is connected to the first input of the reset signal integration unit, the first signal generating unit writing and reading data from the data warehouse, the first input of which is connected to the first output of the marketing data selection block, the second input of the first Data recording and reading data warehouse is connected to the fourth output of the recording signal integration unit, and the third input of the first data signal writing and reading unit of the data storage is connected to the first output of the design task attribute block, while the information output of the first recording and reading signal generating unit data warehouse is connected to the second information input of the address signal integration unit, the first clock output of the first signal generation unit and reading data from the data warehouse is connected to the third synchronizing input of the read signal integration unit, the second and third synchronizing outputs of the first recording and reading data generating unit are connected to the first and second synchronizing inputs of the recording signal integration unit, respectively, and the fourth synchronizing output of the first generating unit data recording and reading signals of the data warehouse is connected to the second input of the reset signal integration unit, the second block of forms signal recording and reading data of the data warehouse, the first input of which is connected to the second output of the marketing data selection block, the second input is connected to the fourth output of the recording signal integration unit, and the third input is connected to the second output of the task unit for specifying computational tasks, while the information output of the second the unit for generating signals for writing and reading data from the data warehouse is connected to the third information input of the address signal integration unit, the first synchronizing output of the second block the formation of the signals for writing and reading data from the data warehouse is connected to the fourth synchronizing input of the unit for integrating read signals, the second and third synchronizing outputs of the second block for generating the signals for writing and reading data from the data warehouse are connected to the third and fourth synchronizing inputs of the unit for integrating recording signals, respectively, and the fourth synchronizing output the second unit for generating signals for writing and reading data from the data warehouse is connected to the third input of the integration unit reset signals, the third block of generating signals for writing and reading data from the data warehouse, the first input of which is connected to the third output of the data selection block for solving computational problems, the second input is connected to the fifth output of the integration block of recording signals, and the third input is connected to the third output of the characteristic setting block computational tasks, while the information output of the third block of generating signals for writing and reading data from the data warehouse is connected to the fourth information input of the address signal integration unit ov, the first synchronizing output of the third unit for generating signals for writing and reading data of the data warehouse is connected to the fifth synchronizing input for the unit for integrating read signals, the second and third synchronizing outputs for the third block for generating signals for writing and reading data for the data warehouse are connected to the fifth and sixth synchronizing inputs of the unit for integrating signals recordings, respectively, and the fourth synchronizing output of the third unit for generating recording and reading data storage data connected to the fourth input of the integration block of the reset signals, the fourth block of generating signals for writing and reading data of the data warehouse, the first input of which is connected to the fourth output of the block for selecting data of calculation tasks, the second input of the fourth block of generating signals for writing and reading data of the data warehouse is connected to the fifth output of the block integration of the recording signals, and the third input of the fourth block of the formation of the recording signals and reading data of the data warehouse is connected to the fourth output of the task unit in computational tasks, while the information output of the fourth block of generating signals for writing and reading data of the data warehouse is connected to the fifth information input of the unit for integrating address signals, the first synchronizing output of the fourth block for generating signals for writing and reading data of the data warehouse is connected to the sixth synchronizing input of the block of integration of read signals , the second and third synchronizing outputs of the fourth block of the formation of signals for writing and reading data from the data warehouse They are connected to the seventh and eighth synchronizing inputs of the recording signal integration unit, respectively, and the fourth synchronizing output of the fourth data recording and reading signal generating unit is connected to the fifth input of the reset signal integration unit, the output of which is connected to the counting input of the marketing data selection unit, the first generating unit data warehouse data recording signals, one input of which is connected to the fifth output of the block of data selection of computational problems, and the other input of the first block is formed The data storage data recording signals are connected to the output of the reset signal integration unit, the information output of the first data storage data recording signal generating unit is connected to the sixth information input of the address signals integration unit, and the second and third synchronizing outputs of the first data storage data recording signal generating unit are connected to the ninth and tenth synchronizing inputs of the recording signal integration unit, respectively, and the second storage data recording signal generating unit data, one input of which is connected to the sixth output of the block of data selection of the calculation tasks, and the other input of the second block of generating signals for recording data of the data warehouse is connected to the output of the integration unit of the reset signals, the information output of the second block of generating signals for recording data of the data warehouse is connected to the seventh information input of the block integration of address signals, and the second and third synchronizing outputs of the first signal generation data recording unit of the data warehouse are connected to the eleventh and twelfth to the fifth synchronizing inputs of the recording signal integration unit, respectively, while the seventh synchronizing input of the read signal integration unit is connected to the fifth synchronizing input of the system.

The essence of the utility model is illustrated by drawings, in which Fig. 1 shows a structural diagram of a system, Fig. 2 shows an example of a specific structural embodiment of a block for selecting data arrays for solving computational problems, Fig. 3 is an example of a specific structural embodiment of a block for modifying addresses of a data warehouse, figure 4 is an example of a specific structural embodiment of the unit for identifying intervals of data sampling, figure 5 is an example of a specific structural embodiment of a unit for integrating read signals, figure 6 is an example to FIG. 7 — an example of a specific constructive implementation of a block for setting the signs of computational tasks, FIG. 8 — an example of a specific constructive execution of blocks for generating signals for writing and reading data of a data warehouse, FIG. 9 — an example of a specific constructive of execution units for generating signals for recording data of the data warehouse, FIG. 10 is an example of a specific structural embodiment of a unit for integrating recording signals, FIG. 11 is an example of a specific second structural embodiment of the unit integration address signals at 12 - example of a specific structural embodiment of the unit integration reset signal.

The system (Fig. 1) contains a block 1 for selecting data arrays for solving computational problems, a block 2 for modifying the addresses of the data warehouse, a block 3 for identifying the intervals of data sampling, a block 4 for integrating read signals, a block 5 for selecting data for the computational problems, a block 6 for specifying characteristics of the computational problems , blocks 7-10 generating signals for writing and reading data from the data warehouse, blocks 11, 12 for generating signals for writing data to the data warehouse, block 13 for integrating recording signals, block 14 for integrating address signals, block 15 for integrating reset signals.

Figure 1 shows the first 25, second 26, third 27, fourth 28 and fifth 29 information inputs of the system, the first 30, second 31, third 32 and fourth 33 synchronizing inputs of the system, information 35 and address 36 system outputs, and the first 37, the second 38 and third 39 synchronizing outputs of the system.

Block 1 (figure 2) of the selection of data arrays for solving computational problems contains registers 40-41, decoders 42, 43, memory blocks 44, 45, made in the form of read-only memory, elements 46-51 And, elements 52-55 delay. The drawing also shows the inputs 25, 26, 30 and outputs 56-61 of the block.

Block 2 (FIG. 3) of the data warehouse address modification contains registers 16.17, an adder 18 and a counter 19. The first 230 and second 231 information inputs, the first 233 and second 234 clock inputs and the counting input 235, as well as the first 236 are shown in the drawing and second 237 information outputs.

Block 3 (Fig. 4) for identifying sampling intervals contains a counter 20 and a comparator 21. The drawing shows information 240, counting 241 and synchronizing 242 inputs, as well as the first 211 and second 212 outputs.

Block 4 (figure 5) integration of read signals contains elements 64, 65 OR, element 66 delay. The drawing also shows inputs 67-73 and outputs 37, 74.

Block 5 (Fig.6) selection of the data of the calculation tasks contains registers 78, 79, decoders 80, 81, counters 82, comparator 83, elements 84-93 AND, elements 94, 95 AND groups of elements, elements 96, 97 OR, elements 98 OR group, delay element 99. The drawing also shows information inputs 27.28, synchronizing inputs 31, 32, counting input 104, as well as synchronizing outputs 105-110, and information output 35.

Block 6 (Fig. 7) for setting the characteristics of computational tasks contains a register 22 and a decoder 23. The drawing shows information 29 and synchronizing 33 inputs, as well as outputs 213-216.

Blocks 7-10 (Fig) of the formation of signals for writing and reading the data warehouse contain a block 115 of memory, made in the form of read-only memory, register 116, adder 117, counters 118, 119, comparator 120, triggers 121, 122, elements 123- 125 AND, elements 126, 127 AND groups of elements, element 128 OR, elements 129 OR groups, elements 130-133 delays. The drawing also shows inputs 135-137 and outputs 138-142.

Blocks 11, 12 (Fig. 9) of generating data storage recording signals comprise a memory unit 150 made in the form of read-only memory, register 151, adder 152, counter 153, triggers 154, 155, elements 156-157 I, elements 158 I groups elements, OR element 159, delay elements 160-163. The drawing also shows inputs 164-165 and outputs 166-168.

Block 13 (figure 10) integration of the recording signals contains elements 170-174 OR. The drawing also shows inputs 175-186 and outputs 38 and 187-190.

Block 14 (11) integration of the address signals contains a trigger 191, elements 192 of the group and elements 193 OR groups. The drawing also shows inputs 194-200 and output 36.

Block 15 integration of the reset signals (Fig.9) contains the element 205 OR. The drawing also shows inputs 206-210 and output 39.

The methodology for planning the transportation of troops (forces) by sea (river) transport includes the following operations:

- calculation of the total area of units of equipment (ET) of military units (EF);

- calculation of the need for vehicles (TS), the number of flights at a certain pace of transportation;

- determination of the number of boarding points and boarding points.

- the distribution of vehicles at points of embarkation and points of disembarkation of a flight;

- development of a graphic transportation plan;

- the distribution of military units on the vehicles of the flight.

- development of a transportation schedule, a detailed plan, ship cargo plans, loading support plans. When planning the transportation of troops by sea in peacetime and wartime, the following initial data are used:

- conclusions from an assessment of the operational, rear and transport situation;

- the composition of the transported troops, their deployment and concentration;

- areas of loading and unloading;

- terms of readiness for transportation;

- the sequence and timing of the transportation;

-transport characteristic of equipment in service with the troops;

- norms of usable space required to accommodate equipment and personnel on ships;

- capabilities of the working core of the fleet;

- the capacity of the areas of loading and unloading.

The planning results are displayed in the output documents, including loading support plans, a graphic transportation plan, a transportation schedule, a detailed plan for troop transportation, cargo plans of ships, and a plan for organizing military transportation in a defensive (counter-offensive) operation, containing: a work map, a graphic plan for troop transportation, volumetric plan of military traffic.

The system operates as follows.

A set of hierarchically interconnected indicators limited by target levels of computational tasks together with initial indicators form an information model of a multi-channel filter. The structure of the algorithm is a tree graph, where at each level of its branching corresponding levels of discrimination (selection criteria) are set.

At the first level of analysis, one of the criteria is selected as a criterion, for example, criterion D - average load per flight. Using this criterion, two new arrays are formed at the first level: with the worst and best values of this criterion, respectively. Thus, the first level of analysis allows you to automatically highlight flights with positive and negative loading dynamics.

At the second level of analysis, another of the possible criteria is selected, for example, the criterion of the load factor -% occupancy of the vehicle area. At this level, two new arrays with low and high load seats are formed from flights with a high load value, respectively.

At the third level of analysis, one of the possible criteria is also selected, for example, for protection against weapons and the corresponding data arrays are formed.

To solve the tasks, the operator at his workstation generates various initial signs of the design tasks.

Firstly, a codogram of a request for an array of data selected for analysis is formed. The codogram has the following structure:

THE CODE THE CODE identifier of the time period to which the array of indicators selected for analysis belongs identifier (flight groups)

Secondly, the identifier of the criterion is set, which he selects for analysis at the first level, and its quantitative value.

For an example, criterion D is selected as such a feature - the average vehicle load per flight. The identifier of the criterion and its numerical value from the input 27 of the system go to the input of the register 78 of block 5, where they are entered by the synchronizing pulse from the input 31. From the output of 101 register 78, the code of the identifier of the criterion goes to one input of the decoder 80 and from the output 100 of register 78 - the code of the numerical the value of the criterion is fed to one input of the comparator 83.

After a set of input data, the operator presses the “EXECUTE” key, after which the code of the identifier of the time period from the input 25 of the system goes to the information input of the register 40 of block 1, and the code of the identifier of the group of flights from the input 26 of the system goes to the information input of the register 41 of block 1.

The entry of input codes into the corresponding registers of block 1 is carried out by a synchronizing signal supplied to the input 30 of the system. From the outputs of the registers 40 and 41 (figure 2), the codes are fed to the inputs of the decoders 42 and 43, respectively. Decoder 42 decrypts the identifier of the time period, and decoder 43 decrypts the code of the sign of the group of flights, giving out one of its outputs a high potential. In parallel with this, the synchronizing pulse from the input 30 of block 1 is fed to the input of element 52, where it is delayed by the time the codes are entered in registers 40, 41 and the decryptors 42, 43 are triggered. Then the same pulse goes to the inputs of elements 46-51 AND, interrogating them state.

Considering the fact that only one of the elements 46-48 I will be open decoder 42 at one input, and only one of the elements 49 - 51 I will be open decoder 43 at one input, then passing the corresponding elements I, the clock pulse, firstly, arrives at the read input of the corresponding fixed memory cell of the permanent storage device 44. In this ROM cell, the relative address of the memory cell of the data warehouse is stored, starting with which the array of attributes of the specified calendar period is stored in the data warehouse, and reads the code of the relative address of the calendar period to the output 56 of block 1.

Secondly, the synchronizing pulse from the output of the delay element 52, passing through the corresponding element 49-51 And, is fed to the read input of the fixed memory cell of the permanent storage device 45, where the reference address of the memory cell of the data warehouse is stored, starting from which an array of indicators is stored in the data warehouse , as well as the total number of records of the array of indicators and reads the code of the reference address to the output 57 of block 1.

The data structure at the output of the memory unit 45 has the following form:

THE CODE THE CODE Reference address of the starting memory cell of the data array The total number of records in the data array

Codes from the outputs 56 and 57 of block 1 are sent to the information inputs 230 and 231 of registers 16 and 17 of block 2, respectively, where they are entered by the synchronizing pulse from the output 59 of block 1, delayed by the delay element 53 for the time of reading codes from memory blocks 44, 45, and coming to the input 232 of block 2. From the output of the register 16 and one output of the register 17, the codes go to the information inputs of the adder 18, which sums the input codes by the synchronizing pulse from the output 60 of the block 1 to the input 233 of the block 2, forming the reference address of the database server starting from which the array of indicators of the reporting calendar period is stored in the server data warehouse.

The code of the generated address from the output of the adder 18 is fed to the information input of the counter 19, where it is entered by the synchronizing pulse coming from the output 61 of block 1 through the input 234 of block 2 to the synchronizing input of the counter 19.

In parallel with this, the same synchronizing pulse from the output 61 of block 1 through the input 201 of block 14 goes to the single input of trigger 191 of block 14 and sets it to a single state, in which, with a high potential from a single output, trigger 191 opens elements 192 And groups of inputs .

The address code from the output 236 of the counter 19 of block 2 through the input 194 of block 14 is supplied to the other inputs of the elements AND 192 of the group, passes the elements 193 OR of the group and issued to the address output 36 of the system.

In parallel with the described process of forming the storage data read address, the synchronizing pulse from the output 61 of block 1 is fed to the input 67 of block 4. Then it passes through the element 64 OR, is delayed by the element 66 for the time of operation of the counter 19, and then, firstly, through the element 65 OR is issued to the output 37 of the system as a read pulse received at the input of the first interrupt channel of the data warehouse server. By this signal, the server switches to the reading routine of the first record of the data array from the data warehouse at the address generated at output 36.

Secondly, the same pulse from the output 74 of block 4 through the input 204 of block 14 passes to the installation input of the trigger 191 and resets it to its original state. From another output 237 of register 17 of block 2, the code for the total number of records of the data array in the data warehouse is fed to input 240 of comparator 21 of block 3, the other input of which receives code from the output of counter 20, which at this point in time is in its original state.

The contents of the reference address of the selected memory cell is issued by the data storage server through the information input 28 of the system to the information input of the register 79 of block 5, where it is entered by the synchronizing pulse of the server coming from the input 32 of the system.

From the output 102 of the register 79 of block 5, its contents are completely output to the output 35 of the system, and the part of the record corresponding to the value of the average load of the vehicle for one flight goes to the inputs of elements 94, 95 And groups.

The decoder 80 of block 5 decrypts the identifier of the specified criterion — the average load of the vehicle per flight set by the operator, and opens the corresponding group of AND elements consisting of a combination of elements 84, 85, 94 or of elements 86, 87, 95. For definiteness, suppose that the elements 84, 85 and 94 I will be open. In this case, the code of the average vehicle load per flight contained in the read-out, from the output 102 of register 79 passes through elements 94 AND groups, then elements 98 OR groups on one input comparate ora 83, to the other input of which the numerical value of the criterion established by the operator from the output 100 of the register 78 is constantly applied.

The comparator 83 of block 5 compares the codes by a clock pulse received from the input 32 of the system, which is then delayed by the element 99 for the time the code is entered in register 79 and then passes to the synchronizing input of the comparator 83. If the numerical value of the criterion in register 78 is greater than the numerical value of the average load by one flight contained in the record, then the pulse 112 appears at the output 112 of the comparator 83, which through the element 84 AND, then the element 96 OR is fed to the inputs of the elements 88-90 I.

Considering, however, that by now the counter 82 is in its initial state, then the decoder 81 generates a high potential, opening the element 88 AND, and the pulse from the output of the element 96 OR passes through the element 88 AND to the output 105 of block 5, from where it goes to the input 135 blocks 7.

From the input 135 of block 7, this pulse is supplied to the inputs of the elements 123, 124 I. Given that the trigger 121 is in the initial state, then the high potential from the inverse output will be open for the 123 element, and the element 124 will be closed with a low potential from the direct output.

As a result of this, the input pulse passes through the And element 123 to the read input of the memory block 115, made in the form of a permanent storage device, in a fixed memory cell of which the starting base address is stored, starting from which the newly formed data array will be written to the server database.

After reading, the base address goes to the information input of the register 116, where it is entered by the synchronizing pulse from the output of the element 123, delayed by the element 130 for the time of reading the code from the ROM 115. From the output of the register 116, the base address of the record of the newly formed array goes to one input of the adder 117, the other input of which receives the readings of the counter 118, which is in the initial state.

In addition, the synchronizing pulse from the output of the delay element 130 arrives at the direct input of the trigger 121, setting it to a single state, in which the 123 And element for the next input pulse from the input 135 will be closed, and the And element 124 is open to the element’s input a delay 131 delaying the synchronizing pulse for the time the base address code is entered in the register 116. From the output of the delay element 131, the synchronizing pulse through the OR element 128 is, firstly, fed to the synchronizing input of the adder 117, by which the adder 117 summarizes There is a register reading with a counter reading of 118.

Secondly, the same pulse is fed to the direct input of trigger 122, setting it to a single state, in which, with a high potential from the direct output, trigger 122 opens elements 126 AND, connecting the output of adder 117 through elements 126 AND groups and elements 129 OR to the output 138 of the block 7. The address code from the output 138 of block 7 goes to the input 196 of block 14, passes the elements 193 of the OR group, and is issued to the address output of the system 36 as the write address of the newly formed data array.

Thirdly, this pulse is delayed by the element 132 for the duration of the operation of the adder 117 and the trigger 122 and is issued to the output 140 of the block 7 as a write pulse, which is input to the input 175 of the block 13, the OR element 170 passes and is issued as the output 187 of the block 13, and to the output 38 of the system as a synchronizing pulse of writing the contents of the register 79 of block 5 from the output 35 of the system to the database at the address generated at the output 36 of the system. From the output 187 of block 13, a synchronizing pulse is fed to the counting input 241 of block 3, increasing the readings of the counter 20 of block 3 by one, and fixing, thereby recording the fact of writing to the database the next record of the array being formed.

Fourthly, from the output of the delay element 132 of block 7, the write synchronization pulse is again delayed by the delay element 133 while the contents of register 79 are being written to the system database, and then it is output to the counting input of the counter 118, which counts the number of records made, to the installation input of the trigger 122, resetting it to its initial state, and from the output 141 of the block 7 to the input 181 of the block 13, where the OR element 172 passes, and from the output 188 of the block 13 it enters through the synchronizing input 242 of the block 3 to the synchronizing input of the comparator 21, comparing the total lo entries in the initial array data supplied from the input 240, with the number of records recorded by the counter 20.

Given that at this point in time only the first record of the newly formed data array was recorded in the counter 20, then its readings will be much less than the readings of the register 17 of block 2.

As a result of this, a synchronizing signal “less” is generated at the output 211 of block 3, which, firstly, passes through the input 235 of block 2 to the counting input of the counter 19, increasing the read reference address by one.

Secondly, the same pulse is fed to the input 203 of block 14, the OR element 194 passes, and fed to the single input of the trigger 191, setting it to a single state in which, with a high potential from the direct output of the trigger, the group of 192 And elements will be open to transmit the address code output 36 of the system.

Thirdly, the same pulse is fed to input 68 of block 4, where the OR element 64 passes, is delayed by the time the address code was issued to the system output 36, and then through the OR element 65 it is again output to the system output 37 as a read pulse arriving at input of the first channel of the server interrupt. By this signal, the server again switches to the subroutine for reading the next record of the data array from the server database at the address generated at output 36. In addition, the same read pulse from output 74 of block 4 passes through input 204 of block 14 to the installation input of trigger 191 and resets its initial state.

If the numerical value of the criterion in the register 78 is less than the numerical value of the average vehicle load per flight contained in the record, the signal will appear on the other output 111 of the comparator 83. This pulse now passes through another element 85 AND, then the element 97 OR and then comes to the inputs of elements 91-93 I. Given, however, that by now the counter 82 remains in its original state, then the high potential decoder 81 opens the AND element 91, and the pulse from the output of the OR element 97 passes through the AND element 91 the output 106 of block 5, from where it enters the input 135 of block 8.

From the input 135 of block 8, this pulse is fed to the inputs of the elements 123, 124 AND, the state of which is determined by the trigger 121. Given that the trigger 121 is in its original state, then the high potential from the inverse output will be open for the 123 And element, and the element 124 will be closed with a low potential from a direct exit.

As a result of this, the input pulse passes through the And element 123 to the read input of the memory block 115, made in the form of a permanent storage device, in a fixed memory cell of which the starting base address is stored, starting from which the newly formed data array will be written to the server database.

As a result of reading, the base address goes to the information input of the register 116, where it is entered by the synchronizing pulse from the output of the element 123, delayed by the element 130 while reading the code from the ROM 115.

From the output of the register 116, the base address of the record of the newly formed array goes to one input of the adder 117, the other input of which receives the readings of the counter 118, which is in the initial state.

In addition, the synchronizing pulse from the output of the delay element 130 goes both to the direct input of the trigger 121, setting it to a single state, in which the 123 And element for the next input pulse from the input 135 will be closed, and the And element 124 will be open, and the input a delay element 131 delaying the synchronizing pulse for the time the base address code is entered in the register 116.

From the output of the delay element 131, the synchronizing pulse through the OR element 128, firstly, is fed to the synchronizing input of the adder 117, by which the adder 117 summarizes the readings of the register with the zero readings of the counter 118.

Secondly, the same pulse is fed to the direct input of trigger 122, setting it to a single state, in which, with a high potential from the direct output, trigger 122 opens elements 126 AND, connecting the output of adder 117 through elements 126 AND groups and elements 129 OR to the output 138 of the block 8.

The address code from the output 138 of block 8 is received at the input 197 of block 14, the elements OR 193 of the group pass, and is output to the address output of the system 36 as the write address of the newly formed data array.

Thirdly, this pulse is delayed by the element 132 for the duration of the operation of the adder 117 and the trigger 122 and is output to the output 140 of the block 8 as a write pulse, which is input to the input 176 of the block 13, the OR element 170 passes and is issued as the output 187 of the block 13, and to the output 38 of the system as a synchronizing pulse of recording the contents of the register 79 from the output 35 of the system to the database at the address generated at the output 36 of the system. From the output 187 of block 13, the synchronizing pulse through the input 241 of block 3 is fed to the counting input of the counter 20, increasing its readings by one, and fixing, thereby recording the fact of writing to the database the next record of the array being formed.

Fourthly, from the output of the delay element 132, the write pulse is again delayed by the delay element 133 for the duration of writing the contents of the register 79 to the system database, and then it is output to the counting input of the counter 118, which counts the number of array entries produced, to the installation input of the trigger 122, resetting it to the initial state, and from the output 141 of block 8 to the input 182 of block 13, where the OR element 172 passes, and from the output 188 of block 13 through the input 242 of block 3, it goes to the synchronizing input of the comparator 21, comparing the total number of records in the original data array x, with the number of records recorded by the counter 20. Given that at this point in time only the first record of the newly formed data array was recorded in the counter 20, then its readings will be much less than the readings of the register 17 of block 2.

As a result of this, a synchronizing signal “less” is generated at the output 211 of block 3, which, firstly, enters through the input 235 of block 2 and enters the counting input of the counter 19, increasing the read reference address by one.

Secondly, the same pulse is fed to the input 203 of block 14, the OR element 194 passes, and fed to the single input of the trigger 191, setting it to a single state in which, with a high potential from the direct output of the trigger, the group of 192 And elements will be open to transmit the address code output 36 of the system.

Thirdly, the same pulse is fed to input 68 of block 4, where the OR element 64 passes, is delayed by the time the address code was issued to the system output 36, and then through the OR element 65 it is again output to the system output 37 as a read pulse arriving at input of the first channel of the server interrupt. By this signal, the server again goes to the subroutine for reading the next record of the analyzed data array from the server database at the address generated at output 36. In addition, the same read pulse from output 74 of block 4 passes through input 204 of block 14 to the installation input of trigger 191 and resets it to its original state.

The process of reading the analyzed array from the database and dividing it into arrays M1 and M2 with writing the latter to the server database continues as described above until the comparator 10 fixes the fact that the number of records in the analyzed data array is equal to the number of records recorded by the counter 20 by a synchronizing pulse supplied to the synchronizing input of block 3 from the output 188 of block 13.

At the moment of equal readings at the inputs of the comparator 21, a signal is generated at its output 212, indicating the end of the separation of the analyzed array into arrays M1 and M2. This signal enters the input 206 of block 15, the OR element 205 passes, and then, firstly, it enters the input 104 of block 5, from where it is supplied to the counting input of the counter 82, increasing its readings by one.

Decoder 81, decoding the counter, will give a high potential at its second output and open the next pair of elements 89, 92 And, preparing the circuits for the passage of pulse signals through these elements And at the second stage of separation of the received arrays M1 or M2.

Secondly, from the output of the OR element 205, the signal is output to the system output 39 as a signal to the operator about the end of the first stage of dividing the analyzed array into arrays M1 and M2. In addition, the same signal is fed to the reset inputs of blocks 11 and 12, as well as to the installation inputs of all the registers and counters of the system. The initial installation circuit of these nodes to simplify the structural diagram of the system is not shown in the drawing.

The operator, having received a signal that the arrays M1 and M2 are ready for further analysis, decides to select one of the arrays for further analysis and select the appropriate criterion. For definiteness, suppose that the operator chose for further analysis - array M1 and criterion Kz - vehicle load factor.

The next stage of the analysis begins with the fact that the operator, firstly, enters the criterion identifier Kz and its numerical value from the input 27 of the system into the register 78 of block 5 using the synchronization signal from input 31.

Secondly, from the input 29 to the register 22 of block 6, the operator enters the identifier of the selected array, for example, M1, and gives the command "Perform step 2".

By this command, a synchronization signal is input to the system 33, which, firstly, enters the identifier code of the selected array in register 22 of block 6. This code is decrypted by the decoder 23, which at the output 213 generates a high potential, which through the input 137 of the block 7 is supplied to the input of the 125 I element, opening it one input, and the input of the 127 And group elements, opening them one input and connecting thereby, the output of adder 117 through the elements 129 OR groups to the output 138 of block 7 and then through the input 196 and elements 193 OR groups to the address output 36 of the system. Recall that in the adder 117 of block 7 to this point in time, the address of the last record of the array Ml is fixed.

Secondly, the synchronizing pulse from the input 33 of the system enters the input 69 of block 4, passes the element 65 OR, and enters the output 37 of the system as the first synchronizing signal read array Ml. This signal is fed to the input of the server’s first interrupt channel, at which the server switches to the subroutine for reading the contents of the database at the address set at the system output 36, and entering the read record in the register 79 of block 5 from the system input 28 using the synchronizing server pulse input 32.

From the output of the register 79, its contents are completely output to the output 35 of the system, and the part of the record corresponding to the value of the load criterion for the flight Kz goes to the inputs of the elements 94, 95 And groups.

The decoder 80 of block 12 decrypts the identifier of the flight loading criterion set by the operator and opens the corresponding group of AND elements, consisting, for example, of elements 86, 87, 95 I.

In this case, the code of the load value of the flight contained in the read record, from the output 102 of the register 79 passes through the elements 95 AND groups, then the elements 98 OR groups to one input of the comparator 83, the other input of which is constantly supplied with the numerical value of the load criteria set by the operator.

The comparator 83 of block 5 compares the codes by a clock pulse supplied to input 32, which is then delayed by element 99 while the code is entered into register 79 and then passes to the synchronizing input of comparator 83.

If the numerical value of the criterion Kz in the register 78 is less than the numerical value of Kz contained in the record, then at the output 111 of the comparator 83 an impulse appears, which through the element 87 AND, then the element 97 OR is supplied to the inputs of the elements 91-93 I. Considering, however, that currently in the counter 82 there is one after the end of the first stage, then the decoder 81 generates a high potential at its second output, opening the element 92 AND, and the pulse from the output of the element 97 OR passes through the element 92 AND the output 108 of the block 5, where it comes from input 135 block a 10.

From the input 135 of block 10, this pulse is supplied to the inputs of the elements 123, 124 I. Given that the trigger 121 is in its original state, then the high potential from the inverse output will be open for the 123 And element, and the element 124 will be closed with a low potential from the direct output.

As a result of this, the input pulse passes through element 123 AND to the read input of the memory block 115, made in the form of a permanent storage device, in a fixed memory cell of which the starting base address is stored, starting from which the newly formed data array M3 will be recorded in the server database.

After reading, the base address arrives at the information input of the register 116, where it is entered by the synchronizing pulse from the output of element 123, delayed by element 130 for the time of reading the code from ROM 115. From the output of register 116, the base address of the record of the newly formed array of MOH goes to one input of the adder 117 , the other input of which receives the readings of the counter 118, which is in the initial state.

In addition, the synchronizing pulse from the output of the delay element 130 arrives at the direct input of the trigger 121, setting it to a single state, in which the 123 And element for the next input pulse from the input 135 will be closed, and the And element 124 is open to the element’s input a delay 131 delaying the synchronizing pulse for the time the base address code is entered in the register 116.

From the output of the delay element 131, the synchronizing pulse through the OR element 128, firstly, is fed to the synchronizing input of the adder 117, by which the adder 117 summarizes the readings of the register with the zero readings of the counter 118.

Secondly, the same pulse is fed to the direct input of trigger 122, setting it to a single state, in which, with a high potential from the direct output, trigger 122 opens elements 126 AND, connecting the output of adder 117 through elements 126 AND groups and elements 129 OR to the output 138 of the block 10. The address code from the output 138 of block 10 is sent to the input 198 of block 14, the elements OR 193 of the group pass, and is output to the address output of the system 36 as the write address of the newly formed data array.

Thirdly, this pulse is delayed by the element 132 for the duration of the adder 117 and the trigger 122 and is output to the output 140 of the block 10 as a write pulse, which is input to the input 177 of the block 13, the OR element 171 passes and is output to the output 38 of the system as a clock pulse recording the contents of the register 79 from the output of the 35 system to the database at the address generated at the output of the 36 system.

Fourthly, from the output of the delay element 132, the write synchronization pulse is again delayed by the delay element 133 while the contents of the register 79 are being written to the system database, and then it is output to the counting input of the counter 118, which counts the number of records made, to the installation input of the trigger 122, resetting it to the initial state, and from the output 141 of the block 10 to the input 183 of the block 13, where the OR element 173 passes, and from the output 189 of the block 13 it goes to the synchronizing inputs 136 of the blocks 7 and 8.

Considering that the operator chose the array M1 fixed for block 7 for analysis, then the high potential from the output 213 of block 6, applied to the input 137 of block 7, will open the 125 And block of block 7.

The pulse from input 136 of block 7 passes through element 125 AND to the counting input of counter 119, recording in the counter the fact of entering the first record of array M1 into the database of array M3.

In addition, the pulse from the output of the element 125 And is delayed by the element 134 for the duration of the counter 119 operation and then goes to the synchronizing input of the comparator 120. At one input of the comparator, a code comes from the output of the counter 118, which records the number of records contained in the array Ml, and another input - a code comes from the output of counter 119, which counts the number of read records in the array M1 from the server database.

If the number of read records of the array M1 in the counter 119 is less than the number of records recorded in the counter 118, then the comparator 120 generates a signal at the output 217, which passes through the output 139 of block 7 to the input 70 of block 4, the OR element 65 passes, and again issued to the output of the 37 system. From the output 37, the synchronizing signal is again fed to the input of the first channel of the server interrupt, transferring it to the subroutine for reading the next record in the manner described above.

If the numerical value of the Kz criterion in register 78 is greater than the numerical value of the Kz criterion contained in the record, the signal will appear on the other output 112 of the comparator 83. This pulse now passes through another element 86 AND, then the element 96 OR and then goes to the inputs of the elements 88-90 I. Given, however, that to date, the high potential decoder 81 opens the 89 AND element, the pulse from the output of the 96 OR element passes through the 89 AND element to the output 107 of block 5, from where it enters the input 135 of block 15.

From the input 135 of block 9, this pulse is supplied to the inputs of the elements 123, 124 AND, the state of which is determined by the trigger 121. Given that the trigger 121 is in its original state, then the high potential from the inverse output will be open for the 123 And element, and the element 124 will be closed with a low potential from a direct exit.

As a result of this, the input pulse passes through element 123 AND to the read input of the memory block 115, made in the form of read-only memory, in a fixed memory cell of which the starting base address is stored, starting from which a newly formed data array will be written to the server database (M4) .

After reading, the base address arrives at the information input of the register 116, where it is entered by the synchronizing pulse from the output of element 123, delayed by element 130 for the time of reading the code from ROM 115. From the output of register 116, the base address of the record of the newly formed array M4 goes to one input of the adder 117 , the other input of which receives the readings of the counter 118, which is in the initial state.

In addition, the synchronizing pulse from the output of the delay element 130 goes both to the direct input of the trigger 121, setting it to a single state, in which the 123 And element for the next input pulse from the input 135 will be closed, and the And element 124 will be open, and the input a delay element 131 delaying the synchronizing pulse for the time the base address code is entered in the register 116.

From the output of the delay element 131, the synchronizing pulse through the OR element 128, firstly, is fed to the synchronizing input of the adder 117, by which the adder 117 summarizes the readings of the register with the zero readings of the counter 118.

Secondly, the same pulse is fed to the direct input of trigger 122, setting it to a single state, in which, with a high potential from the direct output, trigger 122 opens elements 126 AND, connecting the output of adder 117 through elements 126 AND groups and elements 129 OR to the output 138 of the block 9.

The address code from the output 138 of block 9 goes to the input 199 of block 14, the elements OR 193 of the group pass, and is output to the address output of the system 36 as the write address of the newly formed data array M4.

Thirdly, this pulse is delayed by the element 132 for the duration of the operation of the adder 117 and the trigger 122 and is output to the output 140 of the block 9 as a write pulse, which is input to the input 178 of the block 13, the OR element 171 passes, and is issued to the output 38 of the system as a clock pulse recording the contents of the register 79 from the output of the 35 system to the database at the address generated at the output of the 36 system.

Fourthly, from the output of the delay element 132, the write synchronization pulse is again delayed by the delay element 133 while the contents of the register 79 are being written to the system database, and then it is output to the counting input of the counter 118, which counts the number of records made, to the installation input of the trigger 122, resetting it in the initial state, and from the output 141 of the block 9 to the input 184 of the block 13, where the OR element 173 passes, and from the output 189 of the block 13 it goes to the synchronizing input 136 of the block 7.

The pulse from the input 136 of block 7 again passes through the element 125 And to the counting input of the counter 119, recording in the counter the fact of entering the next record of the array M1 into the database of the array M4.

In addition, the pulse from the output of the element 125 And is delayed by the element 134 for the duration of the counter 119 operation and then goes to the synchronizing input of the comparator 120. At one input of the comparator, a code comes from the output of the counter 118, which records the number of records contained in the array M1, and another input - a code comes from the output of counter 119, which counts the number of read records in the array M1 from the server database.

If the number of read records of the array M1 in the counter 119 is less than the number of records recorded in the counter 118, then the comparator 120 generates a signal at the output 217, which passes through the output 139 of block 13 to the input 70 of block 4, the OR element 65 passes, and again issued to the output of the 37 system.

The described process of dividing the array of records and entering them into blocks 9 and 10 continues until the comparator 120 of block 7 fixes the fact that the readings of the counters 118 and 119 are equal by issuing a synchronizing signal to the output 218.

From this output, the synchronizing signal, firstly, enters the installation input of the trigger 121 of block 7, returning it to its original state, and, secondly, it is outputted to the output 142 of block 7, from where it enters the input 207 of block 15. In block 15, it the OR element 205 passes and from the output of block 15 it enters both the input 104 of block 5 and the output 39 of the system, signaling the operator that the procedure for dividing the array M1 into arrays M3 and M4 has been completed.

The operator, having received a signal that the M3 and M4 arrays are ready for further analysis, decides to select one of them for further analysis and select the appropriate criterion.

For definiteness, suppose that the operator chose for further analysis - the MOH array and the Pax criterion - the number of passengers carried per flight (Fig. 10).

The next stage of the analysis begins with the fact that the operator, firstly, in the register 78 enters the identifier of the criterion Pax and its numerical value from the input 27 of the system according to the synchronizing signal from the input 31.

Secondly, from the input 29 to the register 22 of block 6, the operator enters the identifier of the selected array, for example, MOH, and gives the command "Perform step 3".

By this command, a synchronizing signal is input to the system 33, which, firstly, enters the identifier code of the selected array in register 22. This code is decoded by the decoder 23, which at the output 215 generates a high potential, which through the input 137 of the block 9 is supplied both to the input of the 125 And element, opening it one input, and to the input of the 127 And group elements, opening them one input and connecting thereby, the output of adder 117 through the elements 129 OR groups to the output 138 of block 9 and then through the input 199 and elements 193 OR groups to the address output 36 of the system. Recall that in the adder 117 of block 9, at this moment in time, the address of the last record of the M3 array is fixed.

Secondly, the synchronizing pulse from the input 33 of the system enters the input 69 of block 4, passes the element 65 OR, and enters the output 37 of the system as the first synchronizing signal to read the array M3. This signal is fed to the input of the first server interrupt channel, at which the server goes to the subroutine for reading the contents of the database at the address set at the output 36 of the system, and entering the read record in register 79 from the input 28 of the system using the synchronizing pulse of the server, which is input 32 .

From the output of the register 79, its contents are completely output to the output 35 of the system, and the part of the record corresponding to the value of the criterion is supplied to the inputs of the elements 94, 95 And groups. The decoder 80 of block 5 decodes the identifier of the criterion Pax, set by the operator, and opens the corresponding group of elements AND, consisting, for example, of elements 86, 87, 95 I.

In this case, the code of the value of Pax contained in the read record passes through the elements of the 95 AND groups, then the elements 98 OR of the group to one input of the comparator 83, the other input of which is constantly supplied with the numerical value of the load criterion set by the operator.

The comparator 83 of block 5 compares the codes by the clock pulse from input 32, which is then delayed by element 99 while the code is entered in register 79 and then passes to the synchronizing input of the comparator 83.

If the numerical value of the criterion Pax in the register 79 is less than the numerical value of Pax contained in the record, then the pulse 111 appears at the output 111 of the comparator 83, which passes through the element 87 AND, then the element 97 OR is supplied to the inputs of the elements 91-93 I. Considering, however, that To date, a counter corresponding to two completed steps has been fixed in the counter 82, then the decoder 81 generates a high potential at its next output, opening the AND element 93, and the pulse from the output of the OR element 97 passes through the element 93 AND to the output 110 of block 5, from where it arrives to the input 165 of the block 12 and further to the inputs of the elements 156, 157 I.

Given that the trigger 154 is in the initial state, then the high potential from the inverted output element 156 And will be open, and the element 157 is closed by a low potential from the direct output.

As a result of this, the input pulse passes through the And element 156 to the read input of the memory block 115, made in the form of a permanent storage device 150, in a fixed memory cell of which the starting base address is stored, starting from which the newly formed data array M5 will be written to the server database.

After reading, the base address goes to the information input of the register 151, where it is entered by the synchronizing pulse from the output of the 156 I element, delayed by the element 160 for the time of reading the code from the ROM 150. From the output of the register 151, the base address of the record of the newly formed array M5 goes to one input of the adder 152, the other input of which receives the readings of the counter 153, which is in the initial state.

In addition, the synchronizing pulse from the output of the delay element 160 arrives at the direct input of the trigger 154, setting it to a single state, in which the And element 156 for the next input pulse from the input 165 will be closed, and the And element 157 will be open to the element’s input a delay 161 delaying the synchronizing pulse for the time the base address code is entered in the register 151. From the output of the delay element 161, the synchronizing pulse through the OR element 159 is, firstly, fed to the synchronizing input of the adder 152, by which the adder 152 summarizes The readings of the register 151 with the zero readings of the counter 153.

Secondly, the same pulse is applied to the direct input of the trigger 155, setting it to a single state, in which the high potential from the direct output of the trigger 155 opens the elements 158 And groups, connecting the output of the adder 152 through the elements 158 And groups to the output 166 of the block 12. Code the address from the output 166 of the block 12 is fed to the input 201 of the block 14, the elements OR 193 of the group pass through and is output to the address output of the system 36 as the recording address of the newly formed data array.

Thirdly, this pulse is delayed by element 162 for the time of operation of the adder 152 and trigger 155 and is output 167 of block 12 as a write pulse, which is input to input 180 of block 13, passes OR element 171 and is output to system output 38 as a synchronizing pulse recording the contents of the register 79 from the output of the 35 system to the database at the address generated at the output of the 36 system.

Fourthly, from the output of the delay element 162, the synchronizing write pulse is again delayed by the element 163 for the duration of writing the contents of the register 79 to the system database, and then it is output to the counting input of the counter 153, which counts the number of records made, to the installation input of the trigger 155, resetting it to the initial state, and from the output 168 of the block 12 to the input 186 of the block 13, where the OR element 174 passes, and from the output 190 of the block 13 it goes to the synchronizing inputs 136 of the blocks 9 and 10.

Given that the operator for the subsequent analysis chose the M3 array fixed by block 9, then the high potential from the output 215 of block 6, applied to the input 137 of block 9, will open the 125 And block of block 9.

The pulse from input 136 of block 9 passes through element 125 AND to the counting input of counter 119, recording in the counter the fact of entering the first record of array M3 into the database of array M5.

In addition, the pulse from the output of the element 125 And is delayed by the element 134 for the duration of the counter 119 and then goes to the synchronizing input of the comparator 120. At one input of the comparator, a code is received from the output of the counter 118, which records the number of records contained in the M3 array, and another input - the code comes from the output of counter 119, which counts the number of read records in the M3 array from the server database.

If the number of read records of the M3 array in counter 119 is less than the number of records recorded in counter 118, then the comparator 120 generates a signal at the output 217 by a synchronizing pulse, which is transmitted through the output 139 of block 9 to the input 72 of block 4, the OR element 65 passes, and again issued to the output of the 37 system.

From the output 37, the synchronizing signal is again fed to the input of the first channel of the server interrupt, transferring it to the subroutine for reading the next record in the manner described above.

If the numerical value of the criterion Pax in register 79 is greater than the numerical value of the criterion Pax contained in the record, the signal will appear on the other output 112 of the comparator 83. This pulse now passes through another element 86 AND, then the element 96 OR and then goes to the inputs of the elements 88-90 I.

Considering, however, that to date, the decoder 81 has a high potential that opens the element 90 AND, the pulse from the output of the element 96 OR passes through the element 90 AND to the output 109 of the block 5, from where it goes to the input 165 of the block 11 and then to the inputs of the elements 156, 157 AND, the state of which is determined by trigger 154. Given that trigger 154 is in the initial state, then the high potential from the inverse output will open the element 156 And, and the element 157 will be closed with a low potential from the direct output.

As a result of this, the input pulse passes through the element 156 And to the read input of the memory block 150, made in the form of a permanent storage device, in a fixed memory cell of which the starting base address is stored, starting from which the newly formed data array will be written to the server database (M6) .

After reading, the base address goes to the information input of the register 151, where it is entered by the synchronizing pulse from the output of the 156 I element, delayed by the element 160 for the time of reading the code from the ROM 150. From the output of the register 151, the base address of the record of the newly formed array M6 goes to one input of the adder 152, the other input of which receives the readings of the counter 153, which is in the initial state.

In addition, the synchronizing pulse from the output of the delay element 160 goes both to the direct input of the trigger 154, setting it to a single state, in which the And element 156 for the next input pulse from the input 165 is closed, and the And element 124 is open, and to the input delay element 161, delaying the synchronizing pulse for the time the base address code is entered in the register 151.

From the output of the delay element 151, the synchronizing pulse through the OR element 159 is, firstly, fed to the synchronization input of the adder 152, by which the adder sums the readings of the register 151 with the zero readings of the counter 153.

Secondly, the same pulse is supplied to the direct input of the trigger 155, setting it to a single state, in which the high potential from the direct output of the trigger 155 opens the elements 158 And connecting the output of the adder 152 through the elements 158 And groups to the output 166 of block 11.

The address code from the output 166 of block 11 goes to the input 200 of block 14, passes the elements 193 of the OR group, and is output to the address output of the system 36 as the write address of the newly formed data array M6.

Thirdly, this pulse is delayed by element 162 for the time of operation of the adder 152 and trigger 155 and is output 167 of block 11 as a recording pulse, which is input to input 179 of block 13, OR element 171 passes, and is output to system output 38 as a clock pulse recording the contents of the register 79 from the output of the 35 system to the database at the address generated at the output of the 36 system.

Fourthly, from the output of the delay element 162, the write synchronization pulse is again delayed by the delay element 163 for the duration of writing the contents of the register 79 to the system database, and then it is output to the counting input of the counter 153, which counts the number of records made, to the installation input of the trigger 155, resetting it to the initial state, and from the output 168 of the block 11 to the input 185 of the block 13, where the OR element 174 passes, and from the output 190 of the block 13 it goes to the synchronizing input 136 of the block 9.

The pulse from input 136 of block 9 again passes through element 125 AND to the counting input of counter 119, recording in the counter the fact of entering the next record of the M3 array into the database of the M6 array.

In addition, the pulse from the output of the element 125 And is delayed by the element 134 for the duration of the counter 119 and then goes to the synchronizing input of the comparator 120. At one input of the comparator, a code is received from the output of the counter 118, which records the number of records contained in the MOH array, and another input - the code comes from the output of counter 119, which counts the number of read records in the M3 array from the server database.

If the number of read records of the M3 array in counter 119 is less than the number of records recorded in counter 118, then the comparator generates a signal at the output 217 by a synchronizing pulse, which, through the output 139 of block 9, goes to the input 72 of block 4, the OR element 65 passes, and is returned again output 37 of the system.

The described process of dividing the array of M3 records and entering them into blocks 11 and 12 continues until the comparator 120 of block 9 fixes the fact that the readings of the counters 118 and 119 are equal by issuing a synchronizing signal to output 218. From this output, the synchronizing signal, firstly , arrives at the installation input of the trigger 121 of block 9, returning it to its original state, and, secondly, it is issued to the output 142 of block 9, from where it goes to the input 209 of block 15. In block 15, it passes the OR element 205 and from output 39 block 15, he arrives at the input 104 of block 12, and output 39 of the system, signaling to the operator about the end of the procedure for dividing the MOH array into M5 and M6 arrays.

Thus, the introduction of new nodes and blocks and new structural connections has significantly improved system performance by localizing the range of data search addresses in the server database

Sources of information taken into account when drawing up the description of the application:

1. RF patent No. 2280281 (02/14/2005)

2. RF patent No. 77464 (04.16.2008) - (prototype).

Claims (1)

An automated planning system for transporting troops (cargo) by sea (river) transport, containing a data array selection block for solving computational problems, the first and second information inputs of which are the first and second information inputs of the system, and the synchronizing input is the first synchronizing input of the system, while the first the information input of the system is designed to receive the identifier code of the planning time period, the second information input of the system is designed to receive the identifier code a torus of a group of flights for transporting troops (cargoes), and the first synchronizing input of the system is intended for receiving synchronizing pulses of entering input codes into a data array selection block for solving computational problems, a data storage address modification block, the information inputs of which are connected to the corresponding information outputs of the data array selection block for solving computational problems, the synchronizing inputs of the data storage address modification block are connected to the corresponding synchronizing outputs of the block and data arrays for solving computational problems, while the first information output of the data storage address modification block is connected to the first information input of the address signal integration unit, the first synchronizing input of which is connected to the third synchronizing output of the data arrays selection unit for solving computational problems, and the output of the integration unit address signals is the address output of the system, a data selection unit for solving computational problems, the first information input of which is the third information the input of the system intended for receiving the identifier code of the data selection criterion, the second information input of the data selection block for solving computational problems is the fourth information input of the system intended for receiving data from the server data storage, one synchronizing input of the data selection block for solving computational problems is the third synchronizing system input, designed to enter the code of the data selection criterion in the data selection block for solving computational problems, and another synchronization The input input of the data selection unit for solving computational problems is the fourth synchronizing input of the system designed to enter data storage data into the data selection unit for solving computational problems, while the information output of the data selection unit for solving computational problems is the information output of the system, the unit for specifying design features tasks, the information input of which is the fifth information input of the system, designed to receive the identifier of the selected data array, and synchronize The zeroth input of the unit for setting signs of computational tasks is the fifth synchronizing input of the system, intended for receiving synchronizing signals for entering the identifier of the selected data array into the unit for specifying attributes of computational tasks, a unit for integrating read signals, the first input of which is connected to the third synchronizing output of the block for selecting arrays of data for solving computational tasks, while one output of the read signal integration unit is the first synchronizing system output intended To provide read signals to the input of the first interrupt channel of the data warehouse server, and the other output of the read signal integration unit is connected to the installation input of the address signal integration unit, the write signal integration unit, the first output of which is the second synchronizing output of the system for issuing write signals to the input the second channel of the interruption of the data warehouse server, and a reset signal integration unit, the output of which is the system signal output intended for signaling and the end of the procedure for separating data arrays, characterized in that the system comprises a unit for identifying intervals of data sampling, the information input of which is connected to another information output of the unit for modifying the addresses of the data warehouse, the counting input of the unit for identifying intervals of data sampling is connected to the second output of the unit for integrating recording signals, and the synchronizing input of the data sampling interval identification unit is connected to the third output of the recording signal integration unit, while one output of the identification unit the data of intervals of sampling data is connected to the counting input of the block for modifying the addresses of the data warehouse, to the second synchronizing input of the unit for integrating read signals and to the second synchronizing input of the unit for integrating address signals, and the other output of the unit for identifying intervals of data sampling is connected to the first input of the unit for integrating reset signals, the first a unit for generating signals for writing and reading data from the data warehouse, the first input of which is connected to the first output of the marketing data selection unit, the second One of the first unit for generating signals for writing and reading data from the data warehouse is connected to the fourth output of the unit for integrating recording signals, and the third input for the first unit for generating signals for writing and reading data from the data warehouse is connected to the first output of the unit for specifying design tasks, while the information output of the first unit for generating data recording and reading signals of the data warehouse is connected to the second information input of the address signal integration unit, the first synchronizing output of the first a unit for generating signals for writing and reading data of the data warehouse is connected to a third clock input of the unit for integrating read signals, the second and third clock outputs of the first unit for generating signals for writing and reading data for the data warehouse are connected to the first and second clock inputs of the unit for integrating write signals, respectively, and a fourth clock the output of the first unit for generating signals for writing and reading data from the data warehouse is connected to the second input of the integration unit and reset signals, the second unit for generating signals for writing and reading data from the data warehouse, the first input of which is connected to the second output of the marketing data selection block, the second input is connected to the fourth output of the recording signal integration unit, and the third input is connected to the second output of the set of signs for calculating tasks while the information output of the second block of the formation of signals for writing and reading data from the data warehouse is connected to the third information input of the integration block of address signals, the first sync the resonant output of the second data signal writing and reading data generating unit is connected to the fourth synchronizing input of the read signal integration unit, the second and third synchronizing outputs of the second data signal writing and reading data generating unit is connected to the third and fourth synchronizing inputs of the recording signal integration unit, respectively, and the fourth synchronizing output of the second block of the formation of signals for writing and reading data from the data warehouse is connected n with the third input of the integration block of the reset signals, the third block of generating signals for writing and reading data of the data warehouse, the first input of which is connected to the third output of the block of data selection for solving computational problems, the second input is connected to the fifth output of the block of integration of recording signals, and the third input is connected with the third output of the unit for setting signs of computational tasks, while the information output of the third unit of generating signals for writing and reading data from the data warehouse is connected to the fourth information input at the integration unit of the address signals, the first synchronizing output of the third unit of generating signals for writing and reading data of the data warehouse is connected to the fifth synchronizing input of the unit for integrating read signals, the second and third synchronizing outputs of the third unit for generating signals for reading and data of the data warehouse are connected to the fifth and sixth synchronizing the inputs of the recording signal integration block, respectively, and the fourth clock output of the third recording signal generation block and the data store data reader is connected to the fourth input of the reset signal integration unit, the fourth data storage unit for generating data recording and reading data, the first input of which is connected to the fourth output of the calculation task data selection unit, the second input of the fourth data storage unit for recording and reading data signals is connected to the fifth output of the unit for integrating recording signals, and the third input of the fourth unit for generating recording signals and reading data from the data warehouse is connected to four the output of the block for specifying the signs of the calculation tasks, while the information output of the fourth block of generating signals for writing and reading data of the data warehouse is connected to the fifth information input of the unit for integrating address signals, the first clock output of the fourth block for generating signals for writing and reading data of the data warehouse is connected to the sixth synchronizing input a unit for integrating read signals, the second and third synchronizing outputs of the fourth unit for generating recording signals and read data warehouse data are connected to the seventh and eighth synchronizing inputs of the recording signal integration block, respectively, and the fourth synchronizing output of the fourth data recording and reading signal generating block is connected to the fifth input of the reset signal integration block, the output of which is connected to the counting input of the marketing data selection block , the first block for generating signals for recording data of the data warehouse, one input of which is connected to the fifth output of the block for selecting data of computational problems, and d The right input of the first data warehouse data recording signal generation unit is connected to the output of the reset signal integration unit, the information output of the first data warehouse data recording signal generation unit is connected to the sixth information input of the address signal integration unit, and the second and third synchronizing outputs of the first data recording signal generation unit data storages are connected to the ninth and tenth synchronizing inputs of the recording signal integration block, respectively, and the second block is formed I am a data warehouse data recording signal, one input of which is connected to the sixth output of a computational task data selection unit, and another input of a second data warehouse data generating unit is connected to an output of a reset signal integration unit, the information output of a second data warehouse data recording unit is connected with the seventh information input of the address signal integration unit, and the second and third synchronizing outputs of the first signal generation data recording unit of the data warehouse connected to the eleventh and twelfth clock inputs of the write signal integration block, respectively, while the seventh clock input of the read signal integration block is connected to the fifth clock input of the system.

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