RU110866U1 - MEMORY ELEMENT OF A DYNAMIC OPERATIVE REMEMBER - Google Patents

Abstract

 The memory element of dynamic random access memory (DOS), consisting of a semi-insulating semiconductor substrate, on which an inverted structure of a selectively doped heterostructured transistor is formed, containing a buffer layer of an undoped semiconductor, a first undoped barrier layer of a wide-gap semiconductor, a doped delta layer, a second undoped semiconductor wide-gap barrier layer conducting undoped layer of narrow-gap elastically stressed semiconductor ka, the third undoped barrier layer of a wide-gap semiconductor, drain and source regions and metallized contacts to them, on which a mesostructure is formed between the drain and source regions, containing an array of quantum dots from an undoped narrow-gap semiconductor between the barrier layers of an undoped wide-gap semiconductor to which a metallized contact is formed with Schottky barrier of the control electrode (gate), characterized in that the buffer layer is formed on the superlattice and has a composite trukturu variable composition, conducting channel layer formed of a narrow bandgap semiconductor unstressed, mesostructure comprises two arrays with a number of vertically and laterally ordered quantum dots of a predetermined size.

Description

The proposed utility model relates to the field of electronics and computer technology, specifically to dynamic random access memory (DOS).

A known analogue of the claimed object is a memory element DOSE [RU Patent No.RU 2216795 C2 dated February 27, 2001] containing a storage capacitor, address, bit and common bus, p- (n-) channel MOS transistor, non-linear resistor and bipolar npn (pnp) transistor.

This memory element allows recording, short-term storage and reading of an electric charge.

Signs of an analogue that coincide with the essential features of the claimed object are the structure of the MOS transistor (in the inventive device, the structure of a selectively doped heterostructure transistor) with drain and source regions, metallized contacts to them and a control electrode (gate), a storage capacitor (in the inventive device, the mesostructure with arrays quantum dots).

Reasons that impede the achievement of the technical result are: the large area occupied by the element, poor scalability, and significant power consumption.

A known analogue of the claimed object is a memory element DOSE [GB Patent No.GB 2,283,128 A of April 26, 1995] containing a semi-insulating substrate of a semiconductor material on which an undoped barrier layer of wide-gap material is formed, a layer of two-dimensional electron gas (DEG) at the heteroboundary substrate-barrier layer a photosensitive material in which drain and source regions and metallized contacts to them are formed, on which a mesostructure consisting of an array of quantum dots is formed between the drain and source regions made of metal in a metal oxide matrix to which a metal contact of the control electrode (gate) is formed.

This design of the memory element allows you to record, short-term storage and reading of information, reduce the size of the functional element, increase the packing density of the elements.

Signs of an analogue that coincide with the essential features of the claimed utility model are: a semi-insulating substrate of a semiconductor material, an undoped barrier layer of wide-gap material, a mesostructure with an array of quantum dots, a drain and a source region and metallized contacts to them, a control electrode (gate), and transistor and capacitive structures.

Reasons that hinder the achievement of the technical result are: a combined (optical and electrical) recording method, the use of a photosensitive layer, uneven array and the spread of geometric parameters of quantum dots.

Of the known closest in technical essence to the claimed object is the element DOSE [Balocco C., Song AM, Missous M. Room-temperature operations of memory devices based on self-assembled InAs quantum dot structures // Applied Physics Letters, Vol. 85, No. 24, December 13, 2004 - p.5911-5913], containing a semi-insulating semiconductor substrate on which an inverted structure of a selectively doped heterostructure transistor (SLTG) is formed, containing a buffer layer of an undoped semiconductor, an undoped wide-gap semiconductor barrier layer, an alloyed delta layer, undoped the first wide-gap semiconductor barrier layer, the conductive undoped narrow-gap semiconductor layer, the unalloyed wide-gap semiconductor barrier layer, the drain and source regions and the metallized contacts to them, on which a mesostructure is formed between the drain and source regions, consisting of one array of quantum dots from an undoped narrow-gap semiconductor between barrier layers of an undoped wide-gap semiconductor to which a metallized contact with the Schott barrier is formed and control electrode (gate).

This design of the storage element allows the operation of recording, short-term storage and reading of the electric charge, reduce the size of the functional element, increase the packing density of memory cells, reduce power consumption of the device.

Signs of the prototype, which coincide with the essential features of the claimed object, are a semi-insulating semiconductor substrate, undoped barrier layers of a wide-gap semiconductor, a mesostructure with quantum dots, drain and source regions and metallized contacts to them, a control electrode (gate), and structural integration of transistor and capacitive structures.

The reasons that impede the achievement of the technical result are arrays of disordered quantum dots, the spread of the geometric parameters of quantum dots, and the stressed material of the layer of the conducting channel.

The objective of the proposed invention is to reduce power consumption, lower operating voltages, increase noise immunity and speed of the memory element, increase the density of recorded information. This is achieved through the use of a superlattice that effectively filters the substrate dislocations, a composite buffer of variable composition, which removes elastic stresses and extends the range of variations in the composition of the overlying layers, together with the superlattice allowing the use of a defect-free, unstressed layer of a narrower-gap semiconductor with a lower effective mass and greater mobility carriers, which significantly improves the electrophysical characteristics of the device, as well as the introduction of two massif into the mesostructure in with a certain number of ordered quantum dots of a given size, each of which is in a layer of a wide-gap semiconductor of various compositions, which makes it possible to record information by modifying the energy structure of quantum dots under the influence of the surrounding material with a different band gap specified by its composition, by separate recording of information in each array, whose ordered structure contributes to increased noise immunity and reduced size in the item.

The technical result is achieved by the fact that, in the known DOS device, the buffer layer is formed on a superlattice and has a composite structure of variable composition, the layer of the conducting channel is made of an unstressed narrow-gap semiconductor, the mesostructure contains two arrays with a certain number of vertically and laterally ordered quantum dots of a given size, each of which is in a layer of wide-gap semiconductor of various composition.

To achieve the required technical result, a DOSE memory element consisting of a semi-insulating semiconductor substrate on which an inverted structure of a selectively doped heterostructure transistor is formed, containing a buffer layer of an undoped semiconductor, a first undoped barrier layer of a wide-gap semiconductor, an alloyed delta-layer, a second undoped wide-gap barrier layer conducting undoped layer of narrow-gap elastically strained semi a conductor, a third undoped barrier layer of a wide-gap semiconductor, drain and source regions and metallized contacts to them, on which a mesostructure is formed between the drain and source regions, containing an array of quantum dots from an undoped narrow-gap semiconductor between the barrier layers of an undoped wide-gap semiconductor to which a metallized contact is formed with Schottky barrier of the control electrode (gate), superlattice, buffer layer with a composite structure of variable co Av, conducting channel layer of unstressed narrow bandgap semiconductor mesostructure with two arrays with a number of vertically and laterally ordered quantum dots of a predetermined size, each of which is in the wide-gap semiconductor layer of different composition.

In figure 1. the cross section of the proposed memory element DOSE. Figure 2. The topology of the mesostructure with an array of ordered quantum dots of a given size is given.

The DOS memory element (Fig. 1) contains a semi-insulating semiconductor substrate 1 on which an inverted SLGT structure is formed, consisting of a superlattice 2, a composite buffer of variable composition 3, undoped barrier layers 4, 6, 8 of a wide-gap semiconductor of the same composition, between which an alloying delta is formed -layer 5 and a layer of channel 7 made of undoped narrow-gap unstressed semiconductor, source 9 and drain regions 10, metallized contacts 11, 12 to them, between which an ana mesostructure with two arrays of laterally and vertically ordered quantum dots of a given size 13, 15, made of an undoped narrow-gap semiconductor of the same composition, in undoped wide-gap semiconductor layers of different composition 14, 16, and the band gap of the material of layer 16 is much smaller than the material of layer 14, on top of which a barrier layer of a wide-gap semiconductor 17 is formed, to which a metallized contact 18 with a Schottky barrier of the control electrode is formed ( ora).

The storage element works as follows.

When applying to the gate 18 on the surface of the barrier layer 17 an inverted SLGT structure formed on a substrate 1 with a superlattice 2 and a composite buffer 3, the first positive voltage pulse of such a magnitude that equalizes the energy level in the quantum dots of array 13 and the Fermi level in channel 7, the number of carriers, determined by the number of quantum dots in array 13, from the DEG layer formed in channel 7 by passing through the barrier 6 carriers from the delta layer 5 located between the barriers 4, 6, tunnels through arer 8 to level in the quantum dots of the array 13, forming there a localized charge a certain value, whereby the current between the source region 9 and drain 10 through the contacts 11, 12 is reduced by the simultaneous reduction of the carrier concentration in the channel 7 increases, and the Coulomb scattering; when a second positive voltage pulse is applied to the gate 18, such that the energy level in the quantum dots of array 15 and the Fermi level in channel 7 are aligned, the number of carriers, determined by the number of quantum dots in array 15, tunnels through the barriers 8 from the DEG layer in channel 7 , 14 per level in the quantum dots of array 15, forming there a localized charge of a certain value, as a result of which the current between the areas of the source 9 and drain 10 decreases by an even larger amount; The recorded information is reset by supplying a long pulse of negative voltage to the gate 18, as a result of which all carriers from the quantum dots of arrays 13, 15 go into the DEG layer of channel 7, increasing the current between the areas of source 9 and drain 10 through contacts 11, 12 due to the simultaneous an increase in the carrier concentration in channel 7 and a decrease in Coulomb scattering.

Thus, the proposed device is a DOS memory element that allows for electrically controlled recording, short-term storage and reading of an electric charge in one functionally integrated structure. The introduction into the structure of an element of a superlattice 2, a composite buffer 3, two arrays of laterally and vertically ordered quantum dots 13, 15, in undoped wide-gap semiconductor layers of various compositions 14, 16 allows to increase the speed, noise immunity, information recording density, reduce the power consumption and operating voltage of the device.

Thus, in comparison with similar devices, the proposed storage element allows to reduce the size of the storage element, reduce power consumption and operating voltage, increase noise immunity and simplify the manufacturing process.

Claims (1)

A memory element of dynamic random access memory (DOS), consisting of a semi-insulating semiconductor substrate, on which an inverted structure of a selectively doped heterostructured transistor is formed, containing a buffer layer of an undoped semiconductor, a first undoped barrier layer of a wide-gap semiconductor, an alloyed delta layer, a second undoped semiconductor wide-gap barrier layer conducting undoped layer of narrow-gap elastically stressed semiconductor ka, the third undoped barrier layer of a wide-gap semiconductor, drain and source regions and metallized contacts to them, on which a mesostructure is formed between the drain and source regions, containing an array of quantum dots from an undoped narrow-gap semiconductor between the barrier layers of an undoped wide-gap semiconductor to which a metallized contact is formed with Schottky barrier of the control electrode (gate), characterized in that the buffer layer is formed on the superlattice and has a composite trukturu variable composition, conducting channel layer formed of a narrow bandgap semiconductor unstressed, mesostructure comprises two arrays with a number of vertically and laterally ordered quantum dots of a predetermined size.