RU100689U1 - ANTI-PHASE PULSE FORMATOR IC - Google Patents

Abstract

 Integrated microcircuit of an antiphase pulse generator containing a low-power reference frequency generator; a counting trigger that generates antiphase meander pulses for controlling output power transistors, characterized in that the logic elements 2OR-NOT and Schmitt triggers connected to the antiphase channel and allowing the channel to turn on after switching off the antiphase are introduced into the control structure of the output transistors of each channel.

Description

The invention relates to a pulsed technique and can be used as a generator of antiphase pulses for an inductive load, in particular a transformer of a DC-DC converter.

Known integrated circuits MAX253 (1994 Maxim Integrated Products, http://www.maxim-ic.com) and MAX845 (1997 Maxim Integrated Products, http://www.maxirn-ic.com) containing an economical integrated oscillator with high duty cycle reference frequency, the division of which by a counting trigger provides inverse signals at the outputs of the trigger. These signals connected to the gates of n-MOS transistors provide control of the transformer of the DC-DC converter with out-of-phase signals.

The disadvantage of these microcircuits is the coincidence in time of the front and the fall of antiphase signals, which at the moment of this coincidence leads to the passage of through current through the transformer and the release of stray power.

Closest to the claimed technical solution is the KR1211EU1 integrated circuit selected as a prototype (Microcircuits for switching power supplies. - M., Dodeka, 2000, p. 269-272). The chip, in addition to an economical built-in generator with a large duty cycle of the reference frequency, includes a divider built on several countable triggers. Additional logic elements allow you to translate both antiphase outputs when changing phases to a state of low logic level, which avoids the passage of through current through a transformer and the release of stray power. The disadvantage of this scheme is the presence of a certain duration of a pause between antiphase signals, leading to a drop in the efficiency of the DC-DC converter.

The technical result achieved by the implementation of this utility model is the exclusion of the passage of stray current through the transformer and the optimization of efficiency due to automatic tracking of the switching of antiphase channels.

The specified technical result is achieved by introducing a pair of additional Schmitt triggers connected by an input to the antiphase output and an output to the logic that controls the n-MOS channel transistor. According to a utility model, this trigger prohibits the inclusion of a channel until the antiphase is turned off.

Figure 1 presents the structural electrical circuit of the integrated circuit of the driver of antiphase signals.

The driver integrated circuit includes a reference frequency generator I; counting trigger II; two logic elements 2OR-NOT III and IV, controlling two output n-MOS transistors V and VI, connected to the transformer windings VII and VIII; two inverting triggers Schmit IX and X, connected between the antiphase outputs and logic elements 2 OR NOT III and IV according to figure 1.

The reference frequency of a large duty cycle is formed by the reference frequency generator I (bus 1), which provides its own low current consumption of the built-in generator.

The counting trigger II converts by dividing the reference frequency into two signals into two antiphase meander types at the inverse outputs of the trigger (buses 2 and 3).

The element 2 OR NOT IV generates a positive pulse on bus 5, which opens the n-MOS transistor VI and transfers bus 7 to a low logic level (current flows through the winding of transformer VIII).

At the next clock pulse of the reference frequency generator I, a negative pulse is generated on bus 2, but the 2OR-NOT III element will generate a positive pulse on bus 4 only after exceeding the positive threshold value of the Schmit trigger IX on bus 7 (accordingly, a low logic level will be formed on bus 8). After that, the n-MOS transistor V opens, transferring bus 6 to a low logic level (current flows through the second winding of transformer VII).

Thus, the possibility of simultaneous opening of n-MOS transistors and the passage of through-pass stray current in the windings is excluded, at the same time, the delay in turning on the n-MOS transistor is determined only by the turn-off time of the antiphase channel and minimizes the overall efficiency of the device.

Claims (1)

Integrated microcircuit of an antiphase pulse generator containing a low-power reference frequency generator; a counting trigger that generates antiphase meander pulses for controlling output power transistors, characterized in that the logic elements 2OR-NOT and Schmitt triggers connected to the antiphase channel and allowing the channel to turn on after switching off the antiphase are introduced into the control structure of the output transistors of each channel.