RU100349U1 - DEVICE PROCESSING DEVICE FOR SIGNAL SIGNAL WITH HIGH NOISE RESISTANCE WITHOUT PRELIMINARY SYNCHRONIZATION - Google Patents

Abstract

 A device for processing a high frequency noise-frequency interference-frequency signal without preliminary synchronization, containing a signal multiplier, bandpass filters, quadratic detectors, integrators, keys, the first input of the signal multiplier is the device input, the output of the signal multiplier is connected to the inputs of the bandpass filters in k channels, the outputs of the bandpass filters are connected to the inputs of quadratic detectors, the outputs of quadratic detectors are connected to the inputs of integrators, the outputs of integrators are connected to the first inputs of the keys, and the second key inputs are supplied with a “Sampling” signal, characterized by the additional input of the reference generator, the output of the reference generator is connected to the second input of the signal multiplier, k shift registers in the channels, the inputs of the shift registers are connected to the key outputs, the channel switching circuit, the first inputs of the channel switching circuit are connected with the outputs of the shift registers, the source of the connection number of the outputs of the channel registers, the k outputs of the source of the connection number of the outputs of the channel registers are connected to the second k inputs of cx We channel switching, the adder, the adder m inputs are connected to the m output channels scheme switching threshold device, the threshold device input connected to the output of the adder, the output of the threshold device is an output device.

Description

The utility model relates to the field of digital filtering of binary sequences and is intended for digital processing of broadband signals (SHPS) with programmable switching of working frequencies (PFC) in control equipment for various purposes.

When transmitting information in the conditions of radio interference, to increase the noise immunity of the communication channel, signals with programmable switching of operating frequencies are used. Reducing the effectiveness of electronic countermeasures is achieved by transmitting information at different frequencies, switched by an algorithm unknown to the enemy.

High-quality processing of the frequency hopping signal with a known frequency switching sequence assumes, in addition to the agreed filtering, the presence of a synchronizer for searching in time the signal arrives.

With a random nature of the frequency switching for receiving a signal, it is necessary to synchronize the operation of the receiver both in time and in frequency. This process is quite time-consuming, time-consuming, which is unacceptable for electronic means operating with short signals.

The disadvantages of processing frequency hopping signals using various synchronization schemes are either the long duration of the synchronization process with a step-by-step algorithm for operating a single-channel synchronizer, or the complexity of the technical implementation of a multi-channel synchronizer with a parallel search for the beginning of a signal with a large base.

The closest in technical essence to the claimed device is the selected device as a prototype for processing an M-ary FM signal with frequency coding and spacing, including a signal multiplier (PM), the first input of which is the device input, the second input of the signal multiplier is connected to the output of the synthesizer frequency (MF), the input of the frequency synthesizer is connected to the output of the pseudo-random code generator (GPSC), the output of the signal multiplier (PM) is connected to the inputs of k - channels, in each of which the output p a signal multiplier (PM) is connected to the input of the bandpass filter (PF), the output of the bandpass filter is connected to the input of the quadratic detector (CD), the output of the quadratic detector is connected to the input of the integrator (INT), the output of the integrator is connected to the first input of the key (CL), to the second the key input is the signal "Sampling", the key output is connected to the corresponding input k - input maximum selection circuit (CBM), the output of the maximum selection circuit is connected to the input of the diversity symbol adding circuit (CPC), the output of the diversity symbol adding circuit is connected to about the input of the M-binary binary converter (MIS), the output of the M-binary binary converter is connected to the input of the decoder (DC), the output of which is the output of the device (Borisov V.I., Zinchuk V.M., Limarev A.E. and others. "Interference immunity of radio communication systems with the expansion of the spectrum of signals by the method of pseudo-random tuning of the operating frequency" - M .: Radio and communication, 2000. - 384 p.).

The most significant drawback of this device is the need to pre-synchronize the received frequency hopping signal with the operation of the pseudo-random code generator and reduce the noise immunity of the device due to the decision in the channels for one element, which is characterized by the partial use of signal energy at all switched frequencies.

The technical result of the utility model is the processing of frequency hopping signals without prior synchronization while increasing the noise immunity of the device.

This technical result is achieved by the fact that in the processing device of the M-ary FM signal with encoding and spacing of characters in frequency, instead of a pseudo-random code generator (GPSC) and a frequency synthesizer (MF), a reference generator (OG) is introduced, the output of which is connected to the second input of the multiplier ( PM), instead of maximum selection circuits (CBM), diversity diversity addition (CDS), M-binary-binary converter and decoder, shift registers (RG) are introduced by the number of k channels, a channel switching circuit (CC), the first inputs of which are connected with the outputs of the shift registers, the second inputs are connected to the k outputs of the source circuit of the connection number of the outputs of the channel register (HBP), the outputs of the channel switching circuit are connected to the k inputs of the adder (SUM), the output of the adder is connected to the input of the threshold device (GTU), the output of which is the output devices.

Figure 1 presents a diagram of a device for processing a frequency hopping signal with high noise immunity without preliminary synchronization, containing a signal multiplier 1, a reference oscillator 2, in each of the k channels a bandpass filter 3, a quadratic detector 4, an integrator 5, a key 6 shifting n-bit register 7, k is the input circuit of the switching channels 8, k is the output source of the connection number of the outputs of the register 9, m input adder 10, the threshold device 11.

The device processing the frequency hopping signal with high noise immunity without prior synchronization works as follows. The information elements of the frequency hopping signal are fed to the first input of the signal multiplier 1. The signal from the reference generator 2 is fed to the second input of the signal multiplier. The frequency difference of the input frequency multiplier signal and the reference oscillation ensures that the signal from the output of the signal multiplier falls into the passband of one of the k channel bandpass filters 3. The signal from the output of the band-pass filter, consistent with the duration of the information element, passes through a quadratic detector 4, the integrator 5 and the generated video signal I strobed using key 6 on the signal "Sample". The samples of the signal are fed to the input of the shift register 7 with the number of bits n = q × m, where q is the number of samples per information element, m is the number of information elements in the code combination. With m outputs of the register (in steps of q), the signals are fed to the first inputs of the circuit switching circuit of channels 8, the second inputs receive signals from the source of the connection number of the outputs of the channel register 9.

Figure 2 shows a schematic implementation of the source of the connection number of the outputs of the channel register and circuit switching channels for channel 1, the circuits for the remaining channels are similar, the m-outputs of the shift register of the first channel (WG 1 channel) are connected to the first m-inputs of the keys (KL 1 - CR m). The second m-inputs of the keys are connected to the m-outputs of the register of the number of the connected output (WG nom. Output 1 channel) of the shift register (WG 1 channel). The code combination determining the presence of “1” at only one of the register outputs is entered into the register of the number of the connected output (RG number output. 1 channel) by a pre-parallel code (for the variant in Fig. 2 this is the second output of the register). The presence of this “1” will only open the KL2 key, which determines the passage to the output of the signal from the second output of the shift register (WG 1 channel). The outputs of all keys are combined by an OR circuit. To select a different number of the switched output of the shift register (WG 1 channel) it is enough to change the code combination in the register (WG nom. Output 1 channel) from “1” on the other output. A key collection (CL) and an OR circuit are part of a switching circuit for the first channel. The signal from the output of the OR circuit is fed to the input of the adder 10.

In Fig. 1, from the output of the source of the connection number of the outputs of the channel register, only one output for switching in each channel is conventionally shown, which corresponds only to the output of the register (RG number output 1 channel) with a high level of "1" and the switched output 2 of the shift register (WG 1 can.). From the m outputs of the channel switching circuit, the signals simultaneously arrive at the m inputs of the adder 10 and from its output to the threshold device 11. If the number of channels k and the number of information symbols of the frequency hopping signal are equal, the number of outputs of the channel switching circuit and the inputs of the adder m = k. When m> k, the channels will be re-switched, and more than one shift register output will be switched by the channel switching circuit, therefore, the total number of channel switching circuit outputs will be m> k.

As a result, the circuit of switching channels 8, taking into account the programmable delays in shift registers 7, ensures the simultaneous appearance of information symbols on all m outputs, that is, the use of the energy of the entire m-bit code combination when making a decision, which determines a higher noise immunity of this device.

Checking the presence of the frequency hopping signal for each of q samples provides the search for the highest signal-to-noise ratio corresponding to the end of the information element at the output of the matched band-pass filter in the channel.

Thus, the proposed device provides reception of the frequency hopping signal without prior synchronization and has high noise immunity due to the use of its full energy during signal processing.

Information sources:

Borisov V.I., Zinchuk V.M., Limarev A.E. and others. "Interference immunity of radio communication systems with the expansion of the spectrum of signals by the method of pseudo-random tuning of the operating frequency" - M .: "Radio and communication", 2000. - 384 p.

Claims (1)

A device for processing a high frequency noise-frequency interference-frequency signal without preliminary synchronization, containing a signal multiplier, bandpass filters, quadratic detectors, integrators, keys, the first input of the signal multiplier is the device input, the output of the signal multiplier is connected to the inputs of the bandpass filters in k channels, the outputs of the bandpass filters are connected to the inputs of quadratic detectors, the outputs of quadratic detectors are connected to the inputs of integrators, the outputs of integrators are connected to the first inputs of the keys, and the second key inputs are supplied with a “Sampling” signal, characterized by the additional input of the reference generator, the output of the reference generator is connected to the second input of the signal multiplier, k shift registers in the channels, the inputs of the shift registers are connected to the key outputs, the channel switching circuit, the first inputs of the channel switching circuit are connected with the outputs of the shift registers, the source of the connection number of the outputs of the channel registers, the k outputs of the source of the connection number of the outputs of the channel registers are connected to the second k inputs of cx We channel switching, the adder, the adder m inputs are connected to the m output channels scheme switching threshold device, the threshold device input connected to the output of the adder, the output of the threshold device is an output device.