RO91571B1 - Circuit integrat logic - Google Patents
Circuit integrat logicInfo
- Publication number
- RO91571B1 RO91571B1 RO116344A RO11634484A RO91571B1 RO 91571 B1 RO91571 B1 RO 91571B1 RO 116344 A RO116344 A RO 116344A RO 11634484 A RO11634484 A RO 11634484A RO 91571 B1 RO91571 B1 RO 91571B1
- Authority
- RO
- Romania
- Prior art keywords
- outputs
- output
- integrated circuit
- decoder
- type
- Prior art date
Links
Landscapes
- Digital Computer Display Output (AREA)
Abstract
Inventia se refera la un circuit integrat logic în tehnologie I2L, destinat utilizarii în aparatura electronica pentru comanda afisarii numerice. Circuitul conform inventiei cuprinde un numarator final, o memorie si un decodor, numaratorul zecimal fiind un numarator sincron reversibil, la care sînt acesibile intrarea de ceas a primului bistabil, intrarea de stergere, iesirea de transport/împrumut, iesirile sale fiind conectate la patru memorii realizate cu bistabile de tip D cu iesirea de transfer scoasa pe un terminal, iar decodorul fiind de tip BCD-7 segmente si prelucreaza datele de iesirea memoriilor si le transmite unui grup de sapte circuite de tip SAU-EXCLUSIV avînd cîte o intrare legata împreuna si scoasa pe un terminal, cu iesirile conectate la circuitele de interfata pentru comanda dispozitivelor de afisare.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| RO116344A RO91571B1 (ro) | 1984-11-20 | 1984-11-20 | Circuit integrat logic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| RO116344A RO91571B1 (ro) | 1984-11-20 | 1984-11-20 | Circuit integrat logic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| RO91571A2 RO91571A2 (ro) | 1987-04-30 |
| RO91571B1 true RO91571B1 (ro) | 1987-05-01 |
Family
ID=20115846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| RO116344A RO91571B1 (ro) | 1984-11-20 | 1984-11-20 | Circuit integrat logic |
Country Status (1)
| Country | Link |
|---|---|
| RO (1) | RO91571B1 (ro) |
-
1984
- 1984-11-20 RO RO116344A patent/RO91571B1/ro unknown
Also Published As
| Publication number | Publication date |
|---|---|
| RO91571A2 (ro) | 1987-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE3485527D1 (de) | Datenverarbeitungssystembus mit fehlerzyklusbetrieb. | |
| GB1366401A (en) | Three state logic device with appl'ions | |
| US3932734A (en) | Binary parallel adder employing high speed gating circuitry | |
| EP0033346B1 (en) | Incrementer/decrementer circuit | |
| GB1254722A (en) | Improved logical shifting devices | |
| GB1387882A (en) | Asynchronous buffer device | |
| GB1321026A (en) | Data processing device | |
| RO91571B1 (ro) | Circuit integrat logic | |
| US3544773A (en) | Reversible binary coded decimal synchronous counter circuits | |
| GB1279512A (en) | Improvements in or relating to emitter coupled logic circuits | |
| GB1569604A (en) | Key signal entry device | |
| ES437853A1 (es) | Perfeccionamientos en los aparatos telefonicos de pago. | |
| JPS5691534A (en) | Array logic circuit | |
| US3229117A (en) | Logical circuits | |
| SU961151A1 (ru) | Недвоичный синхронный счетчик | |
| ES403566A1 (es) | Memoria de apilamiento con indicacion de desbordamiento pa-ra transmision de datos en forma binaria en el orden crono- logico de su entrada. | |
| SU1596320A1 (ru) | @ -Входовый сумматор | |
| GB1448041A (en) | Data processing equipment | |
| SU392494A1 (ru) | I ВСЕСОЮЗНАЯ|j;rn-:-fVi|O.TF)inHMFnMMАвторыЗа вительКиевска экспедици Украинского научно-исследовательскогогеологоразведоуного институтаSHSJiHOTEKA | |
| GB1131958A (en) | Binary adder | |
| FR2357979A1 (fr) | Memoire pour ordinateur | |
| SU374643A1 (ru) | Реверсивный десятичный счетчик | |
| JPS61288636A (ja) | フレ−ム変換回路 | |
| JP2719071B2 (ja) | タイミング制御信号発生回路 | |
| GB1499742A (en) | Interface adaptor circuits in combination with a processo |